summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper2012-03-085-12/+12
| | | | llvm-svn: 152301
* [ADT] Change the trivial FoldingSetNodeID::Add* methods to be inline, reappliedDaniel Dunbar2012-03-081-43/+1
| | | | | | with a fix for the longstanding over-read of 32-bit pointer values. llvm-svn: 152300
* Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012:Stepan Dyatkovskiy2012-03-0822-127/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120130/136146.html Implemented CaseIterator and it solves almost all described issues: we don't need to mix operand/case/successor indexing anymore. Base iterator class is implemented as a template since it may be initialized either from "const SwitchInst*" or from "SwitchInst*". ConstCaseIt is just a read-only iterator. CaseIt is read-write iterator; it allows to change case successor and case value. Usage of iterator allows totally remove resolveXXXX methods. All indexing convertions done automatically inside the iterator's getters. Main way of iterator usage looks like this: SwitchInst *SI = ... // intialize it somehow for (SwitchInst::CaseIt i = SI->caseBegin(), e = SI->caseEnd(); i != e; ++i) { BasicBlock *BB = i.getCaseSuccessor(); ConstantInt *V = i.getCaseValue(); // Do something. } If you want to convert case number to TerminatorInst successor index, just use getSuccessorIndex iterator's method. If you want initialize iterator from TerminatorInst successor index, use CaseIt::fromSuccessorIndex(...) method. There are also related changes in llvm-clients: klee and clang. llvm-svn: 152297
* Revert r152288, "[ADT] Change the trivial FoldingSetNodeID::Add* methods to beDaniel Dunbar2012-03-081-1/+43
| | | | | | inline.", which is breaking the bots in a way I don't understand. llvm-svn: 152295
* Invoke setTargetDAGCombine for SELECT.Akira Hatanaka2012-03-081-0/+1
| | | | llvm-svn: 152290
* [ADT] Change the trivial FoldingSetNodeID::Add* methods to be inline.Daniel Dunbar2012-03-081-43/+1
| | | | llvm-svn: 152288
* Swap the operands of a select node if the false (the second) operand is 0.Akira Hatanaka2012-03-081-0/+35
| | | | | | | | | | | | For example, this pattern (select (setcc lhs, rhs, cc), true, 0) is transformed to this one: (select (setcc lhs, rhs, inverse(cc)), 0, true) This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to replace 0 with $zero. llvm-svn: 152285
* Rotate two of the functions used to count bonuses for the inline costChandler Carruth2012-03-081-14/+10
| | | | | | | | | | | | | analysis to be methods on the cost analysis's function info object instead of the code metrics object. These really are just users of the code metrics, they're building the information for the function's analysis. This is the first step of growing the amount of information we collect about a function in order to cope with pair-wise simplifications due to allocas. llvm-svn: 152283
* Set minimum function alignment to 3 if target is Mips64.Akira Hatanaka2012-03-081-1/+1
| | | | llvm-svn: 152282
* This patch eliminates redundant instructions that produce 0.Akira Hatanaka2012-03-081-1/+50
| | | | | | | | | | | | For example, the first instruction in the code below can be eliminated if the use of $vr0 is replaced with $zero: addiu $vr0, $zero, 0 add $vr2, $vr1, $vr0 add $vr2, $vr1, $zero llvm-svn: 152280
* misched interface: Expose the MachineScheduler pass.Andrew Trick2012-03-081-144/+102
| | | | | | | | Allow targets to provide their own schedulers (subclass of ScheduleDAGInstrs) to the misched pass. Select schedulers using -misched=... llvm-svn: 152278
* ARM don't use MCRelaxAll, as it's not safe on ARM.Jim Grosbach2012-03-081-2/+2
| | | | | | | | | The ARM code generator makes aggressive assumptions about the encodings being selected for branches which MCRelaxAll invalidates. rdar://11006355 llvm-svn: 152268
* Improved support in RuntimeDyldMachO for generatingSean Callanan2012-03-072-22/+69
| | | | | | | | | | | code that will be relocated into another memory space. Now when relocations are resolved, the address of the relocation in the host memory (where the JIT is) is passed separately from the address that the relocation will be at in the target memory (where the code will run). llvm-svn: 152264
* Cleanup VLIWPacketizer to use the updated ScheduleDAGInstrs interface.Andrew Trick2012-03-071-18/+12
| | | | llvm-svn: 152262
* misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick2012-03-075-343/+4
| | | | | | implement their own MachineScheduler. llvm-svn: 152261
* misched prep: Remove LLVM_LIBRARY_VISIBILITY from ScheduleDAGInstrs.Andrew Trick2012-03-071-2/+2
| | | | llvm-svn: 152260
* misched prep: Comment the ScheduleDAGInstrs interface.Andrew Trick2012-03-072-9/+15
| | | | llvm-svn: 152259
* misched prep: Cleanup ScheduleDAGInstrs interface.Andrew Trick2012-03-072-75/+81
| | | | | | | | ScheduleDAGInstrs will be the main interface for MI-level schedulers. Make sure it's readable: one page of protected fields, one page of public methids. llvm-svn: 152258
* misched prep: remove extra "protected"Andrew Trick2012-03-071-2/+0
| | | | llvm-svn: 152257
* misched prep: rename InsertPos to End.Andrew Trick2012-03-074-22/+20
| | | | | | ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted. llvm-svn: 152256
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-0712-101/+101
| | | | | | | We had half the API with one convention, half with another. Now was a good time to clean it up. llvm-svn: 152255
* Copy the right amount of elements.Benjamin Kramer2012-03-071-3/+5
| | | | llvm-svn: 152254
* SmallPtrSet: Copy all the elements when swapping, not just numelements.Benjamin Kramer2012-03-071-5/+4
| | | | | | | This fixes a build failure in webkit. Copying all elements shouldn't be necessary, I'll look out for a better fix soon. llvm-svn: 152252
* [fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point Chad Rosier2012-03-071-4/+2
| | | | | | | condition flags to CPSR. This allows us to simplify SelectCmp. Patch by Zonr Chang <zonr.xchg@gmail.com>. llvm-svn: 152243
* Fix infinite loop in nested multiclasses.Jakob Stoklund Olesen2012-03-071-6/+2
| | | | | | Patch by Michael Liao! llvm-svn: 152232
* Try to clarify this comment some.Chandler Carruth2012-03-071-4/+7
| | | | llvm-svn: 152221
* Remove another outbreak of customized (and completely broken) hashing.Chandler Carruth2012-03-071-20/+24
| | | | | | | | | | | | | | | This one is particularly annoying because the hashing algorithm is highly specialized, with a strange "equivalence" definition that subsets the fields involved. Still, this looks at the exact same set of data as the old code, but without bitwise or-ing over parts of it and other mixing badness. No functionality changed here. I've left a substantial fixme about the fact that there is a cleaner and more principled way to do this, but it requires making the equality definition actual stable for particular types... llvm-svn: 152218
* Where the BranchFolding pass removes a branch then adds another better branch,Bill Wendling2012-03-071-4/+27
| | | | | | | | the DebugLoc information can be maintained throughout by grabbing the DebugLoc before the RemoveBranch and then passing the result to the InsertBranch. Patch by Andrew Stanford-Jason! llvm-svn: 152212
* Fix cmakeAndrew Trick2012-03-071-1/+0
| | | | llvm-svn: 152210
* commentAndrew Trick2012-03-071-0/+2
| | | | llvm-svn: 152209
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-079-90/+153
| | | | | | | | | | | | | | | | | | | ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. llvm-svn: 152208
* ScheduleDAGInstrs commentsAndrew Trick2012-03-071-0/+2
| | | | llvm-svn: 152207
* misched preparation: modularize schedule emission.Andrew Trick2012-03-076-108/+87
| | | | | | ScheduleDAG has nothing to do with how the instructions are scheduled. llvm-svn: 152206
* misched preparation: modularize schedule printing.Andrew Trick2012-03-075-17/+35
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152205
* misched preparation: modularize schedule verification.Andrew Trick2012-03-077-14/+34
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152204
* whitespaceAndrew Trick2012-03-071-5/+5
| | | | llvm-svn: 152203
* Switch this code to use hash_combine_range rather than incremental callsChandler Carruth2012-03-071-8/+6
| | | | | | | | | | to hash_combine. One of the interfaces could already do this, and the other can just use a small buffer. This is a much more efficient way to use the hash_combine interface, although I don't have any particular benchmark where this code was hot, so I can't measure much of an impact. It at least doesn't slow anything down. llvm-svn: 152200
* Cache the sized-ness of struct types, once we reach the steady state ofChandler Carruth2012-03-071-10/+21
| | | | | | | | | | | | | | | "is sized". This prevents every query to isSized() from recursing over every sub-type of a struct type. This could get *very* slow for extremely deep nesting of structs, as in 177.mesa. This change is a 45% speedup for 'opt -O2' of 177.mesa.linked.bc, and likely a significant speedup for other cases as well. It even impacts -O0 cases because so many part of the code try to check whether a type is sized. Thanks for the review from Nick Lewycky and Benjamin Kramer on IRC. llvm-svn: 152197
* No functionality change. Type::isSized() can be expensive, so avoid calling itNick Lewycky2012-03-071-8/+10
| | | | | | until after other inexpensive tests. llvm-svn: 152195
* ARM pre-v6 assembly parsing for umull/smull.Jim Grosbach2012-03-071-0/+10
| | | | llvm-svn: 152188
* ARM pre-v6 alias for 'nop' to 'mov r0, r0'Jim Grosbach2012-03-071-0/+4
| | | | llvm-svn: 152185
* Tidy up. Remove dead code that slipped into previous commit.Jim Grosbach2012-03-071-6/+0
| | | | llvm-svn: 152184
* Added -view-background to avoid waiting for each GraphViz invocation.Andrew Trick2012-03-071-39/+40
| | | | | | GV and XDOT paths are untested but should work the same. llvm-svn: 152179
* Added -view-misched=dags options.Andrew Trick2012-03-071-0/+9
| | | | llvm-svn: 152178
* Cleanup in preparation for misched: Move DAG visualization logic.Andrew Trick2012-03-075-9/+23
| | | | | | Soon, ScheduleDAG will not refer to the BB. llvm-svn: 152177
* Added MachineBasicBlock::getFullName() to standardize/factor codegen ↵Andrew Trick2012-03-071-0/+12
| | | | | | diagnostics. llvm-svn: 152176
* whitespaceAndrew Trick2012-03-072-6/+6
| | | | llvm-svn: 152175
* Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ↵Andrew Trick2012-03-072-2/+2
| | | | | | the target interface. llvm-svn: 152174
* misched commentsAndrew Trick2012-03-071-0/+2
| | | | llvm-svn: 152173
* misched: Use the StartBlock/FinishBlock hooksAndrew Trick2012-03-071-0/+2
| | | | llvm-svn: 152172
OpenPOWER on IntegriCloud