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* Joining a live interval of a physical register with a virtual one can turn outEvan Cheng2007-03-171-0/+54
| | | | | | | | | | | | to be really bad. Once they are joined they are not broken apart. Also, physical intervals cannot be spilled! Added a heuristic as a workaround for this. Be careful coalescing with a physical register if the virtual register uses are "far". Check if there are uses in the same loop as the source (copy instruction). Check if it is in the loop preheader, etc. llvm-svn: 35134
* Use SmallSet instead of std::set.Evan Cheng2007-03-171-1/+1
| | | | llvm-svn: 35133
* If sdisel has decided to sink GEP index expression into any BB. Replace all usesEvan Cheng2007-03-171-22/+37
| | | | | | in that BB. llvm-svn: 35132
* Support 'I' inline asm constraint.Devang Patel2007-03-171-0/+11
| | | | llvm-svn: 35129
* Only ARMv6 has BSWAP.Lauro Ramos Venancio2007-03-161-0/+4
| | | | | | Fix MultiSource/Applications/aha test. llvm-svn: 35128
* Turn on GEP index sinking by default.Evan Cheng2007-03-161-7/+0
| | | | llvm-svn: 35127
* Stupid bug.Evan Cheng2007-03-161-1/+1
| | | | llvm-svn: 35126
* And now support for MMX logical operations.Bill Wendling2007-03-162-2/+54
| | | | llvm-svn: 35125
* Sink a binary expression into its use blocks if it is a loop invariantEvan Cheng2007-03-161-0/+92
| | | | | | | computation used as GEP indexes and if the expression can be folded into target addressing mode of GEP load / store use types. llvm-svn: 35123
* Added isLegalAddressExpression(). Only allows X +/- C for now.Evan Cheng2007-03-162-0/+21
| | | | llvm-svn: 35122
* Added isLegalAddressExpression hook to test if the given expression can beEvan Cheng2007-03-161-0/+8
| | | | | | folded into target addressing mode for the given type. llvm-svn: 35121
* Add more comments and update to new asm syntax.Nick Lewycky2007-03-161-28/+130
| | | | | | | | | | Add new micro-optimizations. Add icmp predicate snuggling. Given %x ULT 4, "icmp ugt %x, 2" becomes "icmp eq %x, 3". This doesn't apply in any non-trivial cases yet due to missing support for NE values in ValueRanges. llvm-svn: 35119
* Multiplication support for MMX.Bill Wendling2007-03-152-1/+9
| | | | llvm-svn: 35118
* Debugging output stuff.Evan Cheng2007-03-151-4/+4
| | | | llvm-svn: 35117
* Estimate a cost using the possible number of scratch registers required and useEvan Cheng2007-03-141-9/+47
| | | | | | | | | | it as a late BURR scheduling tie-breaker. Intuitively, it's good to push down instructions whose results are liveout so their long live ranges won't conflict with other values which are needed inside the BB. Further prioritize liveout instructions by the number of operands which are calculated within the BB. llvm-svn: 35109
* Under X86-64 large code model, do not emit 32-bit pc relative calls.Evan Cheng2007-03-141-3/+5
| | | | llvm-svn: 35108
* Notes about codegen issues.Evan Cheng2007-03-141-0/+47
| | | | llvm-svn: 35107
* Clean up.Evan Cheng2007-03-141-3/+4
| | | | llvm-svn: 35105
* Oops.Evan Cheng2007-03-141-1/+1
| | | | llvm-svn: 35104
* X86-64 JIT is in large code model. Need stubs for direct calls.Evan Cheng2007-03-141-1/+1
| | | | llvm-svn: 35097
* x86-64 JIT stub codegen.Evan Cheng2007-03-141-0/+11
| | | | llvm-svn: 35096
* Preliminary support for X86-64 JIT stub codegen.Evan Cheng2007-03-141-3/+35
| | | | llvm-svn: 35095
* ShiftAmt might equal to zero. Handle this situation.Zhou Sheng2007-03-141-7/+9
| | | | llvm-svn: 35094
* Enable KnownZero/One.clear().Zhou Sheng2007-03-141-2/+2
| | | | llvm-svn: 35093
* Try schedule def + use closer whne Sethi-Ullman numbers are the same.Evan Cheng2007-03-131-6/+38
| | | | | | | | | | | | | | | | | | | | | e.g. t1 = op t2, c1 t3 = op t4, c2 and the following instructions are both ready. t2 = op c3 t4 = op c4 Then schedule t2 = op first. i.e. t4 = op c4 t2 = op c3 t1 = op t2, c1 t3 = op t4, c2 This creates more short live intervals which work better with the register allocator. llvm-svn: 35089
* AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2]Evan Cheng2007-03-131-0/+23
| | | | llvm-svn: 35088
* Zero is always a legal AM immediate.Evan Cheng2007-03-131-0/+3
| | | | llvm-svn: 35087
* Correct type info for isLegalAddressImmediate() check.Evan Cheng2007-03-131-12/+18
| | | | llvm-svn: 35086
* Stack and register alignment of call arguments in the ELF ABINicolas Geoffray2007-03-131-6/+52
| | | | llvm-svn: 35083
* ifdef out some dead code.Chris Lattner2007-03-131-2/+8
| | | | | | Fix PR1244 and Transforms/InstCombine/2007-03-13-CompareMerge.ll llvm-svn: 35082
* For expression likeZhou Sheng2007-03-131-3/+3
| | | | | | | | "APInt::getAllOnesValue(ShiftAmt).zextOrCopy(BitWidth)", to handle ShiftAmt == BitWidth situation, use zextOrCopy() instead of zext(). llvm-svn: 35080
* In APInt version ComputeMaskedBits():Zhou Sheng2007-03-131-15/+28
| | | | | | | 1. Ensure VTy, KnownOne and KnownZero have same bitwidth. 2. Make code more efficient. llvm-svn: 35078
* Implement getTargetLowering() or else LSR won't be using ARM specific hooks.Evan Cheng2007-03-132-1/+8
| | | | llvm-svn: 35077
* More flexible TargetLowering LSR hooks for testing whether an immediate is a ↵Evan Cheng2007-03-121-3/+13
| | | | | | legal target address immediate or scale. llvm-svn: 35076
* Updated TargetLowering LSR addressing mode hooks for ARM and Thumb.Evan Cheng2007-03-122-8/+88
| | | | llvm-svn: 35075
* More flexible TargetLowering LSR hooks for testing whether an immediate is a ↵Evan Cheng2007-03-122-5/+10
| | | | | | legal target address immediate or scale. llvm-svn: 35074
* More flexible TargetLowering LSR hooks for testing whether an immediate isEvan Cheng2007-03-122-16/+33
| | | | | | a legal target address immediate or scale. llvm-svn: 35073
* Use new TargetLowering addressing modes hooks.Evan Cheng2007-03-121-20/+18
| | | | llvm-svn: 35072
* Stupid bug: SSE2 supports v2i64 add / sub.Evan Cheng2007-03-121-0/+2
| | | | llvm-svn: 35070
* Revert the last patch as it violates the conditions of sext/zext.Reid Spencer2007-03-121-4/+0
| | | | llvm-svn: 35068
* Unbreak C++ build.Jeff Cohen2007-03-121-0/+1
| | | | llvm-svn: 35067
* Unbreak VC++ build. Do not use identifiers starting with _ as they are ↵Jeff Cohen2007-03-121-3/+3
| | | | | | | | reserved and can collide with system defined names. Windows defines _BB, for example. llvm-svn: 35066
* For APInt::z/sext(width), if width == BitWidth, just return *this.Zhou Sheng2007-03-121-0/+4
| | | | llvm-svn: 35065
* Add an APInt version of SimplifyDemandedBits.Reid Spencer2007-03-121-1/+524
| | | | | | Patch by Zhou Sheng. llvm-svn: 35064
* Add an APInt version of ShrinkDemandedConstant.Reid Spencer2007-03-121-0/+24
| | | | | | Patch by Zhou Sheng. llvm-svn: 35063
* Avoid to assert on "(KnownZero & KnownOne) == 0".Zhou Sheng2007-03-121-1/+1
| | | | llvm-svn: 35062
* In function ComputeMaskedBits():Zhou Sheng2007-03-121-6/+6
| | | | | | | | 1. Replace getSignedMinValue() with getSignBit() for better code readability. 2. Replace APIntOps::shl() with operator<<= for convenience. 3. Make APInt construction more effective. llvm-svn: 35060
* Add value ranges. Currently inefficient in both execution time andNick Lewycky2007-03-101-219/+397
| | | | | | optimization power. llvm-svn: 35058
* Use range tests in LowerSwitch, where possibleAnton Korobeynikov2007-03-101-31/+114
| | | | llvm-svn: 35057
* Add getter methods for the extremes of a ConstantRange.Nick Lewycky2007-03-101-0/+64
| | | | llvm-svn: 35056
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