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* [Sparc] Add fcmpe* instructions to Sparc backend.Venkatraman Govindaraju2014-03-023-6/+28
| | | | llvm-svn: 202661
* [Sparc] Add VIS instructions to sparc backend.Venkatraman Govindaraju2014-03-024-8/+290
| | | | llvm-svn: 202660
* Add a PPC inline asm constraint type for single CR bitsHal Finkel2014-03-021-0/+8
| | | | | | | | | | | | | | | | | Now that the PowerPC backend can track individual CR bits as first-class registers, we should also have a way of allocating them for inline asm statements. Because these registers are only one bit, if an output variable is implicitly cast to a larger integer size, we'll get an any_extend to that larger type (this is part of the existing target-independent logic). As a result, regardless of the size of the output type, only the first bit is meaningful. The constraint identifier "wc" has been chosen for this purpose. Although gcc does not currently support allocating individual CR bits, this identifier choice has been coordinated with the gcc PowerPC team, and will be marked as reserved for this purpose in the gcc constraints.md file. llvm-svn: 202657
* [C++11] Replace llvm::tie with std::tie.Benjamin Kramer2014-03-0222-73/+74
| | | | | | The old implementation is no longer needed in C++11. llvm-svn: 202644
* [C++11] Replace LLVM_STATIC_ASSERT with static_assert, we now haveChandler Carruth2014-03-021-2/+2
| | | | | | access to it on all host toolchains. llvm-svn: 202642
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-02126-445/+416
| | | | | | Remove the old functions. llvm-svn: 202636
* [SparcV9] Adds support for branch on integer register instructions (BPr) and ↵Venkatraman Govindaraju2014-03-028-1/+165
| | | | | | conditional moves on integer register (MOVr/FMOVr). llvm-svn: 202628
* AVX-512: Fixed extract_vector_elt for v8i1 vectorElena Demikhovsky2014-03-024-6/+14
| | | | llvm-svn: 202624
* Switch all uses of LLVM_OVERRIDE to just use 'override' directly.Craig Topper2014-03-0263-444/+409
| | | | llvm-svn: 202621
* Switch all uses of LLVM_FINAL to just use 'final', and remove the macro.Craig Topper2014-03-028-8/+8
| | | | llvm-svn: 202618
* [Sparc] Add support for parsing branches and conditional move instructions ↵Venkatraman Govindaraju2014-03-024-44/+89
| | | | | | with %fcc1-%fcc3 conditional registers. llvm-svn: 202616
* [Sparc] Make floating point branch instruction formats to accept %fcc0-%fcc1 ↵Venkatraman Govindaraju2014-03-024-34/+40
| | | | | | | | conditional registers as input. No functionality change. llvm-svn: 202614
* [C++11] Switch all uses of the llvm_move macro to use std::moveChandler Carruth2014-03-027-13/+13
| | | | | | directly, and remove the macro. llvm-svn: 202612
* [Sparc] Add support for parsing fcmp with %fcc registers.Venkatraman Govindaraju2014-03-028-12/+78
| | | | llvm-svn: 202610
* [C++11] Expand and eliminate the LLVM_ENUM_INT_TYPE() macroAlp Toker2014-03-022-2/+2
| | | | llvm-svn: 202607
* [Sparc] Add register class for floating point conditional flags (%fcc0 - %fcc3).Venkatraman Govindaraju2014-03-023-11/+16
| | | | llvm-svn: 202604
* [SparcV9] Add support for parsing branch instructions with prediction.Venkatraman Govindaraju2014-03-017-44/+156
| | | | llvm-svn: 202602
* Remove extra truncs/exts around i32 bit operations on PPC64Hal Finkel2014-03-011-12/+82
| | | | | | | | | | | | | | | | | | | | | | | | | This generalizes the code to eliminate extra truncs/exts around i1 bit operations to also do the same on PPC64 for i32 bit operations. This eliminates a fairly prevalent code wart: int foo(int a) { return a == 5 ? 7 : 8; } On PPC64, because of the extension implied by the ABI, this would generate: cmplwi 0, 3, 5 li 12, 8 li 4, 7 isel 3, 4, 12, 2 rldicl 3, 3, 0, 32 blr where the 'rldicl 3, 3, 0, 32', the extension, is completely unnecessary. At least for the single-BB case (which is all that the DAG combine mechanism can handle), this unnecessary extension is no longer generated. llvm-svn: 202600
* [Sparc] Add support for parsing annulled branch instructions.Venkatraman Govindaraju2014-03-017-13/+80
| | | | llvm-svn: 202599
* [Sparc] Add support for parsing sparcv9 instructions addc/subc/addccc/subccc.Venkatraman Govindaraju2014-03-014-7/+13
| | | | llvm-svn: 202598
* [Sparc] Add missing ALU instruction patterns.Venkatraman Govindaraju2014-03-011-0/+35
| | | | llvm-svn: 202597
* Make helper function static.Benjamin Kramer2014-03-011-2/+1
| | | | llvm-svn: 202596
* Now that we have C++11, turn simple functors into lambdas and remove a ton ↵Benjamin Kramer2014-03-0115-249/+97
| | | | | | | | of boilerplate. No intended functionality change. llvm-svn: 202588
* [C++11] Remove the use of LLVM_HAS_RVALUE_REFERENCES from the rest ofChandler Carruth2014-03-011-6/+0
| | | | | | the core LLVM libraries. llvm-svn: 202582
* [Sparc] Add support to decode unimp instruction.Venkatraman Govindaraju2014-03-011-2/+2
| | | | llvm-svn: 202581
* [C++11] Remove the R-value reference #if usage from the ADT and SupportChandler Carruth2014-03-013-8/+0
| | | | | | libraries. It is now always 1 in LLVM builds. llvm-svn: 202580
* [Sparc] Add support to decode negative simm13 operands in the sparc ↵Venkatraman Govindaraju2014-03-012-23/+36
| | | | | | disassembler. llvm-svn: 202578
* [Sparc] Add support for decoding call instructions in the sparc disassembler.Venkatraman Govindaraju2014-03-012-2/+24
| | | | llvm-svn: 202577
* [Sparc] Add support to disassemble sparc memory instructions.Venkatraman Govindaraju2014-03-013-19/+142
| | | | llvm-svn: 202575
* Add support for parsing sun-style section flags in ELFAsmParser.Venkatraman Govindaraju2014-03-011-6/+43
| | | | llvm-svn: 202573
* [Sparc] Implement writeNopData. Emit actual NOP instruction instead of just ↵Venkatraman Govindaraju2014-03-011-3/+8
| | | | | | filling with zeroes. llvm-svn: 202572
* [Sparc] Teach SparcAsmParser to emit correct relocations for PIC code.Venkatraman Govindaraju2014-03-012-3/+55
| | | | llvm-svn: 202571
* Fix RWMutex to be thread-safe when pthread_rwlock is not availableMark Seaborn2014-03-011-6/+14
| | | | | | | | | | | | | | lib/Support/RWMutex.cpp contains an implementation of RWMutex that uses pthread_rwlock, but when pthread_rwlock is not available (such as under NaCl, when using newlib), it silently falls back to using the no-op definition in lib/Support/Unix/RWMutex.inc, which is not thread-safe. Fix this case to be thread-safe by using a normal mutex. Differential Revision: http://llvm-reviews.chandlerc.com/D2892 llvm-svn: 202570
* [Sparc] 80 column rule. No functionality change.Venkatraman Govindaraju2014-03-011-1/+2
| | | | llvm-svn: 202565
* [Sparc] Add support for parsing directives in SparcAsmParser.Venkatraman Govindaraju2014-03-011-2/+48
| | | | llvm-svn: 202564
* [Sparc] Emit 'restore' instead of 'restore %g0, %g0, %g0'. This improves the ↵Venkatraman Govindaraju2014-03-012-0/+11
| | | | | | readability of the generated code. llvm-svn: 202563
* SpillPlacement: fix a bug in iterate.Manman Ren2014-02-281-2/+4
| | | | | | | | | | | Inside iterate, we scan backwards then scan forwards in a loop. When iteration is not zero, the last node was just updated so we can skip it. But when iteration is zero, we can't skip the last node. For the testing case, fixing this will save a spill and move register copies from hot path to cold path. llvm-svn: 202557
* Reflow isProfitableToMakeFastCCReid Kleckner2014-02-281-1/+2
| | | | llvm-svn: 202555
* Jumped the gun with r202551 and broke some bots that weren't yet C++11ified.Lang Hames2014-02-281-38/+38
| | | | | | Reverting until the C++11 switch is complete. llvm-svn: 202554
* New PBQP solver, and updates to the PBQP graph.Lang Hames2014-02-281-38/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous PBQP solver was very robust but consumed a lot of memory, performed a lot of redundant computation, and contained some unnecessarily tight coupling that prevented experimentation with novel solution techniques. This new solver is an attempt to address these shortcomings. Important/interesting changes: 1) The domain-independent PBQP solver class, HeuristicSolverImpl, is gone. It is replaced by a register allocation specific solver, PBQP::RegAlloc::Solver (see RegAllocSolver.h). The optimal reduction rules and the backpropagation algorithm have been extracted into stand-alone functions (see ReductionRules.h), which can be used to build domain specific PBQP solvers. This provides many more opportunities for domain-specific knowledge to inform the PBQP solvers' decisions. In theory this should allow us to generate better solutions. In practice, we can at least test out ideas now. As a side benefit, I believe the new solver is more readable than the old one. 2) The solver type is now a template parameter of the PBQP graph. This allows the graph to notify the solver of any modifications made (e.g. by domain independent rules) without the overhead of a virtual call. It also allows the solver to supply policy information to the graph (see below). 3) Significantly reduced memory overhead. Memory management policy is now an explicit property of the PBQP graph (via the CostAllocator typedef on the graph's solver template argument). Because PBQP graphs for register allocation tend to contain many redundant instances of single values (E.g. the value representing an interference constraint between GPRs), the new RASolver class uses a uniquing scheme. This massively reduces memory consumption for large register allocation problems. For example, looking at the largest interference graph in each of the SPEC2006 benchmarks (the largest graph will always set the memory consumption high-water mark for PBQP), the average memory reduction for the PBQP costs was 400x. That's times, not percent. The highest was 1400x. Yikes. So - this is fixed. "PBQP: No longer feasting upon every last byte of your RAM". Minor details: - Fully C++11'd. Never copy-construct another vector/matrix! - Cute tricks with cost metadata: Metadata that is derived solely from cost matrices/vectors is attached directly to the cost instances themselves. That way if you unique the costs you never have to recompute the metadata. 400x less memory means 400x less cost metadata (re)computation. Special thanks to Arnaud de Grandmaison, who has been the source of much encouragement, and of many very useful test cases. This new solver forms the basis for future work, of which there's plenty to do. I will be adding TODO notes shortly. - Lang. llvm-svn: 202551
* Fix >> to be > > for non-c++11.Eric Christopher2014-02-281-1/+1
| | | | llvm-svn: 202545
* R600: Verify all instructions in the AsmPrinter on debug buildsTom Stellard2014-02-281-0/+7
| | | | | | | Make a call to R600's implementation of verifyInstruction() to check that instructions are only using legal operands. llvm-svn: 202544
* R600/SI: Expand all v16[if]32 operationsTom Stellard2014-02-281-1/+1
| | | | llvm-svn: 202543
* 80-col.Eric Christopher2014-02-281-1/+2
| | | | llvm-svn: 202541
* Fix a crasher where when we're attempting to replace a typeEric Christopher2014-02-281-4/+7
| | | | | | | | | | during the finalization for CGDebugInfo in clang we would RAUW a type and it would result in a corrupted MDNode for an imported declaration. Testcase pending as reducing has been difficult. llvm-svn: 202540
* CommandLine: Exit successfully for -version and -helpJustin Bogner2014-02-281-3/+3
| | | | | | | | | | | Tools that use the CommandLine library currently exit with an error when invoked with -version or -help. This is unusual and non-standard, so we'll fix them to exit successfully instead. I don't expect that anyone relies on the current behaviour, so this should be a fairly safe change. llvm-svn: 202530
* Fixed operand of SC microMIPS instruction.Zoran Jovanovic2014-02-282-1/+5
| | | | llvm-svn: 202526
* Fixed encoding of SYSCALL microMIPS instruction.Zoran Jovanovic2014-02-281-1/+1
| | | | llvm-svn: 202523
* Revert revision 202518 because of wrong commit message.Zoran Jovanovic2014-02-281-1/+1
| | | | llvm-svn: 202521
* Fix operand of SC instruction.Zoran Jovanovic2014-02-281-1/+1
| | | | llvm-svn: 202518
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