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* Change encoding of instruction operands in bitcode binaries to be relativeJan Wen Voung2012-10-113-90/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | to the instruction position. The old encoding would give an absolute ID which counts up within a function, and only resets at the next function. I.e., Instead of having: ... = icmp eq i32 n-1, n-2 br i1 ..., label %bb1, label %bb2 it will now be roughly: ... = icmp eq i32 1, 2 br i1 1, label %bb1, label %bb2 This makes it so that ids remain relatively small and can be encoded in fewer bits. With this encoding, forward reference operands will be given negative-valued IDs. Use signed VBRs for the most common case of forward references, which is phi instructions. To retain backward compatibility we bump the bitcode version from 0 to 1 to distinguish between the different encodings. llvm-svn: 165739
* Add in the first iteration of support for llvm/clang/lldb to allow variable ↵Micah Villmow2012-10-1135-92/+142
| | | | | | per address space pointer sizes to be optimized correctly. llvm-svn: 165726
* Pass an explicit operand number to addLiveIns.Jakob Stoklund Olesen2012-10-112-8/+8
| | | | | | | | | Not all instructions define a virtual register in their first operand. Specifically, INLINEASM has a different format. <rdar://problem/12472811> llvm-svn: 165721
* This patch addresses PR13947.Bill Schmidt2012-10-111-0/+8
| | | | | | | | | | | | | | | | | | | | | | For function calls on the 64-bit PowerPC SVR4 target, each parameter is mapped to as many doublewords in the parameter save area as necessary to hold the parameter. The first 13 non-varargs floating-point values are passed in registers; any additional floating-point parameters are passed in the parameter save area. A single-precision floating-point parameter (32 bits) must be mapped to the second (rightmost, low-order) word of its assigned doubleword slot. Currently LLVM violates this ABI requirement by mapping such a parameter to the first (leftmost, high-order) word of its assigned doubleword slot. This is internally self-consistent but will not interoperate correctly with libraries compiled with an ABI-compliant compiler. This patch corrects the problem by adjusting the parameter addressing on both sides of the calling convention. llvm-svn: 165714
* Expose move to/from coprocessor instructions in MIPS64 mode.David Chisnall2012-10-111-0/+30
| | | | | | | | | | | Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a custom CP2 that interprets instructions differently and may wish to add their own instructions that use this opcode. We should ensure that this is easy to do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this easy: We want to avoid the GCC situation where every MIPS vendor makes a custom fork that breaks every other MIPS CPU and so can't be merged upstream. llvm-svn: 165711
* dependence analysisSebastian Pop2012-10-113-0/+3783
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Preston Briggs <preston.briggs@gmail.com>. This is an updated version of the dependence-analysis patch, including an MIV test based on Banerjee's inequalities. It's a fairly complete implementation of the paper Practical Dependence Testing Gina Goff, Ken Kennedy, and Chau-Wen Tseng PLDI 1991 It cannot yet propagate constraints between coupled RDIV subscripts (discussed in Section 5.3.2 of the paper). It's organized as a FunctionPass with a single entry point that supports testing for dependence between two instructions in a function. If there's no dependence, it returns null. If there's a dependence, it returns a pointer to a Dependence which can be queried about details (what kind of dependence, is it loop independent, direction and distance vector entries, etc). I haven't included every imaginable feature, but there's a good selection that should be adequate for supporting many loop transformations. Of course, it can be extended as necessary. Included in the patch file are many test cases, commented with C code showing the loops and array references. llvm-svn: 165708
* Follow the same routine to add target float expansion hookMichael Liao2012-10-111-26/+24
| | | | llvm-svn: 165707
* misched: Handle "transient" non-instructions.Andrew Trick2012-10-112-17/+25
| | | | llvm-svn: 165701
* Don't crash when !tbaa.struct contents is invalid.Nick Lewycky2012-10-111-0/+3
| | | | llvm-svn: 165693
* Revert r165661, "Patch by Shuxin Yang <shuxin.llvm@gmail.com>."NAKAMURA Takumi2012-10-111-40/+0
| | | | | | It broke stage2 clang and test-suite/MultiSource/Benchmarks/mediabench/g721/g721encode. llvm-svn: 165692
* Add the LLVM context to this c'tor. It will be needed in the future.Bill Wendling2012-10-111-1/+1
| | | | llvm-svn: 165687
* Support a common idiom on how to build an Attributes class with a single ↵Bill Wendling2012-10-111-0/+3
| | | | | | attribute. llvm-svn: 165686
* Don't crash if a .ll file contains a forward-reference that looks like a globalNick Lewycky2012-10-111-0/+3
| | | | | | | | | value but later turns out to be a function. Unfortunately, we can't fold tests into a single file because we only get one error out of llvm-as. llvm-svn: 165680
* Change MachineInstrBuilder::addDisp to copy over target flags by default.Evan Cheng2012-10-111-5/+2
| | | | llvm-svn: 165677
* Add isel patterns for v2f32 / v4f32 neon.vbsl intrinsics. rdar://12471808Evan Cheng2012-10-101-0/+8
| | | | llvm-svn: 165673
* Add getters for the MIPS TargetTransform classesNadav Rotem2012-10-101-0/+7
| | | | llvm-svn: 165670
* Remove unused member variable introduced in r165665.David Blaikie2012-10-101-1/+0
| | | | llvm-svn: 165669
* Add a new interface to allow IR-level passes to access codegen-specific ↵Nadav Rotem2012-10-1031-102/+301
| | | | | | information. llvm-svn: 165665
* Patch by Shuxin Yang <shuxin.llvm@gmail.com>.Nadav Rotem2012-10-101-0/+40
| | | | | | | | | | | | | | | | | | | Original message: The attached is the fix to radar://11663049. The optimization can be outlined by following rules: (select (x != c), e, c) -> select (x != c), e, x), (select (x == c), c, e) -> select (x == c), x, e) where the <c> is an integer constant. The reason for this change is that : on x86, conditional-move-from-constant needs two instructions; however, conditional-move-from-register need only one instruction. While the LowerSELECT() sounds to be the most convenient place for this optimization, it turns out to be a bad place. The reason is that by replacing the constant <c> with a symbolic value, it obscure some instruction-combining opportunities which would otherwise be very easy to spot. For that reason, I have to postpone the change to last instruction-combining phase. The change passes the test of "make check-all -C <build-root/test" and "make -C project/test-suite/SingleSource". llvm-svn: 165661
* When generating spill and reload code for vector registers on PowerPC,Bill Schmidt2012-10-101-6/+12
| | | | | | | | | | | | the compiler makes use of GPR0. However, there are two flavors of GPR0 defined by the target: the 32-bit GPR0 (R0) and the 64-bit GPR0 (X0). The spill/reload code makes use of R0 regardless of whether we are generating 32- or 64-bit code. This patch corrects the problem in the obvious manner, using X0 and ADDI8 for 64-bit and R0 and ADDI for 32-bit. llvm-svn: 165658
* The PowerPC VRSAVE register has been somewhat of an odd beast sinceBill Schmidt2012-10-102-6/+14
| | | | | | | | | | | | | | | | | the Altivec extensions were introduced. Its use is optional, and allows the compiler to communicate to the operating system which vector registers should be saved and restored during a context switch. In practice, this information is ignored by the various operating systems using the SVR4 ABI; the kernel saves and restores the entire register state. Setting the VRSAVE register is no longer performed by the AIX XL compilers, the IBM i compilers, or by GCC on Power Linux systems. It seems best to avoid this logic within LLVM as well. This patch avoids generating code to update and restore VRSAVE for the PowerPC SVR4 ABIs (32- and 64-bit). The code remains in place for the Darwin ABI. llvm-svn: 165656
* Add in support for expansion of all of the comparison operations to the ↵Micah Villmow2012-10-101-17/+62
| | | | | | | | | | absolute minimum required set. This allows a backend to expand any arbitrary set of comparisons as long as a minimum set is supported. The minimum set of required instructions is ISD::AND, ISD::OR, ISD::SETO(or ISD::SETOEQ) and ISD::SETUO(or ISD::SETUNE). Everything is expanded into one of two patterns: Pattern 1: (LHS CC1 RHS) Opc (LHS CC2 RHS) Pattern 2: (LHS CC1 LHS) Opc (RHS CC2 RHS) llvm-svn: 165655
* Revert r165652: "Remove unnecessary RTTI from the build."Sean Silva2012-10-104-0/+8
| | | | | | ... Apparently the RTTI is still necessary for some reason. llvm-svn: 165654
* Remove unnecessary RTTI from the build.Sean Silva2012-10-104-8/+0
| | | | llvm-svn: 165652
* tblgen: Compile TableGen without RTTI.Sean Silva2012-10-102-4/+0
| | | | | | TableGen no longer needs RTTI! llvm-svn: 165651
* tblgen: Use semantically correct RTTI functions.Sean Silva2012-10-102-36/+21
| | | | | | Also, some minor cleanup. llvm-svn: 165647
* tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva2012-10-102-94/+94
| | | | | | | | | | Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. llvm-svn: 165646
* Add support for FP_ROUND from v2f64 to v2f32Michael Liao2012-10-104-1/+23
| | | | | | | | | | - Due to the current matching vector elements constraints in ISD::FP_ROUND, rounding from v2f64 to v4f32 (after legalization from v2f32) is scalarized. Add a customized v2f32 widening to convert it into a target-specific X86ISD::VFPROUND to work around this constraints. llvm-svn: 165631
* Add alternative support for FP_ROUND from v2f32 to v2f64Michael Liao2012-10-104-90/+26
| | | | | | | | | | | - Due to the current matching vector elements constraints in ISD::FP_EXTEND, rounding from v2f32 to v2f64 is scalarized. Add a customized v2f32 widening to convert it into a target-specific X86ISD::VFPEXT to work around this constraints. This patch also reverts a previous attempt to fix this issue by recovering the scalarized ISD::FP_EXTEND pattern and thus significantly reduces the overhead of supporting non-power-2 vector FP extend. llvm-svn: 165625
* Fix for LDRB instruction:Stepan Dyatkovskiy2012-10-101-1/+2
| | | | | | | | | | | | | | | | | | | SDNode for LDRB_POST_IMM is invalid: number of registers added to SDNode fewer that described in .td. 7 ops is needed, but SDNode with only 6 is created. In more details: In ARMInstrInfo.td, in multiclass AI2_ldridx, in definition _POST_IMM, offset operand is defined as am2offset_imm. am2offset_imm is complex parameter type, and actually it consists from dummy register and imm itself. As I understood trick with dummy reg was made for AsmParser. In ARMISelLowering.cpp, this dummy register was not added to SDNode, and it cause crash in Peephole Optimizer pass. The problem fixed by setting up additional dummy reg when emitting LDRB_POST_IMM instruction. llvm-svn: 165617
* Issue description:Stepan Dyatkovskiy2012-10-103-10/+20
| | | | | | | | | | | | | | | | | | | | SchedulerDAGInstrs::buildSchedGraph ignores dependencies between FixedStack objects and byval parameters. So loading byval parameters from stack may be inserted *before* it will be stored, since these operations are treated as independent. Fix: Currently ARMTargetLowering::LowerFormalArguments saves byval registers with FixedStack MachinePointerInfo. To fix the problem we need to store byval registers with MachinePointerInfo referenced to first the "byval" parameter. Also commit adds two new fields to the InputArg structure: Function's argument index and InputArg's part offset in bytes relative to the start position of Function's argument. E.g.: If function's argument is 128 bit width and it was splitted onto 32 bit regs, then we got 4 InputArg structs with same arg index, but different offset values. llvm-svn: 165616
* Cleanup. Get rid of now dead code.Bill Wendling2012-10-101-2/+0
| | | | llvm-svn: 165613
* Remove the final bits of Attributes being declared in the AttributeBill Wendling2012-10-107-28/+58
| | | | | | | namespace. Use the attribute's enum value instead. No functionality change intended. llvm-svn: 165610
* My earlier "fix" for PBQP (see r165201) was incorrect. The real issue was thatLang Hames2012-10-101-2/+2
| | | | | | | | checkRegMaskInterference only initializes the bitmask on the first interference. This fixes PR14027 and (re)fixes PR13945. llvm-svn: 165608
* Pass into the AttributeWithIndex::get method an ArrayRef of attributeBill Wendling2012-10-101-31/+33
| | | | | | enums. These are then created via the correct Attributes creation method. llvm-svn: 165607
* misched: fall-back to a target hook for instr bundles.Andrew Trick2012-10-101-3/+4
| | | | llvm-svn: 165606
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-107-78/+101
| | | | | | | | Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. llvm-svn: 165603
* whitespaceAndrew Trick2012-10-101-3/+3
| | | | llvm-svn: 165601
* Have 'addFnAttr' take the attribute enum value. Then have it build the ↵Bill Wendling2012-10-103-9/+5
| | | | | | attribute object and add it appropriately. No functionality change. llvm-svn: 165595
* Reorder some parts of the td file to by in alphabetical orderReed Kotler2012-10-101-64/+75
| | | | llvm-svn: 165590
* Adding comments to clarify the reason for non-standard style in these files.Andrew Kaylor2012-10-104-8/+30
| | | | | | Patch committed on behalf of Kirill Uhanov llvm-svn: 165589
* Cosmetic changesAndrew Kaylor2012-10-102-4/+4
| | | | llvm-svn: 165588
* This patch adds new functions to the SectionRef and ObjectFile interfaces to ↵Andrew Kaylor2012-10-102-0/+18
| | | | | | | | determine whether or not a section is meant to be read-only. These functions will be used by the MCJIT RuntimeDyld to give hints to the memory manager during the object loading process in a future patch. Patch by Ashok Thirumurthi. llvm-svn: 165586
* Implement MipsTargetLowering::CanLowerReturn.Akira Hatanaka2012-10-102-1/+22
| | | | | | Patch by Sasa Stankovic. llvm-svn: 165585
* When expanding atomic load arith instructions, do not lose target flags. ↵Evan Cheng2012-10-091-2/+5
| | | | | | rdar://12453106 llvm-svn: 165568
* misched: Add computeInstrLatency to TargetSchedModel.Andrew Trick2012-10-091-0/+24
| | | | llvm-svn: 165566
* misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for ↵Andrew Trick2012-10-091-6/+12
| | | | | | external users of TargetSchedule. llvm-svn: 165564
* misched: Remove LoopDependencies heuristic.Andrew Trick2012-10-091-40/+1
| | | | | | This wasn't contributing anything significant to postRA heuristics except compile time (by my measurements) and will be replaced by a more general heuristic for cross-region dependencies within the scheduler itself. llvm-svn: 165563
* Initial assembler implementation of Mips load address macroJack Carter2012-10-092-6/+109
| | | | | | | | | | | | | | | | | | | | | | | | This patch provides initial implementation of load address macro instruction for Mips. We have implemented two kinds of expansions with their variations depending on the size of immediate operand: 1) load address with immediate value directly: * la d,j => addiu d,$zero,j (for -32768 <= j <= 65535) * la d,j => lui d,hi16(j) ori d,d,lo16(j) (for any other 32 bit value of j) 2) load load address with register offset value * la d,j(s) => addiu d,s,j (for -32768 <= j <= 65535) * la d,j(s) => lui d,hi16(j) (for any other 32 bit value of j) ori d,d,lo16(j) addu d,d,s This patch does not cover the case when the address is loaded from the value of the label or function. Contributer: Vladimir Medic llvm-svn: 165561
* Use the attribute enums to query if a function has an attribute.Bill Wendling2012-10-092-93/+7
| | | | llvm-svn: 165551
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