summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* AMDGPU: Select scratch mubuf offsets when pointer is a constantMatt Arsenault2017-04-242-34/+94
| | | | | | | | In call sequence setups, there may not be a frame index base and the pointer is a constant offset from the frame pointer / scratch wave offset register. llvm-svn: 301230
* AMDGPU: Set StackGrowsUp in MCAsmInfoMatt Arsenault2017-04-241-0/+1
| | | | | | Not sure what this does though. llvm-svn: 301229
* [AMDGPU] Merge M0 initializationsStanislav Mekhanoshin2017-04-242-9/+179
| | | | | | | | | | Merges equivalent initializations of M0 and hoists them into a common dominator block. Technically the same code can be used with any register, physical or virtual. Differential Revision: https://reviews.llvm.org/D32279 llvm-svn: 301228
* Handle invariant.group.barrier in BasicAAPiotr Padlewski2017-04-242-8/+23
| | | | | | | | | | | | | | | | | | | | | Summary: llvm.invariant.group.barrier returns pointer that mustalias pointer it takes. It can't be marked with `returned` attribute, because it would be remove easily. The other reason is that only Alias Analysis can know about this, because if any other pass would know it, then the result would be replaced with it's argument, which would be invalid. We can think about returned pointer as something that mustalias, but it doesn't have to be bitwise the same as the argument. Reviewers: dberlin, chandlerc, hfinkel, sanjoy Subscribers: reames, nlewycky, rsmith, anna, amharc Differential Revision: https://reviews.llvm.org/D31585 llvm-svn: 301227
* [asan] Let the frontend disable gc-sections optimization for asan globals.Evgeniy Stepanov2017-04-241-16/+16
| | | | | | Also extend -asan-globals-live-support flag to all binary formats. llvm-svn: 301226
* [SimplifyCFG] Fix for non-determinism in codegenMandeep Singh Grang2017-04-241-1/+1
| | | | | | | | | | | | | | Summary: This patch fixes issues in codegen uncovered due to https://reviews.llvm.org/D26718 Reviewers: majnemer, chenli, davide Reviewed By: davide Subscribers: davide, arsenm, llvm-commits Differential Revision: https://reviews.llvm.org/D26726 llvm-svn: 301222
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-2446-225/+279
| | | | | | | | | | | | | | | 1. RegisterClass::getSize() is split into two functions: - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const; - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const; 2. RegisterClass::getAlignment() is replaced by: - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const; This will allow making those values depend on subtarget features in the future. Differential Revision: https://reviews.llvm.org/D31783 llvm-svn: 301221
* Don't emit CFI instructions at the end of a functionAdrian Prantl2017-04-241-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | When functions are terminated by unreachable instructions, the last instruction might trigger a CFI instruction to be generated. However, emitting it would be be illegal since the function (and thus the FDE the CFI is in) has already ended with the previous instruction. Darwin's dwarfdump --verify --eh-frame complains about this and the specification supports this. Relevant bits from the DWARF 5 standard (6.4 Call Frame Information): "[The] address_range [field in an FDE]: The number of bytes of program instructions described by this entry." "Row creation instructions: [...] The new location value is always greater than the current one." The first quotation implies that a CFI cannot describe a target address outside of the enclosing FDE's range. rdar://problem/26244988 Differential Revision: https://reviews.llvm.org/D32246 llvm-svn: 301219
* CodeGen: Add a hook for getFenceOperandTyYaxun Liu2017-04-243-2/+12
| | | | | | | | | | | | | | Currently the operand type for ATOMIC_FENCE assumes value type of a pointer in address space 0. This is fine for most targets. However for amdgcn target, the size of pointer in address space 0 depends on triple environment. For amdgiz environment, it is 64 bit but for other environment it is 32 bit. On the other hand, amdgcn target expects 32 bit fence operands independent of the target triple environment. Therefore a hook is need in target lowering for getting the fence operand type. This patch has no effect on targets other than amdgcn. Differential Revision: https://reviews.llvm.org/D32186 llvm-svn: 301215
* Revert "Compute safety information in a much finer granularity."Evgeniy Stepanov2017-04-243-20/+38
| | | | | | Use-after-free in llvm::isGuaranteedToExecute. llvm-svn: 301214
* [InstSimplify] move (A & ~B) | (A ^ B) -> (A ^ B) from InstCombineSanjay Patel2017-04-242-13/+13
| | | | | | | | | | | This is a straight cut and paste, but there's a bigger problem: if this fold exists for simplifyOr, there should be a DeMorganized version for simplifyAnd. But more than that, we have a patchwork of ad hoc logic optimizations in InstCombine. There should be some structure to ensure that we're not missing sibling folds across and/or/xor. llvm-svn: 301213
* X86RegisterInfo: eliminateFrameIndex: Avoid code duplication; NFCMatthias Braun2017-04-243-34/+24
| | | | | | | | | | | | | | | | | Re-Commit of r300922 and r300923 with less aggressive assert (see discussion at the end of https://reviews.llvm.org/D32205) X86RegisterInfo::eliminateFrameIndex() and X86FrameLowering::getFrameIndexReference() both had logic to compute the base register. This consolidates the code. Also use MachineInstr::isReturn instead of manually enumerating tail call instructions (return instructions were not included in the previous list because they never reference frame indexes). Differential Revision: https://reviews.llvm.org/D32206 llvm-svn: 301211
* Use DW_OP_stack_value when reconstructing variable values with arithmetic.Adrian Prantl2017-04-241-13/+32
| | | | | | | | | | | | | | | When the location description of a source variable involves arithmetic on the value itself, it needs to be marked with DW_OP_stack_value since it is not describing the variable's location, but rather its value. This is a follow-up to r297971 and fixes the source testcase quoted in the comment in debuginfo-dce.ll. rdar://problem/30725338 This reapplies r301093 without modifications. llvm-svn: 301210
* Add a testcase for DIExpression(DW_OP_stack_value)Adrian Prantl2017-04-242-1/+2
| | | | | | | | and relax the assertion that prohibited its emission. This fixes the assertion failure uncovered by r301093. llvm-svn: 301209
* AMDGPU: Add StackPtr and FramePtr registers to MFIMatt Arsenault2017-04-242-0/+26
| | | | | | These will be necessary for setting up call sequences. llvm-svn: 301208
* AMDGPU: Move trap lowering to DAGMatt Arsenault2017-04-245-59/+66
| | | | | | | | | | | Fixes traps in any block besides the entry block, and fixes depending on a live-in physical register by using a virtual register copy. Also happens to stop emitting a nop in the case debug trap is not supported. llvm-svn: 301206
* [DomPrinter] Add a way to programmatically dump a dot representation.Davide Italiano2017-04-241-0/+16
| | | | | | Differential Revision: https://reviews.llvm.org/D32145 llvm-svn: 301205
* [llvm-pdbdump] Re-write the record layout code to be more resilient.Zachary Turner2017-04-244-203/+168
| | | | | | | | This reworks the way virtual bases are handled, and also the way padding is detected across multiple levels of aggregates, producing a much more accurate result. llvm-svn: 301203
* [APInt] Simplify the zext and sext methodsCraig Topper2017-04-241-33/+18
| | | | | | | | | | This replaces a hand written copy loop with a call to memcpy for both zext and sext. For sext, it replaces multiple if/else blocks propagating sign information forward. Now we just do a copy, a sign extension on the last copied word, a memset, and clearUnusedBits. Differential Revision: https://reviews.llvm.org/D32417 llvm-svn: 301201
* InstCombine: Fix assert when reassociating fsub with undefMatt Arsenault2017-04-241-0/+5
| | | | | | | | | | | | | There is logic to track the expected number of instructions produced. It thought in this case an instruction would be necessary to negate the result, but here it folded into a ConstantExpr fneg when the non-undef value operand was cancelled out by the second fsub. I'm not sure why we don't fold constant FP ops with undef currently, but I think that would also avoid this problem. llvm-svn: 301199
* [APInt] Add ashrInPlace method and rewrite ashr to make a copy and then call ↵Craig Topper2017-04-241-76/+36
| | | | | | | | | | | | ashrInPlace. This patch adds an in place version of ashr to match lshr and shl which were recently added. I've tried to make this similar to the lshr code with additions to handle the sign extension. I've also tried to do this with less if checks than the current ashr code by sign extending the original result to a word boundary before doing any of the shifting. This removes a lot of the complexity of determining where to fill in sign bits after the shifting. Differential Revision: https://reviews.llvm.org/D32415 llvm-svn: 301198
* AMDGPU: Move v_readlane lane select from VGPR to SGPRNicolai Haehnle2017-04-241-0/+13
| | | | | | | | | | | | | | | | | Summary: Fix a compiler bug when the lane select happens to end up in a VGPR. Clarify the semantic of the corresponding intrinsic to be that of the corresponding GLSL: the lane select must be uniform across a wave front, otherwise results are undefined. Reviewers: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D32343 llvm-svn: 301197
* Compute safety information in a much finer granularity.Xin Tong2017-04-243-38/+20
| | | | | | | | | | | | | | | | | | | Summary: Instead of keeping a variable indicating whether there are early exits in the loop. We keep all the early exits. This improves LICM's ability to move instructions out of the loop based on is-guaranteed-to-execute. I am going to update compilation time as well soon. Reviewers: hfinkel, sanjoy, efriedma, mkuper Reviewed By: hfinkel Subscribers: llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D32433 llvm-svn: 301196
* InstCombine/AMDGPU: Fix constant folding of llvm.amdgcn.{icmp,fcmp}Nicolai Haehnle2017-04-241-2/+20
| | | | | | | | | | | | | | | | | | Summary: The return value of these intrinsics should always have 0 bits for inactive threads. This means that when all arguments are constant and the comparison evaluates to true, the intrinsic should return the current exec mask. Fixes some GL_ARB_shader_ballot tests. Reviewers: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D32344 llvm-svn: 301195
* [GlobalISel][X86] Lower FormalArgument/Ret using ↵Igor Breger2017-04-242-22/+11
| | | | | | | | | | | | | | | | G_MERGE_VALUES/G_UNMERGE_VALUES. Summary: [GlobalISel][X86] Lower FormalArgument/Ret using G_MERGE_VALUES/G_UNMERGE_VALUES. Reviewers: zvi, t.p.northover, guyblank Reviewed By: t.p.northover Subscribers: dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32288 llvm-svn: 301194
* [DAGCombiner] Updated bswap byte offset variable names to be more ↵Simon Pilgrim2017-04-241-13/+15
| | | | | | | | descriptive. NFC As discussed on D32039, use MaskByteOffset to describe the variable and also pull out repeated getOpcode() calls. llvm-svn: 301193
* [APInt] Fix repeated word in comments. NFCCraig Topper2017-04-241-2/+2
| | | | llvm-svn: 301192
* AMDGPU: Fix crash when scheduling non-memory SMRD instructionsNicolai Haehnle2017-04-241-0/+5
| | | | | | | | | | | | Summary: Fixes piglit spec/arb_shader_clock/execution/* Reviewers: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D32345 llvm-svn: 301191
* [SDAG] Teach Chain Analysis about BaseIndexOffset addressing.Nirav Dave2017-04-241-2/+13
| | | | | | | | | | | | | | | | | | While we use BaseIndexOffset in FindBetterNeighborChains to appropriately realize they're almost the same address and should be improved concurrently we do not use it in isAlias using the non-index understanding FindBaseOffset instead. Adding a BaseIndexOffset check in isAlias like should allow indexed stores to be merged. FindBaseOffset to be excised in subsequent patch. Reviewers: jyknight, aditya_nandakumar, bogner Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31987 llvm-svn: 301187
* [SystemZ] Update kill-flag in splitMove().Jonas Paulsson2017-04-241-2/+3
| | | | | | | EarlierMI needs to clear the kill flag on the first operand in case of a store. Review: Ulrich Weigand llvm-svn: 301177
* Add SUSE vendorIsmail Donmez2017-04-241-0/+2
| | | | | | | | | | | | | | Summary: SUSE's ARM triples end with -gnueabi even though they are hard-float. This requires special handling of SUSE ARM triples. Hence we need a way to differentiate the SUSE as vendor. This CL adds that. Reviewers: chandlerc, compnerd, echristo, rengolin Reviewed By: rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D32426 llvm-svn: 301174
* [DWARF] - Take relocations in account when extracting ranges from .debug_rangesGeorge Rimar2017-04-243-14/+22
| | | | | | | | | | | | | | | I found this when investigated "Bug 32319 - .gdb_index is broken/incomplete" for LLD. When we have object file with .debug_ranges section it may be filled with zeroes. Relocations are exist in file to relocate this zeroes into real values later, but until that a pair of zeroes is treated as terminator. And DWARF parser thinks there is no ranges at all when I am trying to collect address ranges for building .gdb_index. Solution implemented in this patch is to take relocations in account when parsing ranges. Differential revision: https://reviews.llvm.org/D32228 llvm-svn: 301170
* [ARM] GlobalISel: Legalize s8 and s16 G_(S|U)DIVDiana Picus2017-04-242-0/+55
| | | | | | | | | | | | | | We have to widen the operands to 32 bits and then we can either use hardware division if it is available or lower to a libcall otherwise. At the moment it is not enough to set the Legalizer action to WidenScalar, since for libcalls it won't know what to do (it won't be able to find what size to widen to, because it will find Libcall and not Legal for 32 bits). To hack around this limitation, we request Custom lowering, and as part of that we widen first and then we run another legalizeInstrStep on the widened DIV. llvm-svn: 301166
* [Arch64AsmParser] better diagnostic for isbSjoerd Meijer2017-04-241-7/+5
| | | | | | | | | | | Instruction isb takes as an operand either 'sy' or an immediate value. This improves the diagnostic when the string is not 'sy' and adds a test case for this which was missing. This also adds tests to check invalid inputs for dsb and dmb. Differential Revision: https://reviews.llvm.org/D32227 llvm-svn: 301165
* [ARM] GlobalISel: Support G_(S|U)DIV for s32Diana Picus2017-04-243-0/+19
| | | | | | | | | Add support for both targets with hardware division and without. For hardware division we have to add support throughout the pipeline (legalizer, reg bank select, instruction select). For targets without hardware division, we only need to mark it as a libcall. llvm-svn: 301164
* [GlobalISel] Legalize G_(S|U)DIV libcallsDiana Picus2017-04-241-12/+30
| | | | | | | | | | Treat them the same as the other binary operations that we have so far, but on integers rather than floating point types. Extract the common code into a helper. This will be used in the ARM backend. llvm-svn: 301163
* [ARM] GlobalISel: Select G_CONSTANT with CImm operandsDiana Picus2017-04-241-0/+12
| | | | | | | | | | | | | | When selecting a G_CONSTANT to a MOVi, we need the value to be an Imm operand. We used to just leave the G_CONSTANT operand unchanged, which works in some cases (such as the GEP offsets that we create when referring to stack slots). However, in many other places the G_CONSTANTs are created with CImm operands. This patch makes sure to handle those as well, and to error out gracefully if in the end we don't end up with an Imm operand. Thanks to Oliver Stannard for reporting this issue. llvm-svn: 301162
* [APInt] Make behavior of ashr by BitWidth consistent between single and ↵Craig Topper2017-04-241-1/+3
| | | | | | | | multi word. Previously single word would always return 0 regardless of the original sign. Multi word would return all 0s or all 1s based on the original sign. Now single word takes into account the sign as well. llvm-svn: 301159
* Revert "Refactor DynamicLibrary so searching for a symbol will have a ↵Frederich Munch2017-04-245-359/+275
| | | | | | | | | | defined order.” The changes are causing the i686-mingw32 build to fail. This reverts commit r301153, and the changes for a separate warning on i686-mingw32 in r301155 and r301156. llvm-svn: 301157
* Fix warning converting from boolean to pointer introduced in r301153.Frederich Munch2017-04-242-2/+2
| | | | | | This reverts commit r301155, which was incorrect. llvm-svn: 301156
* Fix warning converting from void* to boolean introduced in r301153.Frederich Munch2017-04-241-1/+1
| | | | llvm-svn: 301155
* Revert "[SCEV] Enable SCEV verification by default in EXPENSIVE_CHECKS builds"Sanjoy Das2017-04-241-10/+3
| | | | | | | This reverts commit r301150. It breaks CodeGen/Hexagon/hwloop-wrap2.ll, reverting while I investigate. llvm-svn: 301154
* Refactor DynamicLibrary so searching for a symbol will have a defined order andFrederich Munch2017-04-245-275/+359
| | | | | | | | | | | | | | | | | | | | | | | | | | | libraries are properly unloaded when llvm_shutdown is called. Summary: This was mostly affecting usage of the JIT, where storing the library handles in a set made iteration unordered/undefined. This lead to disagreement between the JIT and native code as to what the address and implementation of particularly on Windows with stdlib functions: JIT: putenv_s("TEST", "VALUE") // called msvcrt.dll, putenv_s JIT: getenv("TEST") -> "VALUE" // called msvcrt.dll, getenv Native: getenv("TEST") -> NULL // called ucrt.dll, getenv Also fixed is the issue of DynamicLibrary::getPermanentLibrary(0,0) on Windows not giving priority to the process' symbols as it did on Unix. Reviewers: chapuni, v.g.vassilev, lhames Reviewed By: lhames Subscribers: danalbert, srhines, mgorny, vsk, llvm-commits Differential Revision: https://reviews.llvm.org/D30107 llvm-svn: 301153
* Fix unused variables / fields warnings in release buildsSanjoy Das2017-04-241-0/+6
| | | | llvm-svn: 301151
* [SCEV] Enable SCEV verification by default in EXPENSIVE_CHECKS buildsSanjoy Das2017-04-241-3/+10
| | | | llvm-svn: 301150
* [SCEV] Fix exponential time complexity by cachingSanjoy Das2017-04-241-19/+63
| | | | llvm-svn: 301149
* [PartialInine]: add triaging optionsXinliang David Li2017-04-231-0/+24
| | | | | | | There are more bugs (runtime failures) triggered when partial inlining is turned on. Add options to help triaging problems. llvm-svn: 301148
* [SCEV] Move towards a verifier without false positivesSanjoy Das2017-04-231-68/+59
| | | | | | | | | | | | | | | This change reboots SCEV's current (off by default) verification logic to avoid false failures. Instead of stringifying trip counts, it maps old and new trip counts to the same ScalarEvolution "universe" and asks ScalarEvolution to compute the difference between them. If the difference comes out to be a non-zero constant, then (barring some corner cases) we *know* we messed up. I've not yet enabled this by default since it hits an exponential time issue in SCEV, but once I fix that, I'll flip it on by default in EXPENSIVE_CHECKS builds. llvm-svn: 301146
* [InstCombine] add/move folds for [not]-xorSanjay Patel2017-04-231-38/+67
| | | | | | | | | | | | We handled all of the commuted variants for plain xor already, although they were scattered around and sometimes folded less efficiently using distributive laws. We had no folds for not-xor. Handling all of these patterns consistently is part of trying to reinstate: https://reviews.llvm.org/rL300977 llvm-svn: 301144
* [PartialInlining] Add optimization remark supportXinliang David Li2017-04-231-4/+20
| | | | | | Differential Revision: http://reviews.llvm.org/D32387 llvm-svn: 301143
OpenPOWER on IntegriCloud