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* tools: Add a space between package version and LLVM_VERSION_INFOJustin Bogner2014-06-171-1/+1
| | | | | | This reads a little strangely. Add a space to clean it up. llvm-svn: 211090
* Convert a few loops to use ranges.Rafael Espindola2014-06-171-18/+15
| | | | llvm-svn: 211089
* Add an overload for SourceMgr::PrintMessage that takes an existing diagnostic.Jordan Rose2014-06-171-8/+11
| | | | llvm-svn: 211087
* Modernize doc comments for SourceMgr.Jordan Rose2014-06-171-12/+0
| | | | | | No functionality change. llvm-svn: 211086
* [InstCombine] mark ADD with nuw if no unsigned overflowJingyue Wu2014-06-172-0/+23
| | | | | | | | | | | | | | | | | | | | | | Summary: As a starting step, we only use one simple heuristic: if the sign bits of both a and b are zero, we can prove "add a, b" do not unsigned overflow, and thus convert it to "add nuw a, b". Updated all affected tests and added two new tests (@zero_sign_bit and @zero_sign_bit2) in AddOverflow.ll Test Plan: make check-all Reviewers: eliben, rafael, meheff, chandlerc Reviewed By: chandlerc Subscribers: chandlerc, llvm-commits Differential Revision: http://reviews.llvm.org/D4144 llvm-svn: 211084
* SROA: Only split loads on byte boundariesDuncan P. N. Exon Smith2014-06-171-5/+7
| | | | | | | | | | | | | r199771 accidently broke the logic that makes sure that SROA only splits load on byte boundaries. If such a split happens, some bits get lost when reassembling loads of wider types, causing data corruption. Move the width check up to reject such splits early, avoiding the corruption. Fixes PR19250. Patch by: Björn Steinbrink <bsteinbr@gmail.com> llvm-svn: 211082
* [FastISel][X86] Refactor the code to get the X86 condition from a helper ↵Juergen Ributzka2014-06-163-96/+110
| | | | | | | | | function. NFC. Make use of helper functions to simplify the branch and compare instruction selection in FastISel. Also add test cases for compare and conditonal branch. llvm-svn: 211077
* Teach LoopUnrollPass to respect loop unrolling hints in metadata.Eli Bendersky2014-06-161-87/+275
| | | | | | | | | | | | | [This is resubmitting r210721, which was reverted due to suspected breakage which turned out to be unrelated]. Some extra review comments were addressed. See D4090 and D4147 for more details. The Clang change that produces this metadata was committed in r210667 Patch by Mark Heffernan. llvm-svn: 211076
* Revert r211066, 211067, 211068, 211069, 211070.Zachary Turner2014-06-164-29/+48
| | | | | | | These were committed accidentally from the wrong branch before having a review sign-off. llvm-svn: 211072
* Cleanup more unreferenced MutexGuard parameters on functions.Zachary Turner2014-06-163-29/+29
| | | | | | | | | | | These parameters are intended to serve as sort of a contract that you cannot access the functions outside of a mutex. However, the entire JIT class cannot be accessed outside of a mutex anyway, and all methods acquire a lock as soon as they are entered. Since the containing class already is not intended to be thread-safe, it only serves to add code clutter. llvm-svn: 211071
* Kill the LLVM global lock.Zachary Turner2014-06-163-7/+23
| | | | llvm-svn: 211069
* Remove some code churn.Zachary Turner2014-06-161-1/+1
| | | | llvm-svn: 211068
* Remove some more code out into a separate CL.Zachary Turner2014-06-164-32/+6
| | | | llvm-svn: 211067
* Users of the llvm global mutex must now acquire it manually.Zachary Turner2014-06-163-17/+8
| | | | | | This allows the mutex to be acquired in a guarded, RAII fashion. llvm-svn: 211066
* Add load/store functionalityReed Kotler2014-06-161-7/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patches allows non conversions like i1=i2; where both are global ints. In addition, arithmetic and other things start to work since fast-isel will use existing patterns for non fast-isel from tablegen files where applicable. In addition i8, i16 will work in this limited context for assignment without the need for sign extension (zero or signed). It does not matter how i8 or i16 are loaded (zero or sign extended) since only the 8 or 16 relevant bits are used and clang will ask for sign extension before using them in arithmetic. This is all made more complete in forthcoming patches. for example: int i, j=1, k=3; void foo() { i = j + k; } Keep in mind that this pass is not enabled right now and is an experimental pass It can only be enabled with a hidden option to llvm of -mips-fast-isel. Test Plan: Run test-suite, loadstore2.ll and I will run some executable tests. Reviewers: dsanders Subscribers: mcrosier Differential Revision: http://reviews.llvm.org/D3856 llvm-svn: 211061
* AArch64: Add backend intrinsic for rbit.Jim Grosbach2014-06-161-0/+4
| | | | | | | | | Define an intrinsic for the frontend to use and pattern match it to the RBIT instruction. rdar://9283021 llvm-svn: 211058
* ARM: intrinsic support for rbit.Jim Grosbach2014-06-161-0/+5
| | | | | | | | | We already have an ARMISD node. Create an intrinsic to map to it so we can add support for the frontend __rbit() intrinsic. rdar://9283021 llvm-svn: 211057
* [PPC64] Fix PR19893 - improve code generation for local function addressesBill Schmidt2014-06-163-21/+25
| | | | | | | | | | | | | | | | | | | | | Rafael opened http://llvm.org/bugs/show_bug.cgi?id=19893 to track non-optimal code generation for forming a function address that is local to the compile unit. The existing code was treating both local and non-local functions identically. This patch fixes the problem by properly identifying local functions and generating the proper addis/addi code. I also noticed that Rafael's earlier changes to correct the surrounding code in PPCISelLowering.cpp were also needed for fast instruction selection in PPCFastISel.cpp, so this patch fixes that code as well. The existing test/CodeGen/PowerPC/func-addr.ll is modified to test the new code generation. I've added a -O0 run line to test the fast-isel code as well. Tested on powerpc64[le]-unknown-linux-gnu with no regressions. llvm-svn: 211056
* Since the DataLayout is always found off of the subtarget go aheadEric Christopher2014-06-161-7/+3
| | | | | | and query the base target machine implementation for it. llvm-svn: 211055
* Clean up some unnecessary mutex guards.Zachary Turner2014-06-161-25/+24
| | | | | | | | | | | | | | | These were being used as unreferenced parameters to enforce that the methods must not be called without holding a mutex, but all of the methods in question were internal, and the methods were only exposed through an interface whose entire purpose was to serialize access to these structures, so expecting the methods to be accessed under a mutex is reasonable enough. Reviewed by: blaikie Differential Revision: http://reviews.llvm.org/D4162 llvm-svn: 211054
* Improve comments for r211040Louis Gerbarg2014-06-161-1/+4
| | | | | | | | Added comment to clarify why we r211040 choose to bail out of fast isel instead of generating a more complicated relocation, and fix mislabelled register in the comments of the asan test case. llvm-svn: 211052
* ARM: implement correct atomic operations on v7MTim Northover2014-06-161-8/+14
| | | | | | | | | | ARM v7M has ldrex/strex but not ldrexd/strexd. This means 32-bit operations should work as normal, but 64-bit ones are almost certainly doomed. Patch by Phoebe Buckheister. llvm-svn: 211042
* Fix illegal relocations in X86FastISelLouis Gerbarg2014-06-161-0/+4
| | | | | | | | | | | | On x86_86 the lea instruction can only use a 32 bit immediate value. When the code is compiled statically the RIP register is not used, meaning the immediate is all that can be used for the relocation, which is not sufficient in the case of targets more than +/- 2GB away. This patch bails out of fast isel in those cases and reverts to DAG which does the right thing. Test case included. llvm-svn: 211040
* LowerSwitch: track bounding range for the condition tree.Jim Grosbach2014-06-161-27/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When LowerSwitch transforms a switch instruction into a tree of ifs it is actually performing a binary search into the various case ranges, to see if the current value falls into one cases range of values. So, if we have a program with something like this: switch (a) { case 0: do0(); break; case 1: do1(); break; case 2: do2(); break; default: break; } the code produced is something like this: if (a < 1) { if (a == 0) { do0(); } } else { if (a < 2) { if (a == 1) { do1(); } } else { if (a == 2) { do2(); } } } This code is inefficient because the check (a == 1) to execute do1() is not needed. The reason is that because we already checked that (a >= 1) initially by checking that also (a < 2) we basically already inferred that (a == 1) without the need of an extra basic block spawned to check if actually (a == 1). The patch addresses this problem by keeping track of already checked bounds in the LowerSwitch algorithm, so that when the time arrives to produce a Leaf Block that checks the equality with the case value / range the algorithm can decide if that block is really needed depending on the already checked bounds . For example, the above with "a = 1" would work like this: the bounds start as LB: NONE , UB: NONE as (a < 1) is emitted the bounds for the else path become LB: 1 UB: NONE. This happens because by failing the test (a < 1) we know that the value "a" cannot be smaller than 1 if we enter the else branch. After the emitting the check (a < 2) the bounds in the if branch become LB: 1 UB: 1. This is because by checking that "a" is smaller than 2 then the upper bound becomes 2 - 1 = 1. When it is time to emit the leaf block for "case 1:" we notice that 1 can be squeezed exactly in between the LB and UB, which means that if we arrived to that block there is no need to emit a block that checks if (a == 1). Patch by: Marcello Maggioni <hayarms@gmail.com> llvm-svn: 211038
* Refactor the disabling of Thumb-1 LDM/STM generationJames Molloy2014-06-162-7/+7
| | | | | | | | Originally I switched the LD/ST optimizer off in TargetMachine as it was previously, but Eric has suggested he'd prefer that it be short-circuited in the pass itself. No functionality change. llvm-svn: 211037
* Fix pr17056.Rafael Espindola2014-06-161-5/+5
| | | | | | | | | | | | | This makes llvm-nm ignore members that are not sufficiently aligned for lib/Object to handle. These archives are invalid. GNU AR is able to handle this, but in general just warns about broken archive members. We should probably start warning too, but for now just make sure llvm-nm exits with an 0. llvm-svn: 211036
* Convert the Archive API to use ErrorOr.Rafael Espindola2014-06-162-57/+48
| | | | | | | | | Now that we have c++11, even things like ErrorOr<std::unique_ptr<...>> are easy to use. No intended functionality change. llvm-svn: 211033
* [AArch64] Remove dead code.Tilmann Scheller2014-06-161-3/+0
| | | | | | Both function declarations lack a callee and an implementation. llvm-svn: 211029
* Hook up vector int_ctlz for AVX512.Cameron McInally2014-06-162-0/+14
| | | | llvm-svn: 211024
* [mips][mips64r6] ssnop is deprecated on MIPS32r6/MIPS64r6Daniel Sanders2014-06-162-1/+14
| | | | | | | | | | | | Summary: Depends on D4120 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: zoran.jovanovic, vmedic Differential Revision: http://reviews.llvm.org/D4121 llvm-svn: 211021
* [mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6Daniel Sanders2014-06-166-6/+61
| | | | | | | | | | | | | | | | | Summary: There is no change to the restrictions, just the result register is stored once in the encoding rather than twice. The rt field is zero in MIPS32r6/MIPS64r6. Depends on D4119 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4120 llvm-svn: 211019
* [mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.Daniel Sanders2014-06-1610-35/+142
| | | | | | | | | | | | | | | | | | | | | Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
* Support/ConvertUTF: restore compatibility with MSVC, which only implements C89Dmitri Gribenko2014-06-161-5/+7
| | | | llvm-svn: 211016
* Support/ConvertUTF: implement U+FFFD insertion according to the recommendationDmitri Gribenko2014-06-161-8/+143
| | | | | | | | | given in the Unicode spec That is, replace every maximal subpart of an ill-formed subsequence with one U+FFFD. llvm-svn: 211015
* [AArch64] Fix a fencepost error in lowering for llvm.aarch64.neon.uqshl.James Molloy2014-06-161-1/+1
| | | | | | Patch by Jiangning Liu! llvm-svn: 211014
* [mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates ↵Daniel Sanders2014-06-165-9/+88
| | | | | | | | | | | | | | | | | | | | | rather than 16-bit in MIPS32r6/MIPS64r6 Summary: The error message for the invalid.s cases isn't very helpful. It happens because there is an instruction with a wider immediate that would have matched if the NotMips32r6 predicate were true. I have some WIP to improve the message but it affects most error messages for removed/re-encoded instructions on MIPS32r6/MIPS64r6 and should therefore be a separate commit. Depens on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4117 llvm-svn: 211012
* ARMEB: Fix trunc store for vector typesChristian Pirker2014-06-161-1/+2
| | | | | | Reviewed at http://reviews.llvm.org/D4135 llvm-svn: 211010
* Canonicalize addrspacecast ConstExpr between different pointer typesJingyue Wu2014-06-153-3/+21
| | | | | | | | | | | | | | | | | | As a follow-up to r210375 which canonicalizes addrspacecast instructions, this patch canonicalizes addrspacecast constant expressions. Given clang uses ConstantExpr::getAddrSpaceCast to emit addrspacecast cosntant expressions, this patch is also a step towards having the frontend emit canonicalized addrspacecasts. Piggyback a minor refactor in InstCombineCasts.cpp Update three affected tests in addrspacecast-alias.ll, access-non-generic.ll and constant-fold-gep.ll and added one new test in constant-fold-address-space-pointer.ll llvm-svn: 211004
* Fix copy paste errorMatt Arsenault2014-06-151-1/+1
| | | | llvm-svn: 211003
* R600: Remove a few more things from AMDILISelLoweringMatt Arsenault2014-06-152-27/+21
| | | | | | | Try to keep all the setOperationActions for integer ops together. llvm-svn: 211001
* R600: Fix assert on vector sdivMatt Arsenault2014-06-151-4/+4
| | | | llvm-svn: 211000
* R600: Move / cleanup more leftover AMDIL stuff.Matt Arsenault2014-06-153-71/+30
| | | | llvm-svn: 210998
* R600: Move division custom lowering out of AMDILISelLoweringMatt Arsenault2014-06-153-271/+257
| | | | llvm-svn: 210997
* Temporarily revert r210953 in an attempt to bring the ARM buildbotsEric Christopher2014-06-159-26/+24
| | | | | | back. llvm-svn: 210996
* R600: Report that integer division is expensive.Matt Arsenault2014-06-151-0/+7
| | | | | | Divides by weird constants now emit much better code. llvm-svn: 210995
* R600: Remove dead codeMatt Arsenault2014-06-152-75/+11
| | | | llvm-svn: 210994
* PR20038: DebugInfo missing DIEs for some concrete variables.David Blaikie2014-06-151-0/+3
| | | | | | | | I haven't nailed this down entirely, but this is about as small of a test case as I can seem to construct and adequately demonstrates the crasher. I'll continue investigating the root cause/fix(es). llvm-svn: 210993
* LegalizeDAG: make sure cast is unsigned before using FP_TO_UINT.Tim Northover2014-06-151-1/+4
| | | | | | | | | | | | It's valid to use FP_TO_SINT when asking for a smaller type (e.g. all "unsigned int16" values fit into a "signed int32"), but the reverse isn't true. Unfortunately, I'm not actually aware of any architecture with asymmetric FP_TO_SINT and FP_TO_UINT handling and the logic happens to work in the symmetric case, so I can't actually write a test for this. llvm-svn: 210986
* AArch64: improve handling & modelling of FP_TO_XINT nodes.Tim Northover2014-06-152-10/+25
| | | | | | | | There's probably no acatual change in behaviour here, just updating the LowerFP_TO_INT function to be more similar to the reverse implementation and updating costs to current CodeGen. llvm-svn: 210985
* AArch64: improve vector [su]itofp handling.Tim Northover2014-06-152-36/+46
| | | | | | | This somehow got missed in the AArch64 merge, so should fix a performance regression since 3.4. llvm-svn: 210984
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