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* transform fmin/fmax calls when possible (PR24314)Sanjay Patel2015-08-161-2/+61
| | | | | | | | | | | | | | | If we can ignore NaNs, fmin/fmax libcalls can become compare and select (this is what we turn std::min / std::max into). This IR should then be optimized in the backend to whatever is best for any given target. Eg, x86 can use minss/maxss instructions. This should solve PR24314: https://llvm.org/bugs/show_bug.cgi?id=24314 Differential Revision: http://reviews.llvm.org/D11866 llvm-svn: 245187
* [LSR][NFC] Don’t duplicate entity name at the beginning of the comment.Sanjoy Das2015-08-161-236/+208
| | | | llvm-svn: 245183
* [LSR][NFC] Use camelCase for method names in Formula and RegUseTracker.Sanjoy Das2015-08-161-34/+34
| | | | llvm-svn: 245182
* use SDValue bool operator; NFCISanjay Patel2015-08-161-4/+3
| | | | llvm-svn: 245181
* Add missing include guard.Yaron Keren2015-08-161-0/+4
| | | | llvm-svn: 245173
* Revert "Add support for cross block dse. This patch enables dead stroe ↵David Majnemer2015-08-161-224/+51
| | | | | | | | elimination across basicblocks." This reverts commit r245025, it caused PR24469. llvm-svn: 245172
* [InstCombine] Replace an and+icmp with a trunc+icmpDavid Majnemer2015-08-161-0/+17
| | | | | | | | Bitwise arithmetic can obscure a simple sign-test. If replacing the mask with a truncate is preferable if the type is legal because it permits us to rephrase the comparison more explicitly. llvm-svn: 245171
* Revert r244127: [PM] Remove a failed attempt to port the CallGraphChandler Carruth2015-08-161-0/+15
| | | | | | | | | | | | | analysis ... It turns out that we *do* need the old CallGraph ported to the new pass manager. There are times where this model of a call graph is really superior to the one provided by the LazyCallGraph. For example, GlobalsModRef very specifically needs the model provided by CallGraph. While here, I've tried to make the move semantics actually work. =] llvm-svn: 245170
* [X86] Widen the 'AND' mask if doing so shrinks the encoding sizeDavid Majnemer2015-08-161-2/+61
| | | | | | | | | | | | | We can set additional bits in a mask given that we know the other operand of an AND already has some bits set to zero. This can be more efficient if doing so allows us to use an instruction which implicitly sign extends the immediate. This fixes PR24085. Differential Revision: http://reviews.llvm.org/D11289 llvm-svn: 245169
* MergeFunc: Quick fix for r245140, Ignore second, aka Function*, in sorting.NAKAMURA Takumi2015-08-161-1/+6
| | | | | | Don't assume second would be ordered in the module. llvm-svn: 245168
* Try to appease VS 2015 warnings from http://reviews.llvm.org/D11890Yaron Keren2015-08-151-21/+19
| | | | | | | | | | | | | ByteSize and BitSize should not be size_t but unsigned, considering 1) They are at most 2^16 and 2^19, respectively. 2) BitSize is an argument to Type::getIntNTy which takes unsigned. Also, use the correct utostr instead itostr and cache the string result. Thanks to James Touton for reporting this! llvm-svn: 245167
* [x86] enable machine combiner reassociations for scalar single-precision ↵Sanjay Patel2015-08-151-0/+6
| | | | | | minimums llvm-svn: 245166
* Silence VS2015 warning.Yaron Keren2015-08-151-1/+1
| | | | | | | | Patch by James Touton! http://reviews.llvm.org/D11890 llvm-svn: 245161
* [DAGCombiner] Attempt to mask vectors before zero extension instead of after.Simon Pilgrim2015-08-152-17/+47
| | | | | | | | | | | | | | For cases where we TRUNCATE and then ZERO_EXTEND to a larger size (often from vector legalization), see if we can mask the source data and then ZERO_EXTEND (instead of after a ANY_EXTEND). This can help avoid having to generate a larger mask, and possibly applying it to several sub-vectors. (zext (truncate x)) -> (zext (and(x, m)) Includes a minor patch to SystemZ to better recognise 8/16-bit zero extension patterns from RISBG bit-extraction code. This is the first of a number of minor patches to help improve the conversion of byte masks to clear mask shuffles. Differential Revision: http://reviews.llvm.org/D11764 llvm-svn: 245160
* [PM/AA] Delete the LibCallAliasAnalysis and all the associatedChandler Carruth2015-08-154-185/+0
| | | | | | | | | | | | | | | | | | infrastructure. This AA was never used in tree. It's infrastructure also completely overlaps that of TargetLibraryInfo which is used heavily by BasicAA to achieve similar goals to those stated for this analysis. As has come up in several discussions, the use case here is still really important, but this code isn't helping move toward that use case. Any progress on better supporting rich AA information for runtime library environments would likely be better off starting from scratch or starting from TargetLibraryInfo than from this base. Differential Revision: http://reviews.llvm.org/D12028 llvm-svn: 245155
* AMDGPU/SI: Only look at live out SGPR defsMatt Arsenault2015-08-151-3/+7
| | | | | | | | | | | | | | | | | When trying to fix SGPR live ranges, skip defs that are killed in the same block as the def. I don't think we need to worry about these cases as long as the live ranges of the SGPRs in dominating blocks are correct. This reduces the number of elements the second loop over the function needs to look at, and makes it generally easier to understand. The second loop also only considers if the live range is live in to a block, which logically means it must have been live out from another. llvm-svn: 245150
* [IR] Give catchret an optional 'return value' operandDavid Majnemer2015-08-1512-42/+104
| | | | | | | | | | | Some personality routines require funclet exit points to be clearly marked, this is done by producing a token at the funclet pad and consuming it at the corresponding ret instruction. CleanupReturnInst already had a spot for this operand but CatchReturnInst did not. Other personality routines don't need to use this which is why it has been made optional. llvm-svn: 245149
* Remove redundant TargetFrameLowering::getFrameIndexOffset virtualJames Y Knight2015-08-1518-78/+94
| | | | | | | | | | | function. This was the same as getFrameIndexReference, but without the FrameReg output. Differential Revision: http://reviews.llvm.org/D12042 llvm-svn: 245148
* [WebAssembly] Add RelooperJF Bastien2015-08-153-0/+1121
| | | | | | | | | | | | | | | | This is just an initial checkin of an implementation of the Relooper algorithm, in preparation for WebAssembly codegen to utilize. It doesn't do anything yet by itself. The Relooper algorithm takes an arbitrary control flow graph and generates structured control flow from that, utilizing a helper variable when necessary to handle irreducibility. The WebAssembly backend will be able to use this in order to generate an AST for its binary format. Author: azakai Reviewers: jfb, sunfish Subscribers: jevinskie, arsenm, jroelofs, llvm-commits Differential revision: http://reviews.llvm.org/D11691 llvm-svn: 245142
* Accelerate MergeFunctions with hashingJF Bastien2015-08-151-4/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes the Merge Functions pass faster by calculating and comparing a hash value which captures the essential structure of a function before performing a full function comparison. The hash is calculated by hashing the function signature, then walking the basic blocks of the function in the same order as the main comparison function. The opcode of each instruction is hashed in sequence, which means that different functions according to the existing total order cannot have the same hash, as the comparison requires the opcodes of the two functions to be the same order. The hash function is a static member of the FunctionComparator class because it is tightly coupled to the exact comparison function used. For example, functions which are equivalent modulo a single variant callsite might be merged by a more aggressive MergeFunctions, and the hash function would need to be insensitive to these differences in order to exploit this. The hashing function uses a utility class which accumulates the values into an internal state using a standard bit-mixing function. Note that this is a different interface than a regular hashing routine, because the values to be hashed are scattered amongst the properties of a llvm::Function, not linear in memory. This scheme is fast because only one word of state needs to be kept, and the mixing function is a few instructions. The main runOnModule function first computes the hash of each function, and only further processes functions which do not have a unique function hash. The hash is also used to order the sorted function set. If the hashes differ, their values are used to order the functions, otherwise the full comparison is done. Both of these are helpful in speeding up MergeFunctions. Together they result in speedups of 9% for mysqld (a mostly C application with little redundancy), 46% for libxul in Firefox, and 117% for Chromium. (These are all LTO builds.) In all three cases, the new speed of MergeFunctions is about half that of the module verifier, making it relatively inexpensive even for large LTO builds with hundreds of thousands of functions. The same functions are merged, so this change is free performance. Author: jrkoenig Reviewers: nlewycky, dschuff, jfb Subscribers: llvm-commits, aemerson Differential revision: http://reviews.llvm.org/D11923 llvm-svn: 245140
* LoopStrengthReduce: Try to pass address space to isLegalAddressingModeMatt Arsenault2015-08-151-63/+94
| | | | | | | | | This seems to only work some of the time. In some situations, this seems to use a nonsensical type and isn't actually aware of the memory being accessed. e.g. if branch condition is an icmp of a pointer, it checks the addressing mode of i1. llvm-svn: 245137
* AMDGPU/SI: Fix printing useless info with amdhsaMatt Arsenault2015-08-151-1/+1
| | | | | | | The comments at the bottom would all report 0 if amdhsa was used. llvm-svn: 245135
* AMDGPU/SI: Update LiveVariablesMatt Arsenault2015-08-151-2/+15
| | | | | | | This is simple but won't work if/when this pass is moved to be post-SSA. llvm-svn: 245134
* AMDGPU/SI: Update LiveIntervals during SIFixSGPRLiveRangesMatt Arsenault2015-08-151-4/+13
| | | | | | | | | Does not mark SlotIndexes as reserved, although I think that might be OK. LiveVariables still need to be handled. llvm-svn: 245133
* AMDGPU: Remove unnecessary assertMatt Arsenault2015-08-151-1/+1
| | | | | | | These shouldn't ever be null. The number of successors was already asserted to be 2. llvm-svn: 245132
* AMDGPU/SI: Make comments more precise.Matt Arsenault2015-08-151-8/+8
| | | | | | | | | | | True branch instructions do behave as expected with liveness. Avoid the phrasing "branch decision is based on a value in an SGPR" because this could be misleading. A VALU compare instruction's result is still based on an SGPR, even though that condition may be divergent. llvm-svn: 245131
* Fix a crash where a utility function wasn't aware of fcmp vectors and ↵Nick Lewycky2015-08-141-1/+2
| | | | | | created a value with the wrong type. Fixes PR24458! llvm-svn: 245119
* [SCEV] Apply NSW and NUW flags via poison value analysis for sub, mul and shlBjarke Hammersholt Roune2015-08-141-34/+79
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: http://reviews.llvm.org/D11212 made Scalar Evolution able to propagate NSW and NUW flags from instructions to SCEVs for add instructions. This patch expands that to sub, mul and shl instructions. This change makes LSR able to generate pointer induction variables for loops like these, where the index is 32 bit and the pointer is 64 bit: for (int i = 0; i < numIterations; ++i) sum += ptr[i - offset]; for (int i = 0; i < numIterations; ++i) sum += ptr[i * stride]; for (int i = 0; i < numIterations; ++i) sum += ptr[3 * (i << 7)]; Reviewers: atrick, sanjoy Subscribers: sanjoy, majnemer, hfinkel, llvm-commits, meheff, jingyue, eliben Differential Revision: http://reviews.llvm.org/D11860 llvm-svn: 245118
* Add a target environment for CoreCLR.Pat Gavlin2015-08-144-2/+9
| | | | | | | | | | Although targeting CoreCLR is similar to targeting MSVC, there are certain important differences that the backend must be aware of (e.g. differences in stack probes, EH, and library calls). Differential Revision: http://reviews.llvm.org/D11012 llvm-svn: 245115
* [AArch64] Fix FMLS scalar-indexed-from-2s-after-neg patterns.Ahmed Bougacha2015-08-141-1/+3
| | | | | | | | | We canonicalize V64 vectors to V128 through insert_subvector: the other FMLA/FMLS/FMUL/FMULX patterns match that already, but this one doesn't, so we'd fail to match fmls and generate fneg+fmla instead. The vector equivalents are already tested and functional. llvm-svn: 245107
* [msan] Fix handling of musttail calls.Evgeniy Stepanov2015-08-141-0/+20
| | | | | | | MSan instrumentation for return values of musttail calls is not allowed by the IR constraints, and not needed at the same time. llvm-svn: 245106
* MIR Serialization: Serialize the '.cfi_same_value' CFI directive.Alex Lorenz2015-08-144-0/+15
| | | | llvm-svn: 245103
* MIR Serialization: Serialize the external symbol call entry pseudo sourceAlex Lorenz2015-08-142-5/+10
| | | | | | values. llvm-svn: 245098
* MIR Serialization: Serialize the global value call entry pseudo source values.Alex Lorenz2015-08-142-1/+14
| | | | llvm-svn: 245097
* AMDGPU/SI: Add missing spill classTom Stellard2015-08-141-1/+2
| | | | | | | | The compiler was failing to spill for some shaders. Patch By: Axel Davy llvm-svn: 245087
* Revert "[ARM] Fix MachO CPU Subtype selection"Renato Golin2015-08-142-37/+12
| | | | | | This reverts commit r245081, as it breaks many builds. llvm-svn: 245086
* MIR Serialization: Serialize the 'internal' register operand flag.Alex Lorenz2015-08-144-4/+13
| | | | llvm-svn: 245085
* MIR Serialization: Serialize the bundled machine instructions.Alex Lorenz2015-08-144-10/+63
| | | | llvm-svn: 245082
* [ARM] Fix MachO CPU Subtype selectionVedant Kumar2015-08-142-12/+37
| | | | | | | | | | This patch makes the Darwin ARM backend take advantage of TargetParser. It also teaches TargetParser about ARMV7K for the first time. This makes target triple parsing more consistent across llvm. Differential Revision: http://reviews.llvm.org/D11996 llvm-svn: 245081
* [x86] fix allowsMisalignedMemoryAccess() implementationSanjay Patel2015-08-141-10/+27
| | | | | | | | | | | | | | | | This patch fixes the x86 implementation of allowsMisalignedMemoryAccess() to correctly return the 'Fast' output parameter for 32-byte accesses. To test that, an existing load merging optimization is changed to use the TLI hook. This exposes a shortcoming in the current logic and results in the regression test update. Changing other direct users of the isUnalignedMem32Slow() x86 CPU attribute would be a follow-on patch. Without the fix in allowsMisalignedMemoryAccesses(), we will infinite loop when targeting SandyBridge because LowerINSERT_SUBVECTOR() creates 32-byte loads from two 16-byte loads while PerformLOADCombine() splits them back into 16-byte loads. Differential Revision: http://reviews.llvm.org/D10662 llvm-svn: 245075
* [sancov] Fix an unused variable warning introduced in r245067Justin Bogner2015-08-141-1/+1
| | | | llvm-svn: 245072
* Reverting patch r244235.Kit Barton2015-08-142-50/+22
| | | | | | | | This patch will be redone in a different way. See http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20150810/292978.html for more details. llvm-svn: 245071
* [sancov] Leave llvm.localescape in the entry blockReid Kleckner2015-08-142-9/+40
| | | | | | | | | | | | Summary: Similar to the change we applied to ASan. The same test case works. Reviewers: samsonov Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11961 llvm-svn: 245067
* Revert "Centralize the information about which object format we are using."Rafael Espindola2015-08-145-45/+64
| | | | | | | | | | | | | | | | | | | | | This reverts commit r245047. It was failing on the darwin bots. The problem was that when running ./bin/llc -march=msp430 llc gets to if (TheTriple.getTriple().empty()) TheTriple.setTriple(sys::getDefaultTargetTriple()); Which means that we go with an arch of msp430 but a triple of x86_64-apple-darwin14.4.0 which fails badly. That code has to be updated to select a triple based on the value of march, but that is not a trivial fix. llvm-svn: 245062
* don't repeaat function names in comments; NFCSanjay Patel2015-08-141-11/+8
| | | | llvm-svn: 245058
* Centralize the information about which object format we are using.Rafael Espindola2015-08-145-64/+45
| | | | | | | | | | | Other than some places that were handling unknown as ELF, this should have no change. The test updates are because we were detecting arm-coff or x86_64-win64-coff as ELF targets before. It is not clear if the enum should live on the Triple. At least now it lives in a single location and should be easier to move somewhere else. llvm-svn: 245047
* Separate out BDCE's analysis into a separate DemandedBits analysis.James Molloy2015-08-144-328/+384
| | | | | | | This allows other areas of the compiler to use BDCE's bit-tracking. NFCI. llvm-svn: 245039
* [AArch64] FMINNAN/FMAXNAN on f16 is not legal.James Molloy2015-08-141-2/+4
| | | | | | | | Spotted by Ahmed - in r244594 I inadvertently marked f16 min/max as legal. I've reverted it here, and marked min/max on scalar f16's as promote. I've also added a testcase. The test just checks that the compiler doesn't fall over - it doesn't create fmin nodes for f16 yet. llvm-svn: 245035
* [LVer] Remove unused Pass parameter from versionLoop, NFCAdam Nemet2015-08-142-2/+2
| | | | llvm-svn: 245032
* [RuntimeDyld] Make sure code-sections aren't under-aligned.Lang Hames2015-08-141-0/+6
| | | | | | | | | | | | | | | | | | Code-section alignment should be at least as high as the minimum stub alignment. If the section alignment is lower it can cause padding to be emitted resulting in alignment errors if the section is mapped to a higher alignment on the target. E.g. If a text section with a 4-byte alignment gets 4-bytes of padding to guarantee 8-byte alignment for stubs but is re-mapped to an 8-byte alignment on the target, the 4-bytes of padding will push the stubs to 4-byte alignment causing a crash. No test case: There is currently no way to control host section alignment in llvm-rtdyld. This could be made testable by adding a custom memory manager. I'll look at that in a follow-up patch. llvm-svn: 245031
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