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* Enable FastISel on ARM for Linux and NaClJF Bastien2013-05-291-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | FastISel was only enabled for iOS ARM and Thumb2, this patch enables it for ARM (not Thumb2) on Linux and NaCl. Thumb2 support needs a bit more work, mainly around register class restrictions. The patch punts to SelectionDAG when doing TLS relocation on non-Darwin targets. I will fix this and other FastISel-to-SelectionDAG failures in a separate patch. The patch also forces FastISel to retain frame pointers: iOS always keeps them for backtracking (so emitted code won't change because of this), but Linux was getting much worse code that was incorrect when using big frames (such as test-suite's lencod). I'll also fix this in a later patch, it will probably require a peephole so that FastISel doesn't rematerialize frame pointers back-to-back. The test changes are straightforward, similar to: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html They also add a vararg test that got dropped in that change. I ran all of test-suite on A15 hardware with --optimize-option=-O0 and all the tests pass. llvm-svn: 182877
* Don't reach into the middle of TargetMachine and cache one of its ivars.Bill Wendling2013-05-293-3/+4
| | | | | | Not only does this break encapsulation, it's gross. llvm-svn: 182876
* Teach ReMaterialization to be more cunning about subregistersTim Northover2013-05-291-18/+65
| | | | | | | | | | | | | | | | This allows rematerialization during register coalescing to handle more cases involving operations like SUBREG_TO_REG which might need to be rematerialized using sub-register indices. For example, code like: v1(GPR64):sub_32 = MOVZ something v2(GPR64) = COPY v1(GPR64) should be convertable to: v2(GPR64):sub_32 = MOVZ something but previously we just gave up in places like this llvm-svn: 182872
* Simplify logic by using the appropriate functions.Adrian Prantl2013-05-291-2/+1
| | | | llvm-svn: 182869
* LTO+Debug Info: revert r182791.Manman Ren2013-05-293-54/+13
| | | | | | | | | | | | Since the testing case uses ref_addr, which requires version 3+ to work, we will solve the dwarf version issue first. This patch also causes failures in one of the bots. I will update the patch accordingly in my next attempt. rdar://13926659 llvm-svn: 182867
* Tidy some register classes for ARM and ThumbJF Bastien2013-05-292-3/+3
| | | | | | | | | | | | | | | | | | Tidy up three places where the register class for ARM and Thumb wasn't restrictive enough: - No PC dest for reg-reg add/orr/sub. - No PC dest for shifts. - No PC or SP for Thumb2 reg-imm add. I encountered this while combining FastISel with -verify-machineinstrs. These instructions defined registers whose classes weren't restrictive enough, and the uses failed verification. They're also undefined in the ISA, or would produce code that FastISel wouldn't want. This doesn't fix the register class narrowing issue (where uses should restrict definitions), and isn't thorough, but it's a small step in the right direction. llvm-svn: 182863
* SparcFrameLowering.cpp: Mark verifyLeafProcRegUse() as UNUSED. ↵NAKAMURA Takumi2013-05-291-1/+1
| | | | | | [-Wunused-function] llvm-svn: 182850
* [SystemZ] Immediate compare-and-branch supportRichard Sandiford2013-05-297-11/+59
| | | | | | This patch adds support for the CIJ and CGIJ instructions. llvm-svn: 182846
* Temporary fix to get rid of gcc warning.Patrik Hagglund2013-05-291-1/+10
| | | | llvm-svn: 182832
* [Sparc] Add support for leaf functions in sparc backend. Venkatraman Govindaraju2013-05-296-28/+123
| | | | llvm-svn: 182822
* LoopVectorize.cpp: Fix abuse of StringRef on Twine. Twine captures the ↵NAKAMURA Takumi2013-05-291-2/+1
| | | | | | pointer of StringRef. llvm-svn: 182820
* Whitespace.NAKAMURA Takumi2013-05-291-4/+4
| | | | llvm-svn: 182819
* Mips assembler: Improve set register alias handlingJack Carter2013-05-281-5/+28
| | | | | | | | | | | | | | | | This patch solves the problem of numeric register values not being accepted: ../set_alias.s:1:11: error: expected valid expression after comma .set r4,$4 ^ The parsing of .set directive is changed and handling of symbols in code as well to enable this feature. The test example is added. Patch by Vladimir Medic llvm-svn: 182807
* AArch64: clarify -help messageTim Northover2013-05-281-1/+1
| | | | llvm-svn: 182804
* Add support for llvm.vectorizer metadataPaul Redmond2013-05-282-26/+196
| | | | | | | | | | | | | | | | | | | - llvm.loop.parallel metadata has been renamed to llvm.loop to be more generic by making the root of additional loop metadata. - Loop::isAnnotatedParallel now looks for llvm.loop and associated llvm.mem.parallel_loop_access - document llvm.loop and update llvm.mem.parallel_loop_access - add support for llvm.vectorizer.width and llvm.vectorizer.unroll - document llvm.vectorizer.* metadata - add utility class LoopVectorizerHints for getting/setting loop metadata - use llvm.vectorizer.width=1 to indicate already vectorized instead of already_vectorized - update existing tests that used llvm.loop.parallel and llvm.vectorizer.already_vectorized Reviewed by: Nadav Rotem llvm-svn: 182802
* [APInt] Implement tcDecrement as a counterpart to tcIncrement. This is for ↵Michael Gottesman2013-05-281-0/+14
| | | | | | | | use in APFloat IEEE-754R 2008 nextUp/nextDown function. rdar://13852078 llvm-svn: 182801
* ARM: use pristine object file while processing relocationsTim Northover2013-05-281-15/+23
| | | | | | | | | | | | | | Previously we would read-modify-write the target bits when processing relocations for the MCJIT. This had the problem that when relocations were processed multiple times for the same object file (as they can be), the result is not idempotent and the values became corrupted. The solution to this is to take any bits used in the destination from the pristine object file as LLVM emitted it. This should fix PR16013 and remote MCJIT on ARM ELF targets. llvm-svn: 182800
* LTO+Debug Info: correctly emit inlined_subroutine when the inlined callee isManman Ren2013-05-283-13/+54
| | | | | | | | | | | | from a different CU. We used to print out an error message and fail to generate inlined_subroutine. If we use ref_addr in the generated DWARF, the DWARF version should be 3 or above. rdar://13926659 llvm-svn: 182791
* Hexagon: Typo fix.Jyotsna Verma2013-05-281-5/+5
| | | | llvm-svn: 182790
* Simplify code. No functionality change.Benjamin Kramer2013-05-281-3/+2
| | | | llvm-svn: 182779
* Remove double semicolons.Benjamin Kramer2013-05-283-62/+62
| | | | llvm-svn: 182778
* Extend RemapInstruction and friends to take an optional new parameter, a ↵James Molloy2013-05-283-62/+99
| | | | | | | | ValueMaterializer. Extend LinkModules to pass a ValueMaterializer to RemapInstruction and friends to lazily create Functions for lazily linked globals. This is a big win when linking small modules with large (mostly unused) library modules. llvm-svn: 182776
* [msan] Fix argument shadow alignment.Evgeniy Stepanov2013-05-281-4/+11
| | | | llvm-svn: 182771
* [SystemZ] Register compare-and-branch supportRichard Sandiford2013-05-287-28/+237
| | | | | | | | | | | | | | This patch adds support for the CRJ and CGRJ instructions. Support for the immediate forms will be a separate patch. The architecture has a large number of comparison instructions. I think it's generally better to concentrate on using the "best" comparison instruction first and foremost, then only use something like CRJ if CR really was the natual choice of comparison instruction. The patch therefore opportunistically converts separate CR and BRC instructions into a single CRJ while emitting instructions in ISelLowering. llvm-svn: 182764
* [SystemZ] Tweak SystemZInstrInfo::isBranch() interfaceRichard Sandiford2013-05-283-33/+34
| | | | | | | This is needed for the upcoming compare-and-branch patch. No functional change intended. llvm-svn: 182762
* Make BasicAliasAnalysis recognize the fact a noalias argument cannot alias ↵Michael Kuperstein2013-05-282-4/+24
| | | | | | another argument, even if the other argument is not itself marked noalias. llvm-svn: 182755
* Make it explicit that GlobalAlias are ok in llvm.used.Rafael Espindola2013-05-271-5/+4
| | | | | | No functionality change. llvm-svn: 182747
* Make helper functions static.Rafael Espindola2013-05-274-113/+65
| | | | | | And remove header and cpp file that are empty after that. llvm-svn: 182746
* Convert sqrt functions into sqrt instructions when -ffast-math is in effect.Preston Gurd2013-05-272-0/+6
| | | | | | | | | | | | When -ffast-math is in effect (on Linux, at least), clang defines __FINITE_MATH_ONLY__ > 0 when including <math.h>. This causes the preprocessor to include <bits/math-finite.h>, which renames the sqrt functions. For instance, "sqrt" is renamed as "__sqrt_finite". This patch adds the 3 new names in such a way that they will be treated as equivalent to their respective original names. llvm-svn: 182739
* PPC: Add a isConsecutiveLS utility functionHal Finkel2013-05-271-2/+42
| | | | | | | | | | | | | isConsecutiveLS is a slightly more general form of SelectionDAG::isConsecutiveLoad. Aside from also handling stores, it also does not assume equality of the chain operands is necessary. In the case of the PPC backend, this chain condition is checked in a more general way by the surrounding code. Mostly, this part of the refactoring in preparation for supporting optimized unaligned stores. llvm-svn: 182723
* Prefer to duplicate PPC Altivec loads when expanding unaligned loadsHal Finkel2013-05-261-3/+79
| | | | | | | | | | | | | | | | | | | When expanding unaligned Altivec loads, we use the decremented offset trick to prevent page faults. Unfortunately, if we have a sequence of consecutive unaligned loads, this leads to suboptimal code generation because the 'extra' load from the first unaligned load can be combined with the base load from the second (but only if the decremented offset trick is not used for the first). Search up and down the chain, through loads and token factors, looking for consecutive loads, and if one is found, don't use the offset reduction trick. These duplicate loads are later combined to yield the desired sequence (in the future, we might want a more-powerful chain search, but that will require some changes to allow the combiner routines to access the AA object). This should complete the initial implementation of the optimized unaligned Altivec load expansion. There is some refactoring that should be done, but that will happen when the unaligned store expansion is added. llvm-svn: 182719
* Fix PR16143: Insert DEBUG_VALUE before terminator.Andrew Trick2013-05-261-1/+1
| | | | llvm-svn: 182717
* Add support for DWARF line number table entries for values in the instructionCameron Zwarich2013-05-251-0/+2
| | | | | | stream. llvm-svn: 182712
* PPC: Combine duplicate (offset) lvsl Altivec intrinsicsHal Finkel2013-05-251-1/+28
| | | | | | | | | The lvsl permutation control instruction is a function only of the alignment of the pointer operand (relative to the 16-byte natural alignment of Altivec vectors). As a result, multiple lvsl intrinsics where the operands differ by a multiple of 16 can be combined. llvm-svn: 182708
* Track IR ordering of SelectionDAG nodes 3/4.Andrew Trick2013-05-2510-165/+17
| | | | | | | Remove the old IR ordering mechanism and switch to new one. Fix unit test failures. llvm-svn: 182704
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-2570-2026/+2028
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* Track IR ordering of SelectionDAG nodes 1/4.Andrew Trick2013-05-252-7/+15
| | | | | | | | Use a field in the SelectionDAGNode object to track its IR ordering. This adds fields and utility classes without changing existing interfaces or functionality. llvm-svn: 182701
* ArrayRef-ize MD5 and clean up a few variable names.Eric Christopher2013-05-241-20/+32
| | | | | | | Add a stringize method to make dumping a bit easier, and add a testcase exercising a few different paths. llvm-svn: 182692
* PPC: Initial support for permutation-based unaligned Altivec loadsHal Finkel2013-05-241-0/+129
| | | | | | | | | | | | | | | | | | Altivec only directly supports aligned loads, but the loads have a strange property: If given an unaligned address, they truncate the address to the next lower aligned address, and load from there. This property, along with an extra load and some special-purpose permutation-control instructions that generate the appropriate permutations from the original unaligned address, allow efficient lowering of aligned loads. This code uses the trick explained in the Apple Velocity Engine optimization overview document to prevent the needed extra load from possibly causing a page fault if the original address happens to be aligned. As noted in the FIXMEs, there are several additional optimizations that can be performed to reduce the cost of these loads even more. These will be implemented in future commits. llvm-svn: 182691
* Follow up of the introduction of MCSymbolizer.Quentin Colombet2013-05-246-12/+37
| | | | | | | - Ressurect old MCDisassemble API to soften transition. - Extend MCTargetDesc to set target specific symbolizer. llvm-svn: 182688
* Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.Michael J. Spencer2013-05-2433-75/+75
| | | | llvm-svn: 182680
* Add missing header for atexit.Michael J. Spencer2013-05-241-0/+2
| | | | llvm-svn: 182672
* [objc-arc] KnownSafe does not imply that it is safe to perform code motion ↵Michael Gottesman2013-05-241-8/+40
| | | | | | | | across CFG edges since even if it is safe to remove RR pairs, we may still be able to move a retain/release into a loop. rdar://13949644 llvm-svn: 182670
* [objc-arc] Make sure that multiple owners is propogated correctly through ↵Michael Gottesman2013-05-241-17/+16
| | | | | | | | the pass via the usage of a global data structure. rdar://13750319 llvm-svn: 182669
* LoopVectorize: LoopSimplify can't canonicalize loops with an indirectbr in ↵Benjamin Kramer2013-05-241-1/+4
| | | | | | | | it, don't assert on those cases. Fixes PR16139. llvm-svn: 182656
* Do not reserve space for the ColdEdges and NormalEdges vectors.Diego Novillo2013-05-241-2/+0
| | | | | | | Discussion and rationale at http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130520/175698.html llvm-svn: 182653
* [SystemZ] Improve AsmParser handling of invalid instructionsRichard Sandiford2013-05-241-74/+103
| | | | | | | | | | | | | | | | | | | | | | | Previously, an invalid instruction like: foo %r1, %r0 would generate the rather odd error message: ....: error: unknown token in expression foo %r1, %r0 ^ We now get the more informative: ....: error: invalid instruction foo %r1, %r0 ^ The same would happen if an address were used where a register was expected. We now get "invalid operand for instruction" instead. llvm-svn: 182644
* [SystemZ] Improve AsmParser register parsingRichard Sandiford2013-05-241-53/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The idea is to make sure that: (1) "register expected" is restricted to cases where ParseRegister() is called and the token obviously isn't a register. (2) "invalid register" is restricted to cases where a register-like "%..." sequence is found, but the "..." makes no sense. (3) the generic "invalid operand for instruction" is used in cases where the wrong register type is used (GPR instead of FPR, etc.). (4) the new "invalid register pair" is used if the register has the right type, but is not a valid register pair. Testing of (1)-(3) is now restricted to regs-bad.s. It uses a representative instruction for each register class to make sure that only registers from that class are accepted. (4) is tested by both regs-bad.s (which checks all invalid register pairs) and insn-bad.s (which tests one invalid pair for each instruction that requires a pair). While there, I changed "Number" to "Num" for consistency with the operand class. llvm-svn: 182643
* Run clang-format over the scalarizePHI function.Joey Gouly2013-05-241-12/+8
| | | | llvm-svn: 182640
* scalarizePHI needs to insert the next ExtractElement in the same blockJoey Gouly2013-05-241-2/+4
| | | | | | | | as the BinaryOperator, *not* in the block where the IRBuilder is currently inserting into. Fixes a bug where scalarizePHI would create instructions that would not dominate all uses. llvm-svn: 182639
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