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* Attempting to fix WinEHCatchDirector destructor related build failures.Andrew Kaylor2015-02-231-0/+1
| | | | llvm-svn: 230252
* Remap frame variables for native Windows exception handling.Andrew Kaylor2015-02-232-392/+649
| | | | | | Differential Revision: http://reviews.llvm.org/D7770 llvm-svn: 230249
* Revert "[X86][MMX] Add MMX instructions to foldable tables"Bruno Cardoso Lopes2015-02-231-82/+0
| | | | | | This reverts commit r230226 since it breaks win buildbots. llvm-svn: 230248
* Revert "Revert "Raising minimum required CMake version to 2.8.12.2.""Chad Rosier2015-02-232-2/+2
| | | | | | This reverts commit r230240, which was an accidental commit. llvm-svn: 230246
* Rewrite the global merge pass to be subprogram agnostic for now.Eric Christopher2015-02-237-42/+28
| | | | | | | | | | | | | It was previously using the subtarget to get values for the global offset without actually checking each function as it was generating code. Go ahead and solidify the current behavior and make the existing FIXMEs more prominent. As a note the ARM backend previously had a thumb1 and non-thumb1 set of defaults. Only the former was tested so I've changed the behavior to only use that for now. llvm-svn: 230245
* Prevent hoisting fmul from THEN/ELSE to IF if there is fmsub/fmadd opportunity.Chad Rosier2015-02-234-2/+41
| | | | | | | | | | | This patch adds the isProfitableToHoist API. For AArch64, we want to prevent a fmul from being hoisted in cases where it is more profitable to form a fmsub/fmadd. Phabricator Review: http://reviews.llvm.org/D7299 Patch by Lawrence Hu <lawrence@codeaurora.org> llvm-svn: 230241
* Revert "Raising minimum required CMake version to 2.8.12.2."Chad Rosier2015-02-232-2/+2
| | | | | | This reverts commit 247aed4710e8befde76da42b27313661dea7cf66. llvm-svn: 230240
* InstSimplify: simplify 0 / X if nnan and nszMehdi Amini2015-02-232-16/+34
| | | | | From: Fiona Glaser <fglaser@apple.com> llvm-svn: 230238
* [mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled.Daniel Sanders2015-02-232-5/+20
| | | | | | | | | | | | | | | | | | | Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
* Fix incorrect immediate size for AddrModeT2_i8s4 in rewriteT2FrameIndex.Bob Wilson2015-02-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The natural way to handle this addressing mode would be to say that it has 8 bits and gets scaled by 4, but since the MC layer is expecting the scaling to be already reflected in the immediate value, we have been setting the Scale to 1. That's fine, but then NumBits needs to be adjusted to reflect the effective increase in the range of the immediate. That adjustment was missing. The consequence is that the register scavenger can fail. The estimateRSStackSizeLimit() function in ARMFrameLowering.cpp correctly assumes that the AddrModeT2_i8s4 address mode can handle scaled offsets up to 1020. Under just the right circumstances, we fail to reserve space for the scavenger because it thinks that nothing will be needed. However, the overly pessimistic behavior in rewriteT2FrameIndex causes some frame indexes to be out of range and require scavenged registers, and so the scavenger asserts. Unfortunately I have not been able to come up with a testcase for this. I can only reproduce it on an internal branch where the frame layout and register allocation is slightly different than trunk. We really need a way to serialize MachineInstr-level IR to write reasonable tests for things like this. rdar://problem/19909005 llvm-svn: 230233
* Sync the __builtin_expects for our 3 quadratically probed hash table ↵Benjamin Kramer2015-02-232-11/+13
| | | | | | | | | | | | | | | | | | implementations. This assumes that a) finding the bucket containing the value is LIKELY b) finding an empty bucket is LIKELY c) growing the table is UNLIKELY I also switched the a) and b) cases for SmallPtrSet as we seem to use the set mostly more for insertion than for checking existence. In a simple benchmark consisting of 2^21 insertions of 2^20 unique pointers into a DenseMap or SmallPtrSet a few percent speedup on average, but nothing statistically significant. llvm-svn: 230232
* [X86][MMX] Add MMX instructions to foldable tablesBruno Cardoso Lopes2015-02-231-0/+82
| | | | | | | | Teach the peephole optimizer to work with MMX instructions by adding entries into the foldable tables. This covers folding opportunities not handled during isel. llvm-svn: 230226
* [X86][MMX] Support folding loads in psll, psrl and psra intrinsicsBruno Cardoso Lopes2015-02-232-0/+21
| | | | llvm-svn: 230225
* AVX-512: recommitted 229837 + bugfix + testElena Demikhovsky2015-02-235-47/+87
| | | | llvm-svn: 230223
* restructured X86 scalar unary operation templatesElena Demikhovsky2015-02-231-164/+118
| | | | | | | I made the templates general, no need to define pattern separately for each instruction/intrinsic. Now only need to add r_Int pattern for AVX. llvm-svn: 230221
* AsmParser: Check ConstantExpr insertvalue operands for type correctnessDavid Majnemer2015-02-231-1/+8
| | | | llvm-svn: 230206
* [llvm-pdbdump] Very minor code cleanup.Zachary Turner2015-02-233-20/+15
| | | | | | | This just removes some dead enums as well as some debug flushes of stdout. llvm-svn: 230204
* [llvm-pdbdump] Add an option to dump full class definitions.Zachary Turner2015-02-235-4/+95
| | | | | | | | | | | This adds the --class-definitions flag. If specified, when dumping types, instead of "class Foo" you will see the full class definition, with member functions, constructors, access specifiers. NOTE: Using this option can be very slow, as generating a full class definition requires accessing many different parts of the PDB. llvm-svn: 230203
* AsmParser: Call instructions can't have an alignmentDavid Majnemer2015-02-231-2/+10
| | | | llvm-svn: 230193
* AsmParser: Check ConstantExpr GEP operands for validityDavid Majnemer2015-02-221-2/+24
| | | | llvm-svn: 230188
* [llvm-pdbdump] Rewrite dumper using visitor pattern.Zachary Turner2015-02-2235-498/+293
| | | | | | | | | | This increases the flexibility of how to dump different symbol types -- necessary for context-sensitive formatting of symbol types -- and also improves the modularity by allowing the dumping to be implemented in the actual dumper, as opposed to in the PDB library. llvm-svn: 230184
* [llvm-pdbdump] Simplify options and output.Zachary Turner2015-02-221-0/+1
| | | | | | | | | This removes a wealth of options, and instead now only provides three options. -symbols, -types, and -compilands. This greatly simplifies use of the tool, and makes it easier to understand what you're going to see when you run the tool. llvm-svn: 230182
* Roll condition into an assert then wrap it 'ifndef NDEBUG' to protect from ↵David Blaikie2015-02-221-8/+7
| | | | | | the inevitable "unused variable" warning in a non-asserts build. llvm-svn: 230181
* Use common parse routine to read alignment values from bitcodeJF Bastien2015-02-222-14/+46
| | | | | | | | | | While fuzzing LLVM bitcode files, I discovered that (1) the bitcode reader doesn't check that alignments are no larger than 2**29; (2) downstream code doesn't check the range; and (3) for values out of range, corresponding large memory requests (based on alignment size) will fail. This code fixes the bitcode reader to check for valid alignments, fixing this problem. This CL fixes alignment value on global variables, functions, and instructions: alloca, load, load atomic, store, store atomic. Patch by Karl Schimpf (kschimpf@google.com). llvm-svn: 230180
* [LICM] Refactor to expose functionality as utility functionsHal Finkel2015-02-221-173/+199
| | | | | | | | | | | This refactors the core functionality of LICM: HoistRegion, SinkRegion and PromoteAliasSet (renamed to promoteLoopAccessesToScalars) as utility functions in LoopUtils. This will enable other transformations to make use of them directly. Patch by Ashutosh Nema. llvm-svn: 230178
* [DagCombiner] Generalized BuildVector Vector ConcatenationSimon Pilgrim2015-02-221-23/+38
| | | | | | | | | | | | The CONCAT_VECTORS combiner pass can transform the concat of two BUILD_VECTOR nodes into a single BUILD_VECTOR node. This patch generalises this to support any number of BUILD_VECTOR nodes, and also permits UNDEF nodes to be included as well. This was noticed as AVX vec128 -> vec256 canonicalization sometimes creates a CONCAT_VECTOR with a real vec128 lower and an vec128 UNDEF upper. Differential Revision: http://reviews.llvm.org/D7816 llvm-svn: 230177
* [DAGCombine] Don't assume integer-type legailty in ↵Hal Finkel2015-02-221-0/+5
| | | | | | | | | | | | | | | | | | reduceBuildVecConvertToConvertBuildVec DAGCombine will rewrite an BUILD_VECTOR where all non-undef inputs some from [US]INT_TO_FP, as a BUILD_VECTOR of integers with the conversion applied as a vector operation. We check operation legality of the conversion, but fail to check legality of the integer vector type itself. Because targets don't normally override operation legality defaults for illegal types, we need to check this also. This came up in the context of the QPX vector entensions for PowerPC (which can have legal floating-point vector types without corresponding legal integer vector types). No in-tree test case for this yes, but one can be added once the QPX support has been committed. llvm-svn: 230176
* [SDAG] Use correct alignments on expanded vector trunc-store/ext-loadsHal Finkel2015-02-221-4/+7
| | | | | | | | | | | | | When expanding a truncating store or extending load using vector extracts or inserts and scalar stores and loads, we were giving each of these scalar stores or loads the same alignment as the original vector operation. While this will often be right (most vector operations, especially those produced by autovectorization, have the alignment of the underlying scalar type), the vector operation could certainly have a larger alignment. No test case (yet); noticed by inspection. llvm-svn: 230175
* Fix a warning on HexagonMCCodeEmitter::MCII. [-Wunused-private-field]NAKAMURA Takumi2015-02-221-0/+1
| | | | llvm-svn: 230170
* RewriteStatepointsForGC.cpp: Fix for -Asserts to mark isNullConstant() as ↵NAKAMURA Takumi2015-02-221-1/+1
| | | | | | LLVM_ATTRIBUTE_UNUSED. [-Wunused-function] llvm-svn: 230169
* RewriteStatepointsForGC.cpp: Fix for -Asserts. [-Wunused-variable]NAKAMURA Takumi2015-02-221-2/+1
| | | | llvm-svn: 230168
* LowerBitSets.cpp: Prune incorrect \param(s). [-Wdocumentation]NAKAMURA Takumi2015-02-221-6/+6
| | | | | | \param should be used as itemized. llvm-svn: 230167
* [X86] Add some missing redundant MMX and SSE encodings for disassembler.Craig Topper2015-02-222-0/+28
| | | | llvm-svn: 230165
* COFF: Add 'IMAGE_SCN_CNT_INITIALIZED_DATA' to all DWARF sectionsDavid Majnemer2015-02-221-0/+25
| | | | | | | The CodeView debug info section, .debug$S, also has this set. MinGW sets this bit for their DWARF sections as well. llvm-svn: 230156
* COFF: Consistently format the DWARF sectionsDavid Majnemer2015-02-221-45/+44
| | | | llvm-svn: 230155
* [Orc] Remove redundant using directive.Lang Hames2015-02-221-2/+0
| | | | llvm-svn: 230154
* [Orc] Add header comment to IndirectionUtils.cpp.Lang Hames2015-02-221-0/+9
| | | | llvm-svn: 230153
* IRCE: generalize InductiveRangeCheck::computeSafeIterationSpace toSanjoy Das2015-02-211-32/+57
| | | | | | | | | | work with a non-canonical induction variable. This is currently a non-functional change because we only ever call computeSafeIterationSpace on a canonical induction variable; but the generalization will be useful in a later commit. llvm-svn: 230151
* IRCE: use SCEVs instead of llvm::Value's for intermediateSanjoy Das2015-02-211-46/+30
| | | | | | | | | calculations. Semantically non-functional change. This gets rid of some of the SCEV -> Value -> SCEV round tripping and the Construct(SMin|SMax)Of and MaybeSimplify helper routines. llvm-svn: 230150
* R600/SI: Use v_madmk_f32Matt Arsenault2015-02-211-4/+51
| | | | llvm-svn: 230149
* R600/SI: Try to use v_madak_f32Matt Arsenault2015-02-212-0/+81
| | | | | | | This is a code size optimization when the constant only has one use. llvm-svn: 230148
* R600/SI: Don't crash when getting immediate operand sizeMatt Arsenault2015-02-211-0/+7
| | | | llvm-svn: 230147
* R600/SI: Fix mad*k definitionsMatt Arsenault2015-02-214-2/+40
| | | | llvm-svn: 230146
* [Orc] Move Orc code into a namespace (llvm::orc), update Kaleidoscope code.Lang Hames2015-02-215-14/+29
| | | | | | NFC. llvm-svn: 230143
* MachineInstr: Use range-based for loops. NFC.Benjamin Kramer2015-02-211-34/+20
| | | | llvm-svn: 230142
* Calling memmove on a MachineOperand is totally safe.Benjamin Kramer2015-02-211-8/+2
| | | | | | | While it's not POD due to the user-defined constructor, it's still a trivially copyable type. No functional change. llvm-svn: 230141
* Remove dead prototype.Benjamin Kramer2015-02-211-1/+0
| | | | llvm-svn: 230137
* X86: Remove custom lowering of SIGN_EXTEND_INREGBenjamin Kramer2015-02-211-68/+0
| | | | | | | This was just replicating logic from the legalizer. Covered by existing tests. llvm-svn: 230136
* Unconditionally create a new MCInstrInfo in the asm printer forEric Christopher2015-02-211-5/+4
| | | | | | | | asm parsing since it's not subtarget dependent and we can't depend upon the one hanging off the MachineFunction's subtarget still being around. llvm-svn: 230135
* Remove obsolete comment.Eric Christopher2015-02-211-5/+0
| | | | llvm-svn: 230134
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