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* [AMDGPU] Add options for waitcnt pass debugging; add instr count in debug ↵Mark Searles2017-12-071-8/+62
| | | | | | | | | | | | | output. -amdgpu-waitcnt-forcezero={1|0} Force all waitcnt instrs to be emitted as s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -amdgpu-waitcnt-forceexp=<n> Force emit a s_waitcnt expcnt(0) before the first <n> instrs -amdgpu-waitcnt-forcelgkm=<n> Force emit a s_waitcnt lgkmcnt(0) before the first <n> instrs -amdgpu-waitcnt-forcevm=<n> Force emit a s_waitcnt vmcnt(0) before the first <n> instrs Differential Revision: https://reviews.llvm.org/D40091 llvm-svn: 320084
* [AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and ↵Mark Searles2017-12-072-17/+64
| | | | | | | | GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards(). Differential Revision: https://reviews.llvm.org/D40098 llvm-svn: 320083
* [X86] Fix InsertBitToMaskVector to only issue KSHIFTS of native size so that ↵Craig Topper2017-12-071-7/+33
| | | | | | | | | | | | upper bits are properly zeroed. There's no v2i1 or v4i1 kshift, and v8i1 is only supported with AVXDQ. Isel has fake patterns to extend these types to native shifts, but makes no guarantees about the value of any bits shifted in when shifting right. This patch promotes the vector to a type that supports a native shift first and only allows inserting into the msb of a native sized shift. I've constructed this in a way that doesn't do the promotion if we're going to fallback to using a xmm/ymm/zmm shuffle. I think I have a plan to remove the shuffle fall back entirely. In which case we this can be simplified, but I wanted to fix the correctness issue first. llvm-svn: 320081
* [X86] Fix typo in variable name. NFCCraig Topper2017-12-071-4/+4
| | | | llvm-svn: 320080
* [X86] Make a couple helper lowering methods static.Craig Topper2017-12-072-7/+4
| | | | llvm-svn: 320079
* [X86] Replace tabs with spaces. NFCI.Simon Pilgrim2017-12-071-12/+12
| | | | llvm-svn: 320065
* [X86] Tag BMI/BMI2/TBM instructions scheduler classesSimon Pilgrim2017-12-071-16/+16
| | | | | | Put these under UNARY/BINOP ALU itinerary classes for now - seems to be a good average value llvm-svn: 320064
* [Hexagon] Generate HVX code for basic arithmetic operationsKrzysztof Parzyszek2017-12-074-30/+137
| | | | | | Handle and, or, xor, add, sub, mul for vectors of i8, i16, and i32. llvm-svn: 320063
* [CodeGen] Fix index when printing tied machine operandsFrancis Visoiu Mistrih2017-12-071-3/+3
| | | | llvm-svn: 320061
* [X86] Tag SALC instructions scheduler classSimon Pilgrim2017-12-071-2/+2
| | | | | | Treat these the same as LAHF/SAHF (although its not a x86_64 instruction) llvm-svn: 320055
* [X86][VMX] Tag VMX instructions scheduler classesSimon Pilgrim2017-12-072-21/+32
| | | | | | Tagged all as system instructions llvm-svn: 320053
* [X86] Tag LZCNT/TZCNT instructions scheduler classesSimon Pilgrim2017-12-072-18/+28
| | | | | | Tagged as IMUL instructions for a reasonable approximation (ALU tends to be a lot faster) - POPCNT is currently tagged as FAdd which I think should be replaced with IMUL as well llvm-svn: 320051
* [DAGCombiner] eliminate shuffle of insert elementSanjay Patel2017-12-071-0/+81
| | | | | | | | | | | | | | | | | | | I noticed this pattern in D38316 / D38388. We failed to combine a shuffle that is either repeating a scalar insertion at the same position in a vector or translated to a different element index. Like the earlier patch, this could be an instcombine too, but since we opted to make this a DAG transform earlier, I've made this one a DAG patch too. We do not need any legality checking because the new insert is identical to the existing insert except that it may have a different constant insertion operand. The constant insertion test in test/CodeGen/X86/vector-shuffle-combining.ll was the motivation for D38756. Differential Revision: https://reviews.llvm.org/D40209 llvm-svn: 320050
* [InstCombine] Don't crash on out of bounds index in the insertelementIgor Laevsky2017-12-071-0/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D40390 llvm-svn: 320049
* [X86][SVM] Tag SVM instructions scheduler classesSimon Pilgrim2017-12-072-11/+15
| | | | | | Tagged all as system instructions llvm-svn: 320047
* [CodeGen] Use more getMFIfAvailableFrancis Visoiu Mistrih2017-12-071-16/+8
| | | | llvm-svn: 320046
* [X86] Tag RDRAND/RDSEED instruction scheduler classesSimon Pilgrim2017-12-072-8/+14
| | | | llvm-svn: 320045
* [X86][X87] X87 math binop pseudo instructions don't need scheduling infoSimon Pilgrim2017-12-071-0/+5
| | | | llvm-svn: 320044
* [X86][SSE42] SSE42 string pseudo instructions don't need scheduling infoSimon Pilgrim2017-12-071-4/+4
| | | | llvm-svn: 320043
* [WebAssemby] Support main functions with alternate signatures.Dan Gohman2017-12-071-1/+45
| | | | | | | | | | WebAssembly requires caller and callee signatures to match, so the usual C runtime trick of calling main and having it just work regardless of whether main is defined as '()' or '(int argc, char *argv[])' doesn't work. Extend the FixFunctionBitcasts pass to rewrite main to use the latter form. llvm-svn: 320041
* [RISCV] MC layer support for the jump/branch instructions of the RVC extensionAlex Bradbury2017-12-077-2/+164
| | | | | | | | Differential Revision: https://reviews.llvm.org/D40002 Patch by Shiva Chen. llvm-svn: 320038
* [RISCV] MC layer support for load/store instructions of the C (compressed) ↵Alex Bradbury2017-12-0711-22/+406
| | | | | | | | | | extension Differential Revision: https://reviews.llvm.org/D40001 Patch by Shiva Chen. llvm-svn: 320037
* [RISCV][NFC] Use TargetRegisterClass::hasSubClassEq in ↵Alex Bradbury2017-12-071-2/+2
| | | | | | | | | storeRegToStackSlot/loadReadFromStackSlot Simply checking for register class equality will break once additional register classes are added (as is done for the RVC instruction set extension). llvm-svn: 320036
* [Nios2] final infrastructure to provide compilation of a return from a functionNikolai Bozhenov2017-12-0745-109/+1857
| | | | | | | | | | | | This patch includes all missing functionality needed to provide first compilation of a simple program that just returns from a function. I've added a test case that checks for "ret" instruction printed in assembly output. Patch by Andrei Grischenko (andrei.l.grischenko@intel.com) Differential revision: https://reviews.llvm.org/D39688 llvm-svn: 320035
* Add proper BTVER2 sched support for MOV instr.Andrew V. Tischenko2017-12-071-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D40345 llvm-svn: 320034
* [FuzzMutate] Allow only sized pointers for the GEP instructionIgor Laevsky2017-12-071-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D40837 llvm-svn: 320032
* [RISCV] MC layer support for the standard RV64D instruction set extensionAlex Bradbury2017-12-071-0/+30
| | | | llvm-svn: 320029
* [RISCV] MC layer support for the standard RV64F instruction set extensionAlex Bradbury2017-12-071-0/+22
| | | | llvm-svn: 320028
* [RISCV] MC layer support for the standard RV64A instruction set extensionAlex Bradbury2017-12-071-0/+14
| | | | llvm-svn: 320027
* [RISCV] MC layer support for the standard RV64M instruction set extensionAlex Bradbury2017-12-071-0/+8
| | | | llvm-svn: 320026
* [RISCV] MC layer support for the standard RV64I instructionsAlex Bradbury2017-12-074-18/+111
| | | | llvm-svn: 320024
* [RISCV] MC layer support for the standard RV32D instruction set extensionAlex Bradbury2017-12-077-0/+258
| | | | | | | | | | | As the FPR32 and FPR64 registers have the same names, use validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an FPR64 when necessary. The rest of this patch is very similar to the RV32F patch. Differential Revision: https://reviews.llvm.org/D39895 llvm-svn: 320023
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-0763-433/+441
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. For MachineOperand::print, keep a simple version that can be easily called from `dump()`, and a more complex one which will be called from both the MIRPrinter and MachineInstr::print. Add extra checks inside MachineOperand for detached operands (operands with getParent() == nullptr). https://reviews.llvm.org/D40836 * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+)<def> ([^ ]+)/kill: \1 def \2 \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: def ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: def \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/<def>//g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<kill>/killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use,kill>/implicit killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<def[ ]*,[ ]*dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def[ ]*,[ ]*dead>/implicit-def dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def>/implicit-def \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use>/implicit \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<internal>/internal \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<undef>/undef \1/g' llvm-svn: 320022
* [RISCV] MC layer support for the standard RV32F instruction set extensionAlex Bradbury2017-12-0711-13/+397
| | | | | | | | | | | | | The most interesting part of this patch is probably the handling of rounding mode arguments. Sadly, the RISC-V assembler handles floating point rounding modes as a special "argument" when it would be more consistent to handle them like the atomics, opcode suffixes. This patch supports parsing this optional parameter, using InstAlias to allow parsing these floating point instructions when no rounding mode is specified. Differential Revision: https://reviews.llvm.org/D39893 llvm-svn: 320020
* [TableGen] Give the option of tolerating duplicate register namesAlex Bradbury2017-12-071-11/+14
| | | | | | | | | | | | | | | | | | A number of architectures re-use the same register names (e.g. for both 32-bit FPRs and 64-bit FPRs). They are currently unable to use the tablegen'erated MatchRegisterName and MatchRegisterAltName, as tablegen (when built with asserts enabled) will fail. When the AllowDuplicateRegisterNames in AsmParser is set, duplicated register names will be tolerated. A backend can then coerce registers to the desired register class by (for instance) implementing validateTargetOperandClass. At least the in-tree Sparc backend could benefit from this, as does RISC-V (single and double precision floating point registers). Differential Revision: https://reviews.llvm.org/D39845 llvm-svn: 320018
* [SelectionDAG] In SplitVecOp_EXTRACT_VECTOR_ELT, simplify the code that ↵Craig Topper2017-12-071-11/+2
| | | | | | | | makes the type byte addressable. We can just extend the original vector to vXi1 and trust that the legalization process will revisit it. llvm-svn: 320013
* [SelectionDAG] Use TLI.getVectorIdxTy to determine type for an ↵Craig Topper2017-12-071-1/+2
| | | | | | EXTRACT_VECTOR_ELT index instead of hardcoding MVT::i8. llvm-svn: 320012
* Skip DBG instr in OptimizePHIs when looking for dead PHI cyclesMikael Holmen2017-12-071-1/+1
| | | | | | | | | | | | | | | | | | | Summary: Changed use_instructions() to use_nodbg_instructions() when building an instruction set. We don't want the presence of debug info to affect the code we generate. Reviewers: dblaikie, Eugene.Zelenko, chandlerc, aprantl Reviewed By: aprantl Subscribers: aprantl, llvm-commits Differential Revision: https://reviews.llvm.org/D40882 llvm-svn: 320010
* [AVR] Override ParseDirectiveLeslie Zhai2017-12-0712-22/+285
| | | | | | | | | | Reviewers: dylanmckay, kparzysz Reviewed By: dylanmckay Differential Revision: https://reviews.llvm.org/D38029 llvm-svn: 320009
* Revert "[WebAssembly] Import the linear memory and function table."Sam Clegg2017-12-071-42/+40
| | | | | | | | | We need to a little time to prepare and lld-side change that supports this. Original change: https://reviews.llvm.org/D40875 llvm-svn: 320003
* [WebAssembly] section kind can be codeSam Clegg2017-12-071-1/+12
| | | | | | | | | | | | | Currently, when creating a named section, the Wasm frontend forces it to use `SectionKind::Data`, whereas in fact C++ does generate code sections with custom names. Patch by Nicholas Wilson Differential Revision: https://reviews.llvm.org/D40906 llvm-svn: 320002
* [MC/Dwarf] Use the older DWARF linetables format on Darwin.Davide Italiano2017-12-071-0/+3
| | | | | | | | | | dsymutil doesn't yet understand the new format and the change, among others, breaks a large fraction of the debugger tests on mac OS. rdar://problem/35856354 llvm-svn: 319995
* [ModRefInfo] Replace remaining bit-wise operations with wrappers.Alina Sbirlea2017-12-073-5/+5
| | | | llvm-svn: 319993
* [WebAssembly] Don't try to emit size information for unsized typesDan Gohman2017-12-071-5/+7
| | | | | | | | | | Patch by John Sully! Fixes PR35164. Differential Revision: https://reviews.llvm.org/D39519 llvm-svn: 319991
* [Coverage] Scan ahead for the most-recent completed count (PR35495)Vedant Kumar2017-12-071-5/+4
| | | | | | | | | This extends r319391. It teaches the segment builder to emit the right completed segment when more than one region ends at the same location. Fixes PR35495. llvm-svn: 319990
* [WebAssembly] Import the linear memory and function table.Dan Gohman2017-12-061-40/+42
| | | | | | | | | | | | Instead of having .o files contain linear-memory and function table definitions, use imports. This is more consistent with the stack pointer being imported, and it's consistent with the linker being the one to decide whether linear memory and function table are imported or defined in the linked output. This implements tool-conventions #23. Differential Revision: https://reviews.llvm.org/D40875 llvm-svn: 319989
* [AArch64] Add patterns to replace fsub fmul with fma fneg.Florian Hahn2017-12-061-3/+102
| | | | | | | | | | | | | | | | | | | Summary: This patch adds MachineCombiner patterns for transforming (fsub (fmul x y) z) into (fma x y (fneg z)). This has a lower latency on micro architectures where fneg is cheap. Patch based on work by George Steed. Reviewers: rengolin, joelkevinjones, joel_k_jones, evandro, efriedma Reviewed By: evandro Subscribers: aemerson, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D40306 llvm-svn: 319980
* [LV] Interleaved access vectorization: fix computing new alias infoAdam Nemet2017-12-061-2/+16
| | | | | | | | | | | As a new access is generated spanning across multiple fields, we need to propagate alias info from all the fields to form the most generic alias info. rdar://35602528 Differential Revision: https://reviews.llvm.org/D40617 llvm-svn: 319979
* [Hexagon] Recognize vdealb, vdealh, vshuffb and vshuffh specificallyKrzysztof Parzyszek2017-12-061-4/+37
| | | | llvm-svn: 319978
* [Hexagon] Handle perfect shuffles on single vectorsKrzysztof Parzyszek2017-12-061-6/+19
| | | | llvm-svn: 319965
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