summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* [X86][BTVER2] Use instrs instead of instregex for single use matches (PR35955)Simon Pilgrim2018-01-161-36/+33
| | | | llvm-svn: 322597
* Specify inline for isWhitespace in CommandLine.cppRui Ueyama2018-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Takuto Ikuta. In chromium's component build, there are many directive sections and commandline parsing takes much time. This patch is for speed up of lld in RelWithDebInfo build by forcing inline heavily called isWhitespace function. 10 times link perf stats of blink_core.dll changed like below. master: TotalSeconds: 9.8764878 TotalSeconds: 10.1455242 TotalSeconds: 10.075279 TotalSeconds: 10.3397347 TotalSeconds: 9.8361665 TotalSeconds: 9.9544441 TotalSeconds: 9.8960686 TotalSeconds: 9.8877865 TotalSeconds: 10.0551879 TotalSeconds: 10.0492254 Avg: 10.01159047 with this patch: TotalSeconds: 8.8696762 TotalSeconds: 9.1021585 TotalSeconds: 9.0233893 TotalSeconds: 9.1886175 TotalSeconds: 9.156954 TotalSeconds: 9.0978564 TotalSeconds: 9.1316824 TotalSeconds: 8.8354606 TotalSeconds: 9.2549431 TotalSeconds: 9.4473085 Avg: 9.11080465 llvm-svn: 322595
* [ExecutionEngine] Rename JITSymbol::isStrongDefinition to isStrong.Lang Hames2018-01-162-4/+4
| | | | | | For symmetry with isWeak, isCommon. llvm-svn: 322594
* [PPC] Add a new register XER aliased to CARRYGuozhi Wei2018-01-161-2/+6
| | | | | | | | | | When "xer" is specified as clobbered register in inline assembler, clang can accept it, but llvm simply ignore it when lowered to machine instructions. It may cause problems later in scheduler. This patch adds a new register XER aliased to CARRY, and adds it to register class CARRYRC. Now PPCTargetLowering::getRegForInlineAsmConstraint can return correct register number for inline asm constraint "{xer}", and scheduler behave correctly. Differential Revision: https://reviews.llvm.org/D41967 llvm-svn: 322591
* [CodeGen] Skip some instructions that shouldn't affect shrink-wrappingFrancis Visoiu Mistrih2018-01-161-5/+5
| | | | | | | | | | | r320606 checked for MI.isMetaInstruction which skips all DBG_VALUEs. This also skips IMPLICIT_DEFs and other instructions that may def / read a register. Differential Revision: https://reviews.llvm.org/D42119 llvm-svn: 322584
* [GlobalISel][TableGen] Add support for SDNodeXFormVolkan Keles2018-01-162-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds CustomRenderer which renders the matched operands to the specified instruction. Targets can enable the matching of SDNodeXForm by adding a definition that inherits from GICustomOperandRenderer and GISDNodeXFormEquiv as follows. def gi_imm8 : GICustomOperandRenderer<"renderImm8”>, GISDNodeXFormEquiv<imm8_xform>; Custom renderer functions should be of the form: void render(MachineInstrBuilder &MIB, const MachineInstr &I); Reviewers: dsanders, ab, rovka Reviewed By: dsanders Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet Differential Revision: https://reviews.llvm.org/D42012 llvm-svn: 322582
* [SLP] Fix for PR32164: Improve vectorization of reverse order of extract ↵Alexey Bataev2018-01-161-10/+17
| | | | | | | | | | | | | | operations. Summary: Sometimes vectorization of insertelement instructions with extractelement operands may produce an extra shuffle operation, if these operands are in the reverse order. Patch tries to improve this situation by the reordering of the operands to remove this extra shuffle operation. Reviewers: mkuper, hfinkel, RKSimon, spatel Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D33954 llvm-svn: 322579
* [X86][MMX] Accept UNDEF upper bits for MOVD GR32->MMXSimon Pilgrim2018-01-161-3/+4
| | | | llvm-svn: 322574
* [LiveDebugValues] recognize spilled reg killed in instruction after spillPetar Jovanovic2018-01-161-7/+30
| | | | | | | | | | | Current condition for spill instruction recognition in LiveDebugValues does not recognize case when register is spilled and killed in next instruction. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D41226 llvm-svn: 322554
* [X86][MMX] Improve MMX constant generationSimon Pilgrim2018-01-161-3/+12
| | | | | | Extend the MMX zero code to take any constant with zero'd upper 32-bits llvm-svn: 322553
* [DebugInfo] Unify dumping of address rangesJonas Devlieghere2018-01-164-12/+23
| | | | | | | | | | | | | | | Summary: This patch unifies the printing of address ranges as [0x0, 0x1). rdar://34822059 Reviewers: aprantl, dblaikie Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D42056 llvm-svn: 322543
* [CodeGen] Remove special case of printing subRegIdx from MachineInstr::printFrancis Visoiu Mistrih2018-01-161-3/+0
| | | | | | | Support in MachineOperand has been added in r320209. No need to special case this anymore. llvm-svn: 322542
* [CodeGen][NFC] Correct case for printSubRegIdxFrancis Visoiu Mistrih2018-01-163-3/+3
| | | | llvm-svn: 322541
* [BPF] Mark pseudo insn patterns as isCodeGenOnlyYonghong Song2018-01-161-2/+2
| | | | | | | | | | | | | | | | | | | | These pseudos are not supposed to be visible to user. This patch reduced the auto-generated instruction matcher. For example, the following words are removed from keyword list of LLVM BPF assembler. - MCK__35_, // '#' - MCK__COLON_, // ':' - MCK__63_, // '?' - MCK_ADJCALLSTACKDOWN, // 'ADJCALLSTACKDOWN' - MCK_ADJCALLSTACKUP, // 'ADJCALLSTACKUP' - MCK_PSEUDO, // 'PSEUDO' - MCK_Select, // 'Select' Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com> Acked-by: Yonghong Song <yhs@fb.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> llvm-svn: 322535
* [BPF] Teach DAG2DAG AND elimination about load intrinsicsYonghong Song2018-01-161-7/+31
| | | | | | | | | | | | | | | | | | As commented on the existing code: // The Reg operand should be a virtual register, which is defined // outside the current basic block. DAG combiner has done a pretty // good job in removing truncating inside a single basic block. However, when the Reg operand comes from bpf_load_[byte | half | word] intrinsics, the generic optimizer doesn't understand their results are zero extended, so these single basic block elimination opportunities were missed. Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com> Acked-by: Yonghong Song <yhs@fb.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> llvm-svn: 322534
* [SROA] fix assetion failureHiroshi Inoue2018-01-161-9/+4
| | | | | | | | | | | | | | This patch fixes the assertion failure in SROA reported in PR35657. PR35657 reports the assertion failure due to r319522 (splitting for non-whole-alloca slices), but this problem can happen even without r319522. The problem exists in a check for reusing an existing alloca when rewriting partitions. As the original comment said, we can reuse the existing alloca if the new alloca has the same type and offset with the existing one. But the code checks only type of the alloca and then check the offset using an assert. In a corner case with out-of-bounds access (e.g. @PR35657 function added in unit test), it is possible that the two allocas have the same type but different offsets. This patch makes the check of the offset in the if condition, and re-enables the splitting for non-whole-alloca slices. Differential Revision: https://reviews.llvm.org/D41981 llvm-svn: 322533
* [X86] Revisit the fix I made years ago to make 'xchgl %eax, %eax' not encode ↵Craig Topper2018-01-162-16/+8
| | | | | | | | | | using the 0x90 encoding in 64-bit mode. Prior to this we had a separate instruction and register class that excluded eax to prevent matching the instruction that would encode with 0x90. This patch changes this to just use an InstAlias to force xchgl %eax, %eax to use XCHG32rr instruction in 64-bit mode. This gets rid of the separate instruction and register class. llvm-svn: 322532
* [X86] Make 'xchgq %rax, %rax' an alias for the 0x90 nop encoding to match gas.Craig Topper2018-01-161-0/+4
| | | | | | Previously we encoded it as 0x48 0x90. llvm-svn: 322531
* Avoid Wparentheses warning.Simon Pilgrim2018-01-151-2/+2
| | | | llvm-svn: 322526
* [X86][MMX] Add support for MMX zero vector creationSimon Pilgrim2018-01-153-1/+26
| | | | | | | | | | As mentioned on PR35869, (and came up recently on D41517) we don't create a MMX zero register via the PXOR but instead perform a spill to stack from a XMM zero register. This patch adds support for direct MMX zero vector creation and should make it easier to add better constant vector creation in the future as well. Differential Revision: https://reviews.llvm.org/D41908 llvm-svn: 322525
* [X86][SSE] Add custom execution domain fixing for ↵Simon Pilgrim2018-01-152-3/+192
| | | | | | | | | | BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) Add support for custom execution domain fixing and implement support for BLENDPD/BLENDPS/PBLENDD/PBLENDW. Differential Revision: https://reviews.llvm.org/D42042 llvm-svn: 322524
* [X86] Use MVT::getVectorVT instead of EVT::getVectorVT when splitting ↵Craig Topper2018-01-151-2/+2
| | | | | | | | 256/512 bit build_vectors. NFC We must be creating a legal type here which means it can be an MVT. llvm-svn: 322512
* [X86] Generalize some code in LowerBUILD_VECTOR. NFCCraig Topper2018-01-151-4/+10
| | | | llvm-svn: 322511
* [X86] Remove unnecessary if statement from LowerBUILD_VECTOR. NFCICraig Topper2018-01-151-1/+1
| | | | | | We were checking for 128, 256, or 512 bit vectors, but those are the only types that can get here. llvm-svn: 322510
* [WebAssembly] Update README.txt.Dan Gohman2018-01-151-13/+41
| | | | | | | Describe more of the current status, mention Rust as another easy way to use this backend, and add more documentation links. llvm-svn: 322508
* [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32Stanislav Mekhanoshin2018-01-154-4/+19
| | | | | | Differential Revision: https://reviews.llvm.org/D41617 llvm-svn: 322500
* [Hexagon] Implement signed and unsigned multiply-high for vectorsKrzysztof Parzyszek2018-01-154-3/+166
| | | | llvm-svn: 322499
* [Hexagon] Rewrite LowerVECTOR_SHUFFLE for 32-/64-bit vectorsKrzysztof Parzyszek2018-01-151-38/+115
| | | | | | | The old implementation was not always correct. The new one recognizes more shuffles that match specific instructions. llvm-svn: 322498
* [AMDGPU] Copy impdefs from pseudo to real instructionsStanislav Mekhanoshin2018-01-154-0/+4
| | | | | | | | | | In some cases we do not copy implicit defs from pseudo to real VOP instructions. It has no visible impact at the moment thus no tests are affected or added. Differential Revision: https://reviews.llvm.org/D41783 llvm-svn: 322496
* [X86] Fix typos in WriteVMOVNTDQSt and WriteVMOVNTPYSt pattern names. NFCI.Simon Pilgrim2018-01-151-5/+5
| | | | llvm-svn: 322495
* [WebAssembly] Make WasmObjectWriter's destructor public; NFCDan Gohman2018-01-151-5/+2
| | | | | | This fixes the FIXME introduced in r315327. llvm-svn: 322490
* [SystemZ] Check for legality before doing LOAD AND TEST transformations.Jonas Paulsson2018-01-151-52/+79
| | | | | | | | | | Since a load and test instruction treat its operands as signed, it can only replace a logical compare for EQ/NE uses. Review: Ulrich Weigand https://bugs.llvm.org/show_bug.cgi?id=35662 llvm-svn: 322488
* [X86] Add missing predicates for VRNDSCALES{D,S}{m,r}Clement Courbet2018-01-151-1/+1
| | | | | | | | | | | | Summary: This is similar to https://reviews.llvm.org/D41983. Reviewers: gchatelet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42069 llvm-svn: 322486
* Update BTVER2 sched numbers for some AVX instructions (xmm version).Andrew V. Tischenko2018-01-151-3/+42
| | | | | | Differential Revision: https://reviews.llvm.org/D40067 llvm-svn: 322485
* [X86]Add missing predicates for VMOVDQUYrm,VMOVDQUYmr.Clement Courbet2018-01-151-6/+3
| | | | | | | | | | | | | | | Summary: Due to missing parentheses. This is similar to https://reviews.llvm.org/D41983. Reviewers: gchatelet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42062 llvm-svn: 322483
* [AArch64][AsmParser] Cleanup isSImm7s4, isSImm7s8, (etc) functions.Sander de Smalen2018-01-152-44/+22
| | | | | | | | | | | | Reviewers: fhahn, rengolin, t.p.northover, echristo, olista01, samparker Reviewed By: fhahn, samparker Subscribers: samparker, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D41899 llvm-svn: 322481
* [X86] Fix missing predicates HasAVX512 Predicates in avx512_sqrt_scalar.Clement Courbet2018-01-151-38/+39
| | | | | | | | | | | | | | Summary: For example, VSQRTSDZr and VSQRTSSZr were missing the predicate. Also fix braces indentation and braces for consistency. Reviewers: craig.topper, RKSimon Suscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41983 llvm-svn: 322478
* [Support] Remove MemoryBuffer::getNewMemBufferPavel Labath2018-01-151-5/+0
| | | | | | | all callers have been switched the the Writable version (which does not require const_casting to be useful). llvm-svn: 322475
* Revert "[DAG] Elide overlapping stores"Benjamin Kramer2018-01-151-20/+21
| | | | | | | This reverts commit r322085. Internal PPC testing is still showing the same symptoms as when this patch landed the last time. llvm-svn: 322474
* [LV] Don't call recordVectorLoopValueForInductionCast for newly-created IV ↵Andrei Elovikov2018-01-151-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | from a trunc. Summary: This method is supposed to be called for IVs that have casts in their use-def chains that are completely ignored after vectorization under PSE. However, for truncates of such IVs the same InductionDescriptor is used during creation/widening of both original IV based on PHINode and new IV based on TruncInst. This leads to unintended second call to recordVectorLoopValueForInductionCast with a VectorLoopVal set to the newly created IV for a trunc and causes an assert due to attempt to store new information for already existing entry in the map. This is wrong and should not be done. Fixes PR35773. Reviewers: dorit, Ayal, mssimpso Reviewed By: dorit Subscribers: RKSimon, dim, dcaballe, hsaito, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D41913 llvm-svn: 322473
* [GlobalsAA] Don't let dbg intrinsics affect analysis resultMikael Holmen2018-01-151-0/+4
| | | | | | | | | | | | | | | | | | Summary: This fixes PR35899. Debug info intrinsics shouldn't affect code generation so ignore them in GlobalsAA. Reviewers: hfinkel, aprantl Reviewed By: aprantl Subscribers: aprantl, llvm-commits Differential Revision: https://reviews.llvm.org/D41984 llvm-svn: 322470
* [NFC] Fix comment to adjust to realityMax Kazantsev2018-01-151-1/+1
| | | | llvm-svn: 322468
* [BasicAA] Stop crashing when dealing with pointers > 64 bits.Davide Italiano2018-01-151-0/+7
| | | | | | | | | | | | | | | An alternative (and probably better) fix would be that of making `Scale` an APInt, and there's a patch floating around to do this. As we're still discussing it, at least stop crashing in the meanwhile (added bonus, we now have a regression test for this situation). Fixes PR35843. Thanks to Eli for suggesting the fix and Simon for reporting and reducing the bug. llvm-svn: 322467
* [X86] Autoupgrade kunpck intrinsics using vector operations instead of ↵Craig Topper2018-01-141-5/+17
| | | | | | | | | | | | | | | | scalar operations Summary: This patch changes the kunpck intrinsic autoupgrade to use vXi1 shufflevector operations to perform vector extracts and concats. This more closely matches the definition of the kunpck instructions. Currently we rely on a DAG combine to turn the scalar shift/and/or code into a concat vectors operation. By doing it in the IR we get this for free. Reviewers: spatel, RKSimon, zvi, jina.nahias Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42018 llvm-svn: 322462
* [X86][SSE] Support combining MOVLHPS undef inputsSimon Pilgrim2018-01-141-0/+1
| | | | llvm-svn: 322459
* [InstSimplify] fix code comments; NFCSanjay Patel2018-01-141-8/+8
| | | | llvm-svn: 322456
* [X86] Use ISD::TRUNCATE instead of X86ISD::VTRUNC when input and output ↵Craig Topper2018-01-143-70/+72
| | | | | | types have the same number of elements. llvm-svn: 322455
* [X86] Add X86ISD::VTRUNC to computeKnownBitsForTargetNode.Craig Topper2018-01-141-0/+12
| | | | | | | | We have to take special care to avoid the cases where the result of the truncate would be padded with zero elements. Ideally we'd just use ISD::TRUNCATE for these cases instead. llvm-svn: 322454
* [X86] Improve legalization of vXi16/vXi8 selects.Craig Topper2018-01-142-5/+14
| | | | | | | | Extend vXi1 conditions of vXi8/vXi16 selects even before type legalization gets a chance to split wide vectors. Previously we would only extend 128 and 256 bit vectors. But if we start with a 512 bit vector or wider that needs to be split we wouldn't extend until after the split had taken place. By extending early we improve the results of type legalization. Don't widen condition of 128/256 bit vXi16/vXi8 selects when we have BWI but not VLX. We can still use a mask register by widening the select to 512-bits instead. This is similar to what we do for compares already. llvm-svn: 322450
* X86: Add pattern matching for PMADDWDZvi Rackover2018-01-131-0/+110
| | | | | | | | | | | | | | | In addition to the existing match as part of a loop-reduction, add a straightforward pattern match for DAG-contained patterns. Reviewers: RKSimon, craig.topper Subscribers: llvm-commits Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D41811 llvm-svn: 322446
OpenPOWER on IntegriCloud