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* Delete VirtRegRewriter.Jakob Stoklund Olesen2011-11-133-2666/+0
| | | | | | And there was much rejoicing. llvm-svn: 144480
* Switch PBQP to VRM's trivial rewriter.Jakob Stoklund Olesen2011-11-131-4/+1
| | | | | | The very complicated VirtRegRewriter is going away. llvm-svn: 144479
* Delete the old spilling framework from LiveIntervalAnalysis.Jakob Stoklund Olesen2011-11-121-1193/+0
| | | | | | This is dead code, all register allocators use InlineSpiller. llvm-svn: 144478
* Delete the 'standard' spiller with used the old spilling framework.Jakob Stoklund Olesen2011-11-121-45/+2
| | | | | | The current register allocators all use the inline spiller. llvm-svn: 144477
* Switch PBQP to the modern InlineSpiller framework.Jakob Stoklund Olesen2011-11-121-40/+11
| | | | | | | | | | | It is worth noting that the old spiller would split live ranges around basic blocks. The new spiller doesn't do that. PBQP should do its own live range splitting with SplitEditor::splitSingleBlock() if desired. See RAGreedy::tryBlockSplit(). llvm-svn: 144476
* Delete the linear scan register allocator.Jakob Stoklund Olesen2011-11-123-1549/+0
| | | | | | | | | RegAllocGreedy has been the default for six months now. Deleting RegAllocLinearScan makes it possible to also delete VirtRegRewriter and clean up the spiller code. llvm-svn: 144475
* Add more AVX2 shift lowering support. Move AVX2 variable shift to use ↵Craig Topper2011-11-122-62/+153
| | | | | | patterns instead of custom lowering code. llvm-svn: 144457
* Don't try to loop on iterators that are potentially invalidated inside the ↵Nick Lewycky2011-11-121-0/+18
| | | | | | loop. Fixes PR11361! llvm-svn: 144454
* Fix typo.Akira Hatanaka2011-11-121-1/+1
| | | | llvm-svn: 144453
* Implement Mips64's handling of byval arguments in LowerCall.Akira Hatanaka2011-11-121-12/+100
| | | | llvm-svn: 144452
* Fixed the MCJIT so that it can emit not only instanceSean Callanan2011-11-121-6/+6
| | | | | | | | | | | | | | methods but also class methods for Objective-C. Clang emits Objective-C method names with '\1' at the beginning, and the JIT has pre-existing logic to try prepending a '\1' when searching a module for an instance method (that is, a method whose name begins with '-'). I simply extended it to do the same thing when it encountered a class method (a method whose name begins with '+'). llvm-svn: 144451
* Implement Mips64's handling of byval arguments in LowerFormalArguments.Akira Hatanaka2011-11-121-18/+60
| | | | llvm-svn: 144449
* 64-bit arbitrary immediate pattern.Akira Hatanaka2011-11-121-0/+4
| | | | llvm-svn: 144448
* Function for handling byval arguments.Akira Hatanaka2011-11-122-4/+43
| | | | llvm-svn: 144447
* build: Attempt to rectify inconsistencies between CMake and LLVMBuild ↵Daniel Dunbar2011-11-1231-42/+31
| | | | | | | | versions of explicit dependencies. - The hope is that we have a tool/test to verify these are accurate (and tight) soon. llvm-svn: 144444
* Make sure scalarrepl picks the correct alloca when it rewrites a bitcast. ↵Eli Friedman2011-11-121-2/+10
| | | | | | Fixes PR11353. llvm-svn: 144442
* The dwarf standard says that the only differences between a out-of-lineRafael Espindola2011-11-121-0/+7
| | | | | | | | | | | | | | instance and a concrete inlined instance are the use of DW_TAG_subprogram instead of DW_TAG_inlined_subroutine and the who owns the tree. We were also omitting DW_AT_inline from the abstract roots. To fix this, make sure we mark abstract instance roots with DW_AT_inline even when we have only out-of-line instances referring to them with DW_AT_abstract_origin. FileCheck is not a very good tool for tests like this, maybe we should add a -verify mode to llvm-dwarfdump. llvm-svn: 144441
* ARM refactor simple immediate asm operand render methods.Jim Grosbach2011-11-124-79/+22
| | | | | | | These immediate operands all use the same simple logic for rendering to MCInst, so have them share the method for doing so. llvm-svn: 144439
* Don't try to form pre/post-indexed loads/stores until after LegalizeDAG ↵Eli Friedman2011-11-122-11/+11
| | | | | | runs. Fixes PR11029. llvm-svn: 144438
* Re-apply 144430, this time with the associated isel and disassmbler bits.Jim Grosbach2011-11-123-11/+6
| | | | | | Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.' llvm-svn: 144437
* Some cleanup and bulletproofing for node replacement in LegalizeDAG. To ↵Eli Friedman2011-11-111-57/+59
| | | | | | | | maintain LegalizeDAG invariants, whenever we a node is replaced, we must attempt to delete it, and if it still has uses after it is replaced (which can happen in rare cases due to CSE), we must revisit it. llvm-svn: 144432
* Oops. Missed the isel half of this. revert while I sort that out.Jim Grosbach2011-11-111-3/+4
| | | | llvm-svn: 144431
* ARM assembly parsing for VST1 two-register encoding.Jim Grosbach2011-11-111-4/+3
| | | | llvm-svn: 144430
* ARM optional size suffix for VLDR/VSTR syntax.Jim Grosbach2011-11-111-0/+9
| | | | llvm-svn: 144427
* Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.Chad Rosier2011-11-111-10/+60
| | | | llvm-svn: 144426
* CMake: Fix CMake build for new Mips tblgen file.Daniel Dunbar2011-11-111-0/+1
| | | | llvm-svn: 144423
* ARM vldm and vstm VFP instructions can take a data type suffix.Jim Grosbach2011-11-112-1/+23
| | | | | | | | | | | | It's ignored by the assembler when present, but is legal syntax. Other instructions have something similar, but for some mnemonics it's only sometimes not significant, so this quick check in the parser will need refactored into something more robust soon-ish. This gets some basics working in the meantime. Partial for rdar://10435264 llvm-svn: 144422
* LLVMBuild: Alphabetize required_libraries lists.Daniel Dunbar2011-11-112-2/+2
| | | | llvm-svn: 144416
* Target/LLVMBuild: Order components alphabetically.Daniel Dunbar2011-11-111-16/+16
| | | | llvm-svn: 144415
* Mips MC object code emission improvements:Bruno Cardoso Lopes2011-11-1113-130/+475
| | | | | | | | | | "With this patch we can now generate runnable Mips code through LLVM direct object emission. We have run numerous simple programs, both C and C++ and with -O0 and -O3 from the output. The code is not production ready, but quite useful for experimentation." Patch and message by Jack Carter llvm-svn: 144414
* Nuke no longer accurate comment.Jim Grosbach2011-11-111-3/+0
| | | | llvm-svn: 144411
* Preserve MachineMemOperands in ARMLoadStoreOptimizer.Andrew Trick2011-11-111-0/+22
| | | | | | Fixes PR8113. llvm-svn: 144409
* ARM allow Q registers in vldm/vstm register lists.Jim Grosbach2011-11-111-27/+45
| | | | | | rdar://9672822 llvm-svn: 144407
* Add a custom safepoint method, in order for language implementers to decide ↵Nicolas Geoffray2011-11-111-2/+15
| | | | | | which machine instruction gets to be a safepoint. llvm-svn: 144399
* Remove FIXME comment that should have been removed with r144351.Bob Wilson2011-11-111-1/+0
| | | | llvm-svn: 144392
* allow non-device function calls in PTX when natively handling device-side printfDan Bailey2011-11-114-23/+129
| | | | llvm-svn: 144388
* add rules in tabgen for PTX COPY_ADDRESS of frameindexDan Bailey2011-11-111-0/+6
| | | | llvm-svn: 144387
* Clients are responsible for initializing the targets, remove it from the ↵Benjamin Kramer2011-11-114-32/+1
| | | | | | | | | | disassembler API. This will break users of the LLVMCreateDisasm API (not that I know of any). They have to call the LLVMInitializeAll* functions from llvm-c/Target.h themselves now. edis' C API in all its horribleness should be unaffected. llvm-svn: 144385
* Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.Benjamin Kramer2011-11-111-1/+1
| | | | llvm-svn: 144384
* Remove the unnecessary dependency on libMBlazeCodeGen from ↵Benjamin Kramer2011-11-112-9/+2
| | | | | | libMBlazeDisassembler. llvm-svn: 144383
* Add lowering for AVX2 shift instructions.Craig Topper2011-11-112-117/+167
| | | | llvm-svn: 144380
* Rename variables to avoid confusion. No functionallity change intended.Chad Rosier2011-11-111-18/+18
| | | | llvm-svn: 144377
* Add support for using immediates with select instructions.Chad Rosier2011-11-111-8/+40
| | | | | | rdar://10412592 llvm-svn: 144376
* Do not try to detect DAG combine patterns for integer multiply-add/sub if valueAkira Hatanaka2011-11-111-2/+4
| | | | | | | type is not i32. MIPS does not have 64-bit integer multiply-add/sub instructions. llvm-svn: 144373
* 64-bit atomic instructions.Akira Hatanaka2011-11-113-64/+194
| | | | llvm-svn: 144372
* Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64.Akira Hatanaka2011-11-111-1/+2
| | | | llvm-svn: 144371
* Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.Akira Hatanaka2011-11-113-12/+27
| | | | llvm-svn: 144370
* 64-bit versions of jal, jalr and bal.Akira Hatanaka2011-11-112-0/+27
| | | | llvm-svn: 144368
* Emit Mips64's sequence of instructions that set global register in prologue.Akira Hatanaka2011-11-111-1/+21
| | | | llvm-svn: 144367
* Fix printing of MCSymbolRegExpr. Needs three closing parentheses forAkira Hatanaka2011-11-111-1/+4
| | | | | | VK_Mips_GPOFF_HI/LO. llvm-svn: 144366
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