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* Eliminate the use of PriorityQueue and just use a std::vector,Dan Gohman2010-05-262-8/+41
| | | | | | | | implementing pop with a linear search for a "best" element. The priority queue was a neat idea, but in practice the comparison functions depend on dynamic information. llvm-svn: 104718
* Delete an unused function.Dan Gohman2010-05-261-2/+0
| | | | llvm-svn: 104716
* MC: Change RelaxInstruction to only take the input and output instructions.Daniel Dunbar2010-05-262-8/+7
| | | | llvm-svn: 104713
* Fix a typo in a comment that Gabor noticed.Dan Gohman2010-05-261-3/+3
| | | | llvm-svn: 104711
* MC: Eliminate an unnecessary copy.Daniel Dunbar2010-05-261-9/+4
| | | | llvm-svn: 104709
* MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query itDaniel Dunbar2010-05-263-28/+12
| | | | | | before encoding. llvm-svn: 104707
* Remove dead code.Devang Patel2010-05-262-11/+1
| | | | llvm-svn: 104706
* Do not construct location list backword!Devang Patel2010-05-261-13/+17
| | | | llvm-svn: 104705
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-269-279/+87
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. llvm-svn: 104704
* MC: Eliminate MCAsmFixup, replace with MCFixup.Daniel Dunbar2010-05-264-28/+24
| | | | llvm-svn: 104699
* MC: Use accessors for access to MCAsmFixup.Daniel Dunbar2010-05-264-25/+30
| | | | llvm-svn: 104697
* MC: Change MCInst::dump_pretty to not include a trailing newline.Daniel Dunbar2010-05-263-3/+6
| | | | llvm-svn: 104696
* Kill unneeded SExt.Benjamin Kramer2010-05-261-1/+1
| | | | llvm-svn: 104692
* SRetReturnReg was set in LowerFormalArguments(). So only assert it here.Zhongxing Xu2010-05-261-4/+2
| | | | llvm-svn: 104691
* MC: Eliminate MCFragment vtable, which was unnecessary.Daniel Dunbar2010-05-261-69/+62
| | | | llvm-svn: 104689
* Coding style change (Adding 1 missing space.)Shih-wei Liao2010-05-261-1/+1
| | | | llvm-svn: 104670
* Adding the missing implementation for ARM::SBFX and ARM::UBFX.Shih-wei Liao2010-05-261-1/+13
| | | | | | Fixing http://llvm.org/bugs/show_bug.cgi?id=7225. llvm-svn: 104667
* Temporarily revert r104655 as it's breaking the bots.Eric Christopher2010-05-262-39/+37
| | | | llvm-svn: 104664
* fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.Jim Grosbach2010-05-262-3/+3
| | | | llvm-svn: 104661
* Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen2010-05-269-87/+279
| | | | | | This reverts commit 104654. llvm-svn: 104660
* Change push_all to a non-virtual function and implement it in theDan Gohman2010-05-262-6/+1
| | | | | | base class, since all the implementations are the same. llvm-svn: 104659
* Trim #include.Dan Gohman2010-05-261-1/+0
| | | | llvm-svn: 104657
* Dale and Evan suggested putting the "check for setjmp" much earlier in theBill Wendling2010-05-262-37/+39
| | | | | | machine code generation. That's a good idea, so I made it so. llvm-svn: 104655
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-269-279/+87
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. llvm-svn: 104654
* Adding the missing implementation of Bitfield's "clear" and "insert".Shih-wei Liao2010-05-261-4/+9
| | | | | | Fixing http://llvm.org/bugs/show_bug.cgi?id=7222. llvm-svn: 104653
* To handle s* registers in emitVFPLoadStoreMultipleInstruction().Shih-wei Liao2010-05-261-7/+12
| | | | | | Fixing http://llvm.org/bugs/show_bug.cgi?id=7221. llvm-svn: 104652
* Start adding mach-o tls reloc support.Eric Christopher2010-05-262-2/+10
| | | | llvm-svn: 104651
* Drop the SuperregHashTable. It is essentially the same as SubregHashTable.Jakob Stoklund Olesen2010-05-251-2/+0
| | | | llvm-svn: 104650
* First cut at supporting .debug_loc section. Devang Patel2010-05-253-87/+253
| | | | | | This is used to track variable information. llvm-svn: 104649
* Properly promote operands when optimizing a single-character memcmp.Benjamin Kramer2010-05-251-3/+6
| | | | llvm-svn: 104648
* Constify function.Bill Wendling2010-05-251-2/+2
| | | | llvm-svn: 104646
* Do one map lookup instead of two.Dan Gohman2010-05-251-2/+3
| | | | llvm-svn: 104645
* Fix a missing newline in debug output.Dan Gohman2010-05-251-1/+1
| | | | llvm-svn: 104644
* Move the verbose asm output up a bit so it can be used in the special casesEric Christopher2010-05-251-5/+6
| | | | | | as well. llvm-svn: 104642
* Okay, bear with me here...Bill Wendling2010-05-251-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If you have a setjmp/longjmp situation, it's possible for stack slot coloring to reuse a stack slot before it's really dead. For instance, if we have something like this: 1: y = g; x = sigsetjmp(env, 0); switch (x) { case 1: /* ... */ goto run; case 0: run: do_run(); /* marked as "no return" */ break; case 3: if (...) { /* ... */ goto run; } /* ... */ break; } 2: g = y; "y" may be put onto the stack, so the expression "g = y" is relying upon the fact that the stack slot containing "y" isn't modified between (1) and (2). But it can be, because of the "no return" calls in there. A longjmp might come back with 3, modify the stack slot, and then go to case 0. And it's perfectly acceptable to reuse the stack slot there because there's no CFG flow from case 3 to (2). The fix is to disable certain optimizations in these situations. Ideally, we'd disable them for all "returns twice" functions. But we don't support that attribute. Check for "setjmp" and "sigsetjmp" instead. llvm-svn: 104640
* Add support for initialized global data for darwin tls. Update commentsEric Christopher2010-05-252-7/+19
| | | | | | and testcases accordingly. llvm-svn: 104635
* Changed the encoding of X86 floating point stack operations where both operandsKevin Enderby2010-05-251-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | are st(0). These can be encoded using an opcode for storing in st(0) or using an opcode for storing in st(i), where i can also be 0. To allow testing with the darwin assembler and get a matching binary the opcode for storing in st(0) is now used. To do this the same logical trick is use from the darwin assembler in converting things like this: fmul %st(0), %st into this: fmul %st(0) by looking for the second operand being X86::ST0 for specific floating point mnemonics then removing the second X86::ST0 operand. This also has the add benefit to allow things like: fmul %st(1), %st that llvm-mc did not assemble. llvm-svn: 104634
* Separate unrelated cases that once shared a numeric valueJakob Stoklund Olesen2010-05-251-9/+12
| | | | llvm-svn: 104629
* Print symbolic SubRegIndex names on machine operands.Jakob Stoklund Olesen2010-05-252-3/+9
| | | | llvm-svn: 104628
* Remove NumberHack entirely.Jakob Stoklund Olesen2010-05-257-47/+44
| | | | | | | SubRegIndex instances are now numbered uniquely the same way Register instances are - in lexicographical order by name. llvm-svn: 104627
* MC/X86: Add a hack to allow recognizing 'cmpltps' and friends.Daniel Dunbar2010-05-251-1/+36
| | | | llvm-svn: 104626
* Fix another variant of PR 7191. Also add a testcaseDale Johannesen2010-05-251-1/+5
| | | | | | | | Mon Ping provided; unfortunately bugpoint failed to reduce it, but I think it's important to have a test for this in the suite. 8023512. llvm-svn: 104624
* MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}.Daniel Dunbar2010-05-251-0/+42
| | | | llvm-svn: 104622
* The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is requiredKevin Enderby2010-05-251-1/+2
| | | | | | for the 64-bit version of the Bit Test instruction. llvm-svn: 104621
* Fix PR 7191. I have been unable to create a .ll file that fails, sorry.Dale Johannesen2010-05-251-2/+10
| | | | | | | (oye, a word which should be better known to people writing tree traversals, means grandchild.) llvm-svn: 104619
* Make sure aeskeygenassist uses an unsigned immediate field.Eric Christopher2010-05-251-33/+32
| | | | | | Fixes rdar://8017638 llvm-svn: 104617
* Ignore NumberHack and give each SubRegIndex instance a unique enum value ↵Jakob Stoklund Olesen2010-05-251-3/+3
| | | | | | | | | | | instead. This passes lit tests, but I'll give it a go through the buildbots to smoke out any remaining places that depend on the old SubRegIndex numbering. Then I'll remove NumberHack entirely. llvm-svn: 104615
* Use enums instead of literals for SystemZ subregistersJakob Stoklund Olesen2010-05-251-11/+11
| | | | llvm-svn: 104612
* Use enums instead of literals for X86 subregisters.Jakob Stoklund Olesen2010-05-252-11/+10
| | | | | | | The cases in getMatchingSuperRegClass cannot be broken up until the enums have unique values. llvm-svn: 104611
* Add missing implementation to the materialization of VFP misc. instructions ↵Zonr Chang2010-05-251-0/+43
| | | | | | (vmrs, vmsr and vmov (immediate)) llvm-svn: 104588
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