| Commit message (Collapse) | Author | Age | Files | Lines |
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Other bug fixes.
llvm-svn: 37623
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llvm-svn: 37622
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llvm-svn: 37621
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llvm-svn: 37620
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define double @test2(i64 %A) {
%B = bitcast i64 %A to double
ret double %B
}
$ llvm-as < t.ll | llc -march=x86-64
before:
.align 4
.globl _test2
_test2:
movd %rdi, %xmm0
ret
after:
_test2:
subq $8, %rsp
movq %rdi, (%rsp)
movsd (%rsp), %xmm0
addq $8, %rsp
ret
llvm-svn: 37617
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1. Consider all possible ifcvt cases at once. No longer restricted to bottom
up iterative approach.
2. Sort all possible cases based on a cost function. Perform the most profitable
ones first invalidate others that target the same blocks.
3. Fixed a number of bugs related to block duplication.
llvm-svn: 37613
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llvm-svn: 37611
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instructions that depend on invokes.
llvm-svn: 37610
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llvm-svn: 37608
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llvm-svn: 37607
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during ifcvt.
llvm-svn: 37606
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llvm-svn: 37602
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for tied register constraints.
llvm-svn: 37601
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llvm-svn: 37599
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llvm-svn: 37597
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integer constant SCEV.
llvm-svn: 37596
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llvm-svn: 37595
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llvm-svn: 37593
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This created an ambiguity for expandInTy to decide when to use
sign-extension or zero-extension, but it turns out that most of its callers
don't actually need a type conversion, now that LLVM types don't have
explicit signedness. Drop expandInTy in favor of plain expand, and change
the few places that actually need a type conversion to do it themselves.
llvm-svn: 37591
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llvm-svn: 37590
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integer ops. This implements Transforms/InstCombine/and-or-not.ll
test3/test4, and finishes off PR1510
llvm-svn: 37589
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AND vectors.
llvm-svn: 37586
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llvm-svn: 37585
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1. ~(~X | Y) === (X & ~Y)
2. (A|B) & ~(A&B) -> A^B
This allows us to transform ~(~(a|b) | (a&b)) -> a^b.
This implements PR1510 for scalar values.
llvm-svn: 37584
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operations from Duraids example.
llvm-svn: 37582
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llvm-svn: 37581
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it. It needs to be re-analyzed.
llvm-svn: 37580
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llvm-svn: 37579
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llvm-svn: 37578
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llvm-svn: 37577
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and an
implementation for x86.
llvm-svn: 37576
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llvm-svn: 37575
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llvm-svn: 37574
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class basis.
llvm-svn: 37572
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llvm-svn: 37571
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turned on. Likewise for scanning of invokes to mark landing pads.
llvm-svn: 37570
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VCONCAT_VECTORS. Use these for CopyToReg and CopyFromReg legalizing in
the case that the full register is to be split into subvectors instead
of scalars. This replaces uses of VBIT_CONVERT to present values as
vector-of-vector types in order to make whole subvectors accessible via
BUILD_VECTOR and EXTRACT_VECTOR_ELT.
This is in preparation for adding extended ValueType values, where
having vector-of-vector types is undesirable.
llvm-svn: 37569
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correct types for the result vector, even though it is currently bitcasted
to a different type immediately.
llvm-svn: 37568
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crashing but breaks exception handling. The problem
described in PR1224 is that invoke is a terminator that
can produce a value. The value may be needed in other
blocks. The code that writes to registers values needed
in other blocks runs before terminators are lowered (in
this case invoke) so asserted because the value was not
yet available. The fix that was applied was to do invoke
lowering earlier, before writing values to registers.
The problem this causes is that the code to copy values
to registers can be output after the invoke call. If
an exception is raised and control is passed to the
landing pad then this copy-code will never execute. If
the value is needed in some code path reached via the
landing pad then that code will get something bogus.
So revert the original fix and simply skip invoke values
in the general copying to registers code. Instead copy
the invoke value to a register in the invoke lowering code.
llvm-svn: 37567
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llvm-svn: 37566
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llvm-svn: 37565
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llvm-svn: 37564
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llvm-svn: 37562
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llvm-svn: 37561
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common dominator.
llvm-svn: 37559
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being more careful when using
post-dominator information.
llvm-svn: 37556
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llvm-svn: 37554
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Remove unused PostETForest.
llvm-svn: 37551
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rather than topological order. This
fixes a testcase extracted from llvm-test.
llvm-svn: 37550
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llvm-svn: 37548
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