summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* Small cleanups.Michael Gottesman2013-04-031-14/+14
| | | | | | | | Cleaned up trailing whitespace and added extra slashes in front of a function level comment so that it follow the convention of having 3 slashes. llvm-svn: 178712
* Refactored out a part of ObjCARCOpt::OptimizeReturns into its own method ↵Michael Gottesman2013-04-031-22/+33
| | | | | | HasSafePathToPredecessorCall. llvm-svn: 178710
* Removed an old comment.Michael Gottesman2013-04-031-7/+0
| | | | llvm-svn: 178709
* Clean up arc annotations by moving the top/bottom BB annotations into ↵Michael Gottesman2013-04-031-58/+46
| | | | | | | | conditional macros that no-op in Release mode instead of #ifdef sections of the code. This is to follow the example of the DEBUG macro. llvm-svn: 178705
* X86 cost model: Vector shifts are expensive in most casesArnold Schwaighofer2013-04-031-0/+42
| | | | | | | | | | | | | | The default logic does not correctly identify costs of casts because they are marked as custom on x86. For some cases, where the shift amount is a scalar we would be able to generate better code. Unfortunately, when this is the case the value (the splat) will get hoisted out of the loop, thereby making it invisible to ISel. radar://13130673 radar://13537826 llvm-svn: 178703
* R600: Fix last ALU of a clause being emitted in a separate clauseVincent Lejeune2013-04-031-2/+2
| | | | llvm-svn: 178675
* Ensuring that both bits are set, and not just a combination of one or the other.Aaron Ballman2013-04-031-1/+2
| | | | llvm-svn: 178674
* Cleanup PPC reciprocal-estimate functionalityHal Finkel2013-04-032-61/+47
| | | | | | | Incorporating review feedback from Bill Schmidt on r178617. No functionality change intended. llvm-svn: 178672
* R600: Factorize maximum alu per clause in a single locationVincent Lejeune2013-04-034-2/+6
| | | | llvm-svn: 178667
* Testing for Visual Studio 2010 SP1 or greater before calling the _xgetbv ↵Aaron Ballman2013-04-031-2/+2
| | | | | | intrinsic. This also fixes a minor code formatting issue. llvm-svn: 178666
* R600: Simplify data structure and add DEBUG to R600ControlFlowFinalizerVincent Lejeune2013-04-031-20/+21
| | | | llvm-svn: 178665
* R600: Consider KILLGT as an ALU instructionVincent Lejeune2013-04-032-3/+4
| | | | | | | Mesa does not override llvm behavior wrt KILLGT anymore so llvm has to handle KILLGT on its own. llvm-svn: 178664
* Measure time that IR parsing took as part of the -time-passes measurement.Eli Bendersky2013-04-032-4/+13
| | | | llvm-svn: 178662
* PPC: Enable FRES and FRSQRTE on the default PPC64 descriptionHal Finkel2013-04-031-1/+2
| | | | | | | I discussed this with Bill Schmidt on IRC, and it was decided that this is a safe and reasonable default. llvm-svn: 178659
* PPC: Add a FIXME regarding the non-working fma+fneg Altivec patternHal Finkel2013-04-031-0/+2
| | | | llvm-svn: 178658
* Remove some obsolete PowerPC/README entriesHal Finkel2013-04-031-20/+0
| | | | llvm-svn: 178657
* More direct types in PowerPC AltiVec intrinsics.Ulrich Weigand2013-04-031-47/+29
| | | | | | | | | | This patch follows up on work done by Bill Schmidt in r178277, and replaces most of the remaining uses of VRRC in ISEL DAG patterns. The resulting .inc files are identical except for comments, so no change in code generation is expected. llvm-svn: 178656
* Fix PR15632: No support for ppcf128 floating-point remainder on PowerPC.Bill Schmidt2013-04-033-0/+13
| | | | | | | | For this we need to use a libcall. Previously LLVM didn't implement libcall support for frem, so I've added it in the usual straightforward manner. A test case from the bug report is included. llvm-svn: 178639
* AArch64: implement ETMv4 trace system registers.Tim Northover2013-04-032-0/+432
| | | | llvm-svn: 178637
* Second pass at addressing PR15351 by explicitly checking for AVX supportAaron Ballman2013-04-031-2/+25
| | | | | | when getting the host processor information. It emits a .byte sequence on GNUC compilers to work around lack of xgetbv support with older assemblers, and resolves a comment typo found in the previous patch. llvm-svn: 178636
* Fix SRet for thiscall in i686-pc-win32Timur Iskhodzhanov2013-04-031-2/+2
| | | | llvm-svn: 178634
* AArch64: switch patterns to be type-based rather than RegClass-basedTim Northover2013-04-031-503/+492
| | | | | | | It's a bit of churn in the blame log, but I think there are real benefits to the newer system so I'm making the change in one go. llvm-svn: 178633
* Fix grammar.Eric Christopher2013-04-031-1/+1
| | | | llvm-svn: 178624
* Remove ZeroOrMore from the option description. We don't need it here.Eric Christopher2013-04-031-1/+1
| | | | llvm-svn: 178623
* Add 64-bit compare + branch for SPARC v9.Jakob Stoklund Olesen2013-04-035-5/+34
| | | | | | | | | | The same compare instruction is used for 32-bit and 64-bit compares. It sets two different sets of flags: icc and xcc. This patch adds a conditional branch instruction using the xcc flags for 64-bit compares. llvm-svn: 178621
* Remove some unsupported-feature comments from PPC.tdHal Finkel2013-04-031-3/+0
| | | | | | These refer to the reciprocal estimate support recently committed. llvm-svn: 178618
* Use PPC reciprocal estimates with Newton iteration in fast-math modeHal Finkel2013-04-037-30/+321
| | | | | | | | | | | | | | | | | | | When unsafe FP math operations are enabled, we can use the fre[s] and frsqrte[s] instructions, which generate reciprocal (sqrt) estimates, together with some Newton iteration, in order to quickly generate floating-point division and sqrt results. All of these instructions are separately optional, and so each has its own feature flag (except for the Altivec instructions, which are covered under the existing Altivec flag). Doing this is not only faster than using the IEEE-compliant fdiv/fsqrt instructions, but allows these computations to be pipelined with other computations in order to hide their overall latency. I've also added a couple of missing fnmsub patterns which turned out to be missing (but are necessary for good code generation of the Newton iterations). Altivec needs a similar fix, but that will probably be more complicated because fneg is expanded for Altivec's v4f32. llvm-svn: 178617
* Fix the fde encoding used by mips to match gas.Rafael Espindola2013-04-031-4/+7
| | | | | | | | | | | | | This finally fixes the encoding. The patch also * Removes eh-frame.ll. It was an unnecessary .ll to .o test that was checking the wrong value. * Merge fde-reloc.s and eh-frame.s into a single test, since the only difference was the run lines. * Don't blindly test the content of the entire .eh_frame section. It makes it hard to anyone actually fixing a bug and hitting a difference in a binary blob. Instead, use a CHECK for each field and document what is being checked. llvm-svn: 178615
* Rolling back the AVX support patch due to breaking a gcc 4.6 build bot that ↵Aaron Ballman2013-04-031-23/+2
| | | | | | doesn't understand the xgetbv instruction for some reason. Will revisit when time permits. llvm-svn: 178614
* Remove an optimization where we were changing an objc_autorelease into an ↵Michael Gottesman2013-04-031-16/+1
| | | | | | | | | | | | | | | | | | | | | objc_autoreleaseReturnValue. The semantics of ARC implies that a pointer passed into an objc_autorelease must live until some point (potentially down the stack) where an autorelease pool is popped. On the other hand, an objc_autoreleaseReturnValue just signifies that the object must live until the end of the given function at least. Thus objc_autorelease is stronger than objc_autoreleaseReturnValue in terms of the semantics of ARC* implying that performing the given strength reduction without any knowledge of how this relates to the autorelease pool pop that is further up the stack violates the semantics of ARC. *Even though objc_autoreleaseReturnValue if you know that no RV optimization will occur is more computationally expensive. llvm-svn: 178612
* Improved comment. No functionality change.Michael Gottesman2013-04-031-1/+2
| | | | llvm-svn: 178605
* Attempting to fix the build on older GCC versions.Aaron Ballman2013-04-031-1/+2
| | | | llvm-svn: 178604
* This patch addresses PR15351 by explicitly checking for AVX supportAaron Ballman2013-04-031-2/+22
| | | | | | when getting the host processor information. llvm-svn: 178598
* Formatting.Eric Christopher2013-04-021-2/+1
| | | | llvm-svn: 178589
* [mips] Small update to the implementation of eh.return for Mips.Akira Hatanaka2013-04-021-0/+4
| | | | | | | | | | This patch initializes t9 to the handler address, but only if the relocation model is pic. This handles the case where handler to which eh.return jumps points to the start of the function. Patch by Sasa Stankovic. llvm-svn: 178588
* Support and test template arguments for unions.Eric Christopher2013-04-021-1/+2
| | | | llvm-svn: 178586
* Reformat arguments.Eric Christopher2013-04-021-4/+6
| | | | llvm-svn: 178585
* [mips] Expand pseudo multiply/divide instructions in MipsCodeEmitter.cpp.Akira Hatanaka2013-04-021-0/+36
| | | | | | | | | | This patch fixes the following two tests which have been failing on llvm-mips-linux builder since r178403: LLVM :: Analysis/Profiling/load-branch-weights-ifs.ll LLVM :: Analysis/Profiling/load-branch-weights-loops.ll llvm-svn: 178584
* Allow MachineTraceMetrics to be used when the model has no resources.Jakob Stoklund Olesen2013-04-022-7/+11
| | | | | | | It it still possible to extract information from itineraries, for example. llvm-svn: 178582
* [ms-inline asm] Add support for parsing variables with namespace aliasChad Rosier2013-04-021-0/+54
| | | | | | | | | | | | | qualifiers. This patch only adds support for parsing these identifiers in the X86AsmParser. The front-end interface isn't capable of looking up these identifiers at this point in time. The end result is the compiler now errors during object file emission, rather than at parse time. Test case coming shortly. Part of rdar://13499009 and PR13340 llvm-svn: 178566
* Fix PR15630: Replace faulty stdcx. with stwcx.Bill Schmidt2013-04-021-1/+1
| | | | | | | | | | When doing a partword atomic operation, a lwarx was being paired with a stdcx. instead of a stwcx. when compiling for a 64-bit target. The target has nothing to do with it in this case; we always need a stwcx. Thanks to Kai Nacke for reporting the problem. llvm-svn: 178559
* Don't attempt MTM heuristics without a scheduling model present.Jakob Stoklund Olesen2013-04-021-0/+4
| | | | | | This should fix the PPC buildbots. llvm-svn: 178558
* Count processor resources individually in MachineTraceMetrics.Jakob Stoklund Olesen2013-04-021-9/+144
| | | | | | | | | | | | | | | The new instruction scheduling models provide information about the number of cycles consumed on each processor resource. This makes it possible to estimate ILP more accurately than simply counting instructions / issue width. The functions getResourceDepth() and getResourceLength() now identify the limiting processor resource, and return a cycle count based on that. This gives more precise resource information, particularly in traces that use one resource a lot more than others. llvm-svn: 178553
* [fast-isel] Use the correct API to disable FastLowerArguments for Win64.Chad Rosier2013-04-021-1/+1
| | | | llvm-svn: 178549
* DAGCombiner: Merge store/loads when we have extload/truncstoresArnold Schwaighofer2013-04-021-0/+19
| | | | | | | | | | | | | | | | This is helps on architectures where i8,i16 are not legal but we have byte, and short loads/stores. Allowing us to merge copies like the one below on ARM. copy(char *a, char *b, int n) { do { int t0 = a[0]; int t1 = a[1]; b[0] = t0; b[1] = t1; radar://13536387 llvm-svn: 178546
* [NVPTX] Fix a few style issues in NVVMReflectJustin Holewinski2013-04-021-72/+56
| | | | llvm-svn: 178536
* Use a worklist to avoid a sneaky iterator invalidation.Bill Wendling2013-04-021-3/+3
| | | | | | | | | | | | | The iterator could be invalidated when it's recursively deleting a whole bunch of constant expressions in a constant initializer. Note: This was only reproducible if `opt' was run on a `.bc' file. If `opt' was run on a `.ll' file, it wouldn't crash. This is why the test first pushes the `.ll' file through `llvm-as' before feeding it to `opt'. PR15440 llvm-svn: 178531
* Add 64-bit load and store instructions.Jakob Stoklund Olesen2013-04-021-0/+68
| | | | | | There is only a few new instructions, the rest is handled with patterns. llvm-svn: 178528
* Basic 64-bit ALU operations.Jakob Stoklund Olesen2013-04-021-0/+38
| | | | | | | SPARC v9 extends all ALU instructions to 64 bits, so we simply need to add patterns to use them for both i32 and i64 values. llvm-svn: 178527
* Materialize 64-bit immediates.Jakob Stoklund Olesen2013-04-021-0/+88
| | | | | | | The last resort pattern produces 6 instructions, and there are still opportunities for materializing some immediates in fewer instructions. llvm-svn: 178526
OpenPOWER on IntegriCloud