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* [MC] Remove an unused (and broken) variant of the setupForSymbolicDisassemblyLang Hames2014-03-301-8/+0
| | | | | | method in MCDisassembler. llvm-svn: 205123
* Add a missing break.Rafael Espindola2014-03-301-0/+1
| | | | | | | | | | Patch by Tobias Güntner. I tried to write a test, but the only difference is the Changed value that gets returned. It can be tested with "opt -debug-pass=Executions -functionattrs, but that doesn't seem worth it. llvm-svn: 205121
* Support: normalize the default triple on UnixSaleem Abdulrasool2014-03-301-1/+1
| | | | | | | | | | This will fix cross-compiling buildbots (e.g. cygwin). This is in the same vein as SVN r205070. Apply this to fix the cross-compiling scenario, even though the preferred solution is to update the build system to normalize the embedded triple rather than perform this at runtime every time. This is meant to tide us over until that approach is fleshed out and applied. llvm-svn: 205120
* Fix a few -Wdocumentation warningsDmitri Gribenko2014-03-294-13/+13
| | | | llvm-svn: 205116
* Detemplatize LOHDirective.Benjamin Kramer2014-03-293-25/+25
| | | | | | | | | | | The ARM64 backend uses it only as a container to keep an MCLOHType and Arguments around so give it its own little copy. The other functionality isn't used and we had a crazy method specialization hack in place to keep it working. Unfortunately that was incompatible with MSVC. Also range-ify a couple of loops while at it. llvm-svn: 205114
* ARM64: Remove unused helper function, make others static.Benjamin Kramer2014-03-293-45/+6
| | | | llvm-svn: 205112
* tblgen: Twinify PrintFatalError.Benjamin Kramer2014-03-292-22/+22
| | | | | | No functionality change. llvm-svn: 205110
* Avoid storing Twines.Benjamin Kramer2014-03-291-22/+19
| | | | | | While there nested ifs into a helper function. No functionality change. llvm-svn: 205108
* [PowerPC] Handle v2i64 comparisonsHal Finkel2014-03-291-0/+23
| | | | | | | | v2i64 is a legal type under VSX, however we don't have native vector comparisons. We can handle eq/ne by casting it to an Altivec type, but everything else must be expanded. llvm-svn: 205106
* ARM64: format register strings without creating a local Twine.Tim Northover2014-03-291-5/+5
| | | | | | It was causing horrible failures on some build-bots. llvm-svn: 205105
* [PowerPC] VSX instruction latency correctionsHal Finkel2014-03-292-15/+15
| | | | | | | | The vector divide and sqrt instructions have high latencies, and the scalar comparisons are like all of the others. On the P7, permutations take an extra cycle over purely-simple vector ops. llvm-svn: 205096
* Recommitted fix for PR18931, with extended tests set.Stepan Dyatkovskiy2014-03-292-2/+20
| | | | | | | | | | | | | Issue subject: Crash using integrated assembler with immediate arithmetic Fix description: Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage, since it is impossible to resolve labels on this stage. In the end of stage we still have expression (MCExpr). Then, when we want to encode it, we expect it to be an immediate, but it still an expression. Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage. llvm-svn: 205094
* ARM64: use 64-bit constant even on 32-bit machinesTim Northover2014-03-291-1/+1
| | | | | | Another existing bot failure so no tests. llvm-svn: 205093
* ARM64: change format specifier to work on 32-bit targetsTim Northover2014-03-291-1/+1
| | | | | | Existing tests were failing. llvm-svn: 205092
* [ARM64] Fix 'assert("...")' to be 'assert(0 && "...")'. Otherwise, it isChandler Carruth2014-03-293-3/+3
| | | | | | | | | | | no assert at all. ;] Some of these should probably be switched to llvm_unreachable, but I didn't want to perturb the behavior in this patch. Found by -Wstring-conversion, which I'll try to turn on in CMake builds at least as it is finding useful things. llvm-svn: 205091
* ARM64: initial backend importTim Northover2014-03-2995-14/+58771
| | | | | | | | | | | | This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
* CodeGen: add sensible defaults for the ISD::FROUND operationTim Northover2014-03-291-0/+9
| | | | | | Some exotic types didn't know how to handle FROUND, which ARM64 uses. llvm-svn: 205088
* MC-exceptions: add support for compact-unwind without .eh_frameTim Northover2014-03-292-3/+22
| | | | | | | | | | | | ARM64 has compact-unwind information, but doesn't necessarily want to emit .eh_frame directives as well. This teaches MC about such a situation so that it will skip .eh_frame info when compact unwind has been successfully produced. For functions incompatible with compact unwind, the normal information is still written. llvm-svn: 205087
* CodeGenPrep: wrangle IR to exploit AArch64 tbz/tbnz inst.Tim Northover2014-03-292-0/+81
| | | | | | | | | | | | | | | | Given IR like: %bit = and %val, #imm-with-1-bit-set %tst = icmp %bit, 0 br i1 %tst, label %true, label %false some targets can emit just a single instruction (tbz/tbnz in the AArch64 case). However, with ISel acting at the basic-block level, all three instructions need to be together for this to be possible. This adds another transformation to CodeGenPrep to expose these opportunities, if targets opt in via the hook. llvm-svn: 205086
* MC: add a RefKind field to MCValueTim Northover2014-03-291-0/+5
| | | | | | | | This is principally to allow neater mapping of fixups to relocations in ARM64 ELF. Without this, there isn't enough information available to GetRelocType, leading to many more fixup_arm64_... enumerators. llvm-svn: 205085
* MachO: Add linker-optimisation hint framework to MC.Tim Northover2014-03-296-2/+86
| | | | | | | | Another part of the ARM64 backend (so tests will be following soon). This is currently used by the linker to relax adrp/ldr pairs into nops where possible, though could well be more broadly applicable. llvm-svn: 205084
* MachO: actually set linker-private prefix at MC level.Tim Northover2014-03-291-0/+1
| | | | | | This was accidentally omitted from r205081. llvm-svn: 205083
* MachO: allow each section to have a linker-private symbolTim Northover2014-03-293-4/+41
| | | | | | | | | The upcoming ARM64 backend doesn't have section-relative relocations, so we give each section its own symbol to provide this functionality. Of course, it doesn't need to appear in the final executable, so linker-private is the best kind for this purpose. llvm-svn: 205081
* Intrinsics: add LLVMHalfElementsVectorType constraintTim Northover2014-03-292-1/+17
| | | | | | | | | | This is like the LLVMMatchType, except the verifier checks that the second argument is a vector with the same base type and half the number of elements. This will be used by the ARM64 backend. llvm-svn: 205079
* Completely rewrite ELFObjectWriter::RecordRelocation.Rafael Espindola2014-03-2923-637/+308
| | | | | | | | | | | | | | | | | | | I started trying to fix a small issue, but this code has seen a small fix too many. The old code was fairly convoluted. Some of the issues it had: * It failed to check if a symbol difference was in the some section when converting a relocation to pcrel. * It failed to check if the relocation was already pcrel. * The pcrel value computation was wrong in some cases (relocation-pc.s) * It was missing quiet a few cases where it should not convert symbol relocations to section relocations, leaving the backends to patch it up. * It would not propagate the fact that it had changed a relocation to pcrel, requiring a quiet nasty work around in ARM. * It was missing comments. llvm-svn: 205076
* [PowerPC] Add subregister classes for f64 VSX valuesHal Finkel2014-03-298-59/+192
| | | | | | | | | | | | | We had stored both f64 values and v2f64, etc. values in the VSX registers. This worked, but was suboptimal because we would always spill 16-byte values even through we almost always had scalar 8-byte values. This resulted in an increase in stack-size use, extra memory bandwidth, etc. To fix this, I've added 64-bit subregisters of the Altivec registers, and combined those with the existing scalar floating-point registers to form a class of VSX scalar floating-point registers. The ABI code has also been enhanced to use this register class and some other necessary improvements have been made. llvm-svn: 205075
* Windows: canonicalise the default windows tripleSaleem Abdulrasool2014-03-291-1/+1
| | | | | | | Canonicalise the default triple that is used on Windows. This should hopefully fix the MSVC buildbots. llvm-svn: 205070
* [x86] Fix printing of register operands with q modifier.Akira Hatanaka2014-03-281-3/+5
| | | | | | | | | Emit 32-bit register names instead of 64-bit register names if the target does not have 64-bit general purpose registers. <rdar://problem/14653996> llvm-svn: 205067
* Debug Compression: Avoid compression debug_frame for nowDavid Blaikie2014-03-281-1/+1
| | | | | | | | Turns out debug_frame does use multiple fragments, so it doesn't compress correctly with the current approach. Disable compressing it for now while I figure out what's the best solution for it. llvm-svn: 205059
* X86: Disable IsLegalToCallImmediateAddr for Win32David Majnemer2014-03-281-1/+4
| | | | | | | | | | WinCOFF cannot form PC relative relocations to support absolute MCValues. We should reenable this once WinCOFF supports emission of IMAGE_REL_I386_REL32 relocations. This fixes PR19272. llvm-svn: 205058
* [PowerPC] Fix VSX permutation iselHal Finkel2014-03-281-1/+1
| | | | | | | Not only did I invert the indices when I wrote the code, but I also did the same thing when I wrote the regression test. Oops. llvm-svn: 205046
* [PowerPC] v2[fi]64 need to be explicitly passed in VSX registersHal Finkel2014-03-282-7/+36
| | | | | | | | v2[fi]64 values need to be explicitly passed in VSX registers. This is because the code in TRI that finds the minimal register class given a register and a value type will assert if given an Altivec register and a non-Altivec type. llvm-svn: 205041
* Map ELf flags back to more specific section kinds.Rafael Espindola2014-03-281-2/+28
| | | | | | With that, convert another llc -filetype=obj test. llvm-svn: 205031
* Parse .gpdword and convert another llc -filetype=obj test.Rafael Espindola2014-03-281-1/+22
| | | | llvm-svn: 205028
* SLPVectorizer: Take credit for free extractelement instructionsArnold Schwaighofer2014-03-281-2/+11
| | | | | | | | | Extract element instructions that will be removed when vectorzing lower the cost. Patch by Arch D. Robison! llvm-svn: 205020
* SLPVectorizer: Fix typosArnold Schwaighofer2014-03-281-2/+2
| | | | | | Patch by Arch D. Robison! llvm-svn: 205019
* SLPVectorizer: Ignore users that are insertelements we can reschedule themArnold Schwaighofer2014-03-281-30/+65
| | | | | | Patch by Arch D. Robison! llvm-svn: 205018
* Add const to a method I missed in the previous commit.Rafael Espindola2014-03-281-7/+4
| | | | llvm-svn: 205014
* Add const.Rafael Espindola2014-03-284-7/+8
| | | | llvm-svn: 205013
* Revert "InstCombine: merge constants in both operands of icmp."Erik Verbruggen2014-03-282-14/+12
| | | | | | | | | This reverts commit r204912, and follow-up commit r204948. This introduced a performance regression, and the fix is not completely clear yet. llvm-svn: 205010
* Revert "GVN: merge overflow intrinsics with non-overflow instructions."Erik Verbruggen2014-03-281-124/+58
| | | | | | | | | This reverts commit r203553, and follow-up commits r203558 and r203574. I will follow this up on the mailinglist to do it in a way that won't cause subtle PRE bugs. llvm-svn: 205009
* Add ARM big endian Target (armeb, thumbeb)Christian Pirker2014-03-2818-87/+431
| | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D3095 llvm-svn: 205007
* R600: avoid calling std::next on an iterator that might be end()Tim Northover2014-03-281-3/+3
| | | | | | | | This was causing my llc to go into an infinite loop on CodeGen/R600/address-space.ll (just triggered recently by some allocator changes). llvm-svn: 205005
* Intrinsics: expand semantics of LLVMExtendedVectorType (& trunc)Tim Northover2014-03-282-22/+48
| | | | | | | | | | | | These are used in the ARM backends to aid type-checking on patterns involving intrinsics. By making sure one argument is an extended/truncated version of another. However, there's no reason to limit them to just vectors types. For example AArch64 has the instruction "uqshrn sD, dN, #imm" which would naturally use an intrinsic taking an i64 and returning an i32. llvm-svn: 205003
* [Allocator Cleanup] Move generic pointer alignment helper out of anChandler Carruth2014-03-281-15/+3
| | | | | | | out-of-line private static method and into the collection of inline alignment helpers in MathExtras.h. llvm-svn: 204995
* [Allocator Cleanup] Make the growth of the "slab" size of theChandler Carruth2014-03-281-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | BumpPtrAllocator significantly less strange by making it a simple function of the number of slabs allocated rather than by making it a recurrance. I *think* the previous behavior was essentially that the size of the slabs would be doubled after the first 128 were allocated, and then doubled again each time 64 more were allocated, but only if every allocation packed perfectly into the slab size. If not, the wasted space wouldn't be counted toward increasing the size, but allocations over the size threshold *would*. And since the allocations over the size threshold might be much larger than the slab size, this could have somewhat surprising consequences where we rapidly grow the slab size. This currently requires adding state to the allocator to track the number of slabs currently allocated, but that isn't too bad. I'm planning further changes to the allocator that will make this state fall out even more naturally. It still doesn't fully decouple the growth rate from the allocations which are over the size threshold. That fix is coming later. This specific fix will allow making the entire thing into a more stateless device and lifting the parameters into template parameters rather than runtime parameters. llvm-svn: 204993
* [cleanup] Hoist the initialization and constants for slab sizes to theChandler Carruth2014-03-281-20/+17
| | | | | | | | top of the default jit memory manager. This will allow them to be used as template parameters rather than runtime parameters in a subsequent commit. llvm-svn: 204992
* C++11: convert verbose loops to range-based loops.Adrian Prantl2014-03-271-7/+6
| | | | llvm-svn: 204981
* [PowerPC] Use a small cleanup pass to remove VSX self copiesHal Finkel2014-03-273-0/+78
| | | | | | | | | | | | As explained in r204976, because of how the allocation of VSX registers interacts with the call-lowering code, we sometimes end up generating self VSX copies. Specifically, things like this: %VSL2<def> = COPY %F2, %VSL2<imp-use,kill> (where %F2 is really a sub-register of %VSL2, and so this copy is a nop) This adds a small cleanup pass to remove these prior to post-RA scheduling. llvm-svn: 204980
* Provide a target override for the cost of using a callee-saved registerManman Ren2014-03-271-2/+6
| | | | | | | | | for the first time. Thanks Andy for the discussion. rdar://16162005 llvm-svn: 204979
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