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* Revert r332657: "[AA] cfl-anders-aa with field sensitivity"George Burgess IV2018-05-173-156/+110
| | | | | | | I don't believe the person who LGTMed this review has appropriate context on this code. I apologize if I'm wrong. llvm-svn: 332674
* AMDGPU/SI: Don't promote alloca to vector for atomic load/storeChangpeng Fang2018-05-171-3/+5
| | | | | | | | | | | | | Summary: Don't promote alloca to vector for atomic load/store Reviewer: arsenm Differential Revision: https://reviews.llvm.org/D46085 llvm-svn: 332673
* Revert "[pdb] Change /DEBUG:GHASH to emit 8 byte hashes."Zachary Turner2018-05-173-21/+12
| | | | | | | A few tests haven't been properly updated, so reverting while I have time to investigate proper fixes. llvm-svn: 332672
* [pdb] Change /DEBUG:GHASH to emit 8 byte hashes.Zachary Turner2018-05-173-12/+21
| | | | | | | | | | | | | | | | Previously we emitted 20-byte SHA1 hashes. This is overkill for identifying debug info records, and has the negative side effect of making object files bigger and links slower. By using only the last 8 bytes of a SHA1, we get smaller object files and ~10% faster links. This modifies the format of the .debug$H section by adding a new value for the hash algorithm field, so that the linker will still work when its object files have an old format. Differential Revision: https://reviews.llvm.org/D46855 llvm-svn: 332669
* [WebAssembly] Add Wasm personality and isScopedEHPersonality()Heejin Ahn2018-05-1711-32/+35
| | | | | | | | | | | | | | | | | | | | | Summary: - Add wasm personality function - Re-categorize the existing `isFuncletEHPersonality()` function into two different functions: `isFuncletEHPersonality()` and `isScopedEHPersonality(). This becomes necessary as wasm EH uses scoped EH instructions (catchswitch, catchpad/ret, and cleanuppad/ret) but not outlined funclets. - Changed some callsites of `isFuncletEHPersonality()` to `isScopedEHPersonality()` if they are related to scoped EH IR-level stuff. Reviewers: majnemer, dschuff, rnk Subscribers: jfb, sbc100, jgravelle-google, eraman, JDevlieghere, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D45559 llvm-svn: 332667
* [ORC] Consolidate materialization errors, and generate them in VSO'sLang Hames2018-05-171-28/+17
| | | | | | | | | | | notifyFailed method rather than passing in an error generator. VSO::notifyFailed is responsible for notifying queries that they will not succeed due to error. In practice the queries don't care about the details of the failure, just the fact that a failure occurred for some symbols. Having VSO::notifyFailed take care of this simplifies the interface. llvm-svn: 332666
* [codeview] Include record prefix in global type hashingReid Kleckner2018-05-171-0/+1
| | | | | | | | | | | | The prefix includes type kind, which is important to preserve. Two different type leafs can easily have the same interior record contents as another type. We ran into this issue in PR37492 where a bitfield type record collided with a const modifier record. Their contents were bitwise identical, but their kinds were different. llvm-svn: 332664
* ARC, Nios2: Silence build warnings. NFCI.Peter Collingbourne2018-05-177-12/+5
| | | | llvm-svn: 332663
* [AA] cfl-anders-aa with field sensitivityDavid Bolvansky2018-05-173-110/+156
| | | | | | | | | | | | | | | | | | | Summary: There was some unfinished work started for offset tracking in CFLGraph by the author of implementation of Andersen algorithm. This work was completed and support for field sensitivity was added to the core of Andersen algorithm. The performance results seem promising. SPEC2006 int_base score was increased by 1.1 % (I compared clang 6.0 with clang 6.0 with this patch). The avergae compile time was increased by +- 1 % according my measures with small and medium C/C++ projects (I did not tested it on the large projects with milions of lines of code) Reviewers: chandlerc, george.burgess.iv, rja Reviewed By: rja Subscribers: rja, llvm-commits Differential Revision: https://reviews.llvm.org/D46282 llvm-svn: 332657
* [LV][VPlan] Build plain CFG with simple VPInstructions for outer loops.Diego Caballero2018-05-179-42/+838
| | | | | | | | | | | | | | | | | | | Patch #3 from VPlan Outer Loop Vectorization Patch Series #1 (RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119523.html). Expected to be NFC for the current inner loop vectorization path. It introduces the basic algorithm to build the VPlan plain CFG (single-level CFG, no hierarchical CFG (H-CFG), yet) in the VPlan-native vectorization path using VPInstructions. It includes: - VPlanHCFGBuilder: Main class to build the VPlan H-CFG (plain CFG without nested regions, for now). - VPlanVerifier: Main class with utilities to check the consistency of a H-CFG. - VPlanBlockUtils: Main class with utilities to manipulate VPBlockBases in VPlan. Reviewers: rengolin, fhahn, mkuper, mssimpso, a.elovikov, hfinkel, aprantl. Differential Revision: https://reviews.llvm.org/D44338 llvm-svn: 332654
* Add a limit for phi folding instcombineXinliang David Li2018-05-171-1/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D47023 llvm-svn: 332653
* [RISCV] Separate base from offset in lowerGlobalAddressSameer AbuAsal2018-05-171-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When lowering global address, lower the base as a TargetGlobal first then create an SDNode for the offset separately and chain it to the address calculation This optimization will create a DAG where the base address of a global access will be reused between different access. The offset can later be folded into the immediate part of the memory access instruction. With this optimization we generate: lui a0, %hi(s) addi a0, a0, %lo(s) ; shared base address. addi a1, zero, 20 ; 2 instructions per access. sw a1, 44(a0) addi a1, zero, 10 sw a1, 8(a0) addi a1, zero, 30 sw a1, 80(a0) Instead of: lui a0, %hi(s+44) ; 3 instructions per access. addi a1, zero, 20 sw a1, %lo(s+44)(a0) lui a0, %hi(s+8) addi a1, zero, 10 sw a1, %lo(s+8)(a0) lui a0, %hi(s+80) addi a1, zero, 30 sw a1, %lo(s+80)(a0) Which will save one instruction per access. Reviewers: asb, apazos Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, apazos, asb, llvm-commits Differential Revision: https://reviews.llvm.org/D46989 llvm-svn: 332641
* [RISCV] Implement MC layer support for the tail pseudoinstructionMandeep Singh Grang2018-05-173-3/+14
| | | | | | | | | | | | | | | | Summary: This patch implements MC support for tail psuedo instruction. A follow-up patch implements the codegen support as well as handling of the indirect tail pseudo instruction. Reviewers: asb, apazos Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, llvm-commits Differential Revision: https://reviews.llvm.org/D46221 llvm-svn: 332634
* [WebAssembly] MC: Fix typo in commentSam Clegg2018-05-171-1/+1
| | | | llvm-svn: 332632
* [X86] Split WriteCMOV + WriteCMOV2 scheduler classesSimon Pilgrim2018-05-1711-71/+36
| | | | | | Handle SNB+ targets which treat CMOVA/CMOVBE specially due to partial EFLAGS handling. llvm-svn: 332626
* AMDGPU/SI: Handle infinite loop for the structurizer to work with CFG with ↵Changpeng Fang2018-05-171-0/+32
| | | | | | | | | | | | | | | | | | | infinite loops. Summary: The current StructurizeCFG pass only works for CFG with one exit. AMDGPUUnifyDivergentExitNodes combines multiple "return" blocks and/or "unreachable" blocks to one exit block for the Structurizer to work. However, infinite loop is another kind of special "exit", and if we don't handle it, the case of multiple exits will prevent the structurizer from working. In this work, for each infinite loop, we add a dummy edge to the "return" block, and thus the AMDGPUUnifyDivergentExitNodes pass will work with infinite loops. This will make CFG with infinite loops be structurized. Reviewer: nhaehnle Differential Revision: https://reviews.llvm.org/D46340 llvm-svn: 332625
* [mips] Add support for Global INValidate ASEPetar Jovanovic2018-05-1713-2/+199
| | | | | | | | | | | | | | | | | | This includes Instructions: ginvi, ginvt, Assembler directives: .set ginv, .set noginv, .module ginv, .module noginv Attribute: ginv .MIPS.abiflags: GINV (0x20000) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D46268 llvm-svn: 332624
* [InstCombine] Propagate the nsw/nuw flags from the add in the 'shifty' abs ↵Craig Topper2018-05-171-1/+5
| | | | | | | | | | | | pattern to the sub in the select version. According to alive this is valid. I'm hoping to use this to make an assumption that the sign bit is zero after this sequence. The only way it wouldn't be is if the input was INT__MIN, but by preserving the flags we can make doing this to INT_MIN UB. The nuw flags is weird because it creates such a contradiction that the original number would have to be positive meaning we could remove the select entirely, but we don't get that far. Differential Revision: https://reviews.llvm.org/D46988 llvm-svn: 332623
* [RISCV] Set isReMaterializable on ADDI and LUI instructionsAlex Bradbury2018-05-173-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | The isReMaterlizable flag is somewhat confusing, unlike most other instruction flags it is currently interpreted as a hint (mightBeRematerializable would be a better name). While LUI is always rematerialisable, for an instruction like ADDI it depends on its operands. TargetInstrInfo::isTriviallyReMaterializable will call TargetInstrInfo::isReallyTriviallyReMaterializable, which in turn calls TargetInstrInfo::isReallyTriviallyReMaterializableGeneric. We rely on the logic in the latter to pick out instances of ADDI that really are rematerializable. The isReMaterializable flag does make a difference on a variety of test programs. The recently committed remat.ll test case demonstrates how stack usage is reduce and a unnecessary lw/sw can be removed. Stack usage in the Proc0 function in dhrystone reduces from 192 bytes to 112 bytes. For the sake of completeness, this patch also implements RISCVRegisterInfo::isConstantPhysReg. Although this is called from a number of places, it doesn't seem to result in different codegen for any programs I've thrown at it. However, it is called in the rematerialisation codepath and it seems sensible to implement something correct here. Differential Revision: https://reviews.llvm.org/D46182 llvm-svn: 332617
* [X86][BtVer2] ADC/SBB take 2cy on an ALU pipe, not 1cy like ADD/SUBSimon Pilgrim2018-05-171-1/+1
| | | | llvm-svn: 332616
* In thin and full LTO + CFI, direct function calls may go through jump tableDmitry Mikulin2018-05-172-40/+82
| | | | | | | | | entries to reach the target. Since these calls don't require type checks, we can short-circuit them to their real targets. Differential Revision: https://reviews.llvm.org/D46326 llvm-svn: 332610
* [Hexagon] Use addAliasForDirective for data directivesAlex Bradbury2018-05-171-39/+4
| | | | | | | | | | | Data directives such as .word, .half, .hword are currently parsed using HexagonAsmParser::ParseDirectiveValue which effectively duplicates logic from AsmParser::parseDirectiveValue. This patch deletes that duplicated logic in favour of using addAliasForDirective. Differential Revision: https://reviews.llvm.org/D46999 llvm-svn: 332607
* [X86] Split WriteADC/WriteADCRMW scheduler classesSimon Pilgrim2018-05-1711-130/+64
| | | | | | For integer ALU instructions taking eflags as an input (ADC/SBB/ADCX/ADOX) llvm-svn: 332605
* [SystemZ] Commenting (NFC)Jonas Paulsson2018-05-172-6/+10
| | | | | | | Some minor commenting in scheduler files. Review: Ulrich Weigand llvm-svn: 332599
* [X86][SNB] Minor scheduler cleanupSimon Pilgrim2018-05-171-7/+3
| | | | | | Merge 2 instregex and explain the VMOVDQArr/MOVDQArr difference llvm-svn: 332591
* [AArch64][SVE] Asm: Support for structured ST2, ST3 and ST4 (scalar+scalar) ↵Sander de Smalen2018-05-172-1/+37
| | | | | | | | | | | | store instructions. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46680 llvm-svn: 332584
* Require DominatorTree when requiring/preserving LoopInfo in the old pass managerMikael Holmen2018-05-173-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Require DominatorTree when requiring/preserving LoopInfo in the old pass manager BreakCriticalEdges tries to keep LoopInfo and DominatorTree updated if they exist. However, since commit r321653 and r321805, to update LoopInfo we must have a DominatorTree, or we will hit an assert. To fix this we now make a couple of passes that only required/preserved LoopInfo also require DominatorTree. This solves PR37334. Reviewers: eli.friedman, efriedma Reviewed By: efriedma Subscribers: efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D46829 llvm-svn: 332583
* [Analysis] Only use _unlocked stdio functions on linuxMartin Storsjo2018-05-171-1/+2
| | | | | | | | | | | | | | | | The existing comment said that the functions were available only on GNU/Linux (and on certain Android versions), but only checked T.isGNUEnvironment() which also is true on MinGW (for arch-windows-gnu triplets), which doesn't have such functions. Existing checks in the initialize function in TargetLibraryInfo.cpp also use only T.isOSLinux() to check for glibc features. This fixes use of stdio on MinGW. Differential Revision: https://reviews.llvm.org/D47002 llvm-svn: 332581
* [SROA] Handle PHI with multiple duplicate predecessorsBjorn Pettersson2018-05-171-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The verifier accepts PHI nodes with multiple entries for the same basic block, as long as the value is the same. As seen in PR37203, SROA did not handle such PHI nodes properly when speculating loads over the PHI, since it inserted multiple loads in the predecessor block and changed the PHI into having multiple entries for the same basic block, but with different values. This patch teaches SROA to reuse the same speculated load for each PHI duplicate entry in such situations. Resolves: https://bugs.llvm.org/show_bug.cgi?id=37203 Reviewers: uabelho, chandlerc, hfinkel, bkramer, efriedma Reviewed By: efriedma Subscribers: dberlin, efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D46426 llvm-svn: 332577
* [SROA] pr37267: fix assertion failure in integer wideningHiroshi Inoue2018-05-171-0/+8
| | | | | | | | | | The current integer widening does not support rewriting partial split slices in rewriteIntegerStore (and rewriteIntegerLoad). This patch adds explicit checks for this case in isIntegerWideningViableForSlice. Before r322533, splitting is allowed only for the whole-alloca slice and hence the above case is implicitly rejected by another check `if (DL.getTypeStoreSize(ValueTy) > Size)` because whole-alloca slice is larger than the partition. Differential Revision: https://reviews.llvm.org/D46750 llvm-svn: 332575
* [RISCV] Add support for .half, .hword, .word, .dword directivesAlex Bradbury2018-05-172-0/+6
| | | | | | | | | | These directives are recognised by gas. Support is added through the use of addAliasForDirective. Also match RISC-V gcc in preferring .half and .word for 16-bit and 32-bit data directives. llvm-svn: 332574
* [X86] Add OptForSize to a couple load folding patterns. Remove some bad ↵Craig Topper2018-05-172-10/+7
| | | | | | | | FIXME comments. The FIXME comments were about preventing load folding to avoid a partial xmm update. But these instructions use GPR as input when the load isn't folded. This won't help prevent a partial xmm update. llvm-svn: 332573
* [WebAssembly] Fix the opcode number for i64.load16_u.Dan Gohman2018-05-171-1/+1
| | | | | | Fixes PR37488. llvm-svn: 332561
* [CodeGen] Use MachineInstr::getOperand(0) instead of gets the defs ↵Craig Topper2018-05-161-1/+1
| | | | | | | | iterator_range and calling begin. NFC Defs are well defined to come first in MachineInstr operand list. No need for a more complex indirection. llvm-svn: 332559
* Revert 332508 as it caused problems in the clang test suite.Greg Clayton2018-05-161-4/+0
| | | | llvm-svn: 332555
* [STLExtras] Add size() for ranges, and remove distance()Vedant Kumar2018-05-165-7/+10
| | | | | | | | | | r332057 introduced distance() for ranges. Based on post-commit feedback, this renames distance() to size(). The new size() is also only enabled when the operation is O(1). Differential Revision: https://reviews.llvm.org/D46976 llvm-svn: 332551
* [NFC] WebAssembly build break #2JF Bastien2018-05-161-0/+4
| | | | | | | | | | | | | | | | | Summary: Same as r332530, move WasmSymbol::dump to an implementation file to avoid linker issues when the dump function is seen in the header, doesn't get eliminated, and then linking fails because of the missing dependency. <rdar://problem/40258137> Reviewers: sbc100, ncw, paquette, vsk, dschuff Subscribers: jgravelle-google, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D46985 llvm-svn: 332542
* [ORC] Rewrite the VSO symbol table yet again. Update related utilities.Lang Hames2018-05-164-438/+694
| | | | | | | | | | | | | | | | | | | VSOs now track dependencies for materializing symbols. Each symbol must have its dependencies registered with the VSO prior to finalization. Usually this will involve registering the dependencies returned in AsynchronousSymbolQuery::ResolutionResults for queries made while linking the symbols being materialized. Queries against symbols are notified that a symbol is ready once it and all of its transitive dependencies are finalized, allowing compilation work to be broken up and moved between threads without queries returning until their symbols fully safe to access / execute. Related utilities (VSO, MaterializationUnit, MaterializationResponsibility) are updated to support dependence tracking and more explicitly track responsibility for symbols from the point of definition until they are finalized. llvm-svn: 332541
* [X86][SNB] Remove unnecessary CVT InstRW overridesSimon Pilgrim2018-05-161-82/+24
| | | | llvm-svn: 332536
* [WebAssembly] Remove unused headers in MCWasmObjectWriterSam Clegg2018-05-161-3/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D46969 llvm-svn: 332535
* [InstCombine] Fix the signature of fgets_unlocked.Benjamin Kramer2018-05-161-2/+2
| | | | | | | It returns a pointer, not an int. This miscompiles all code that uses the return value of fgets. llvm-svn: 332531
* [NFC] WebAssembly build fixJF Bastien2018-05-161-0/+13
| | | | | | | | | | | | | | | | | | | | | | Summary: r332305 added a use of llvm::wasm::toString in llvm::object::WasmSymbol::print, which is in a header file. It also moves toString to BinaryFormat. This has the unintended side-effect that any inclusion of Object/Wasm.h now relies on toString, and needs to required_libraries = BinaryFormat. Thankfully most builds don't fail with this because print just isn't used and gets eliminated, dropping the required dependency in the process. Not all builds are so lucky. Fix this issue by moving print to the corresponding .cpp file. <rdar://problem/40258137> Reviewers: sbc100, ncw, paquette Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D46977 llvm-svn: 332530
* [MachineOutliner] Don't outline instructions that modify SP.Eli Friedman2018-05-161-0/+8
| | | | | | | | | | | | | This breaks the code which saves and restores LR, so we can't outline without doing something more complicated for stack adjustment. Found by inspection; we get lucky in most cases because getMemOpInfo only handles STRWpost, not any other pre/post-increment forms. But it hits a couple of artificial testcases in the tree. Differential Revision: https://reviews.llvm.org/D46920 llvm-svn: 332529
* [Hexagon] Fix the order of operands when selecting QCATKrzysztof Parzyszek2018-05-161-2/+2
| | | | llvm-svn: 332526
* [Hexagon] Mark HVX vector predicate bitwise ops as legal, add patternsKrzysztof Parzyszek2018-05-162-35/+73
| | | | llvm-svn: 332525
* [X86][SSE] Reduce instruction/register usages for v4i32 vector shifts (PR37441)Simon Pilgrim2018-05-161-16/+39
| | | | | | | | | | As suggested by Fabian on PR37441, use PSHUFLW to extend shift amount types for use with PSRAD/PSRLD to reduce register pressure. Some of this ideally would be done by combineTargetShuffle but its tricky to do as most of the shuffles are sharing inputs. Differential Revision: https://reviews.llvm.org/D46959 llvm-svn: 332524
* AMDGPU : Recalculate SGPRs when trap handler is supportedKonstantin Zhuravlyov2018-05-162-6/+11
| | | | | | Differential Revision: https://reviews.llvm.org/D29911 llvm-svn: 332523
* Fix small grammar-o.Eric Christopher2018-05-161-1/+1
| | | | llvm-svn: 332522
* Fix up a misleading format warning.Eric Christopher2018-05-161-1/+1
| | | | llvm-svn: 332521
* [WebAssembly] MC: Ensure that FUNCTION_OFFSET relocations are always against ↵Sam Clegg2018-05-161-1/+17
| | | | | | | | | | | | | | | | | function symbols. The getAtom() method wasn't doing what we needed in all cases. We want the symbols for the function which defines that section. We can compute this easily enough and we know that we have at most one function in each section. Once this lands I will revert rL331412 which is no longer needed. Fixes PR37409 Differential Revision: https://reviews.llvm.org/D46970 llvm-svn: 332517
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