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* AArch64: Relax assert about large shift sizes.Matthias Braun2015-02-241-3/+9
| | | | | | | | | | The reason why these large shift sizes happen is because OpaqueConstants currently inhibit alot of DAG combining, but that has to be addressed in another commit (like the proposal in D6946). Differential Revision: http://reviews.llvm.org/D6940 llvm-svn: 230355
* DAGCombiner: Move variable definitions closer to use; NFCMatthias Braun2015-02-241-38/+38
| | | | llvm-svn: 230354
* DAGCombiner: Move variable declaration closer to definiion; NFCMatthias Braun2015-02-241-3/+3
| | | | llvm-svn: 230353
* R600/SI: Remove isel mubuf legalizationTom Stellard2015-02-242-130/+0
| | | | | | | We legalize mubuf instructions post-instruction selection, so this code is no longer needed. llvm-svn: 230352
* ARM: treat [N x i32] and [N x i64] as AAPCS composite typesTim Northover2015-02-244-69/+107
| | | | | | | | | | | The logic is almost there already, with our special homogeneous aggregate handling. Tweaking it like this allows front-ends to emit AAPCS compliant code without ever having to count registers or add discarded padding arguments. Only arrays of i32 and i64 are needed to model AAPCS rules, but I decided to apply the logic to all integer arrays for more consistency. llvm-svn: 230348
* Revert "Raising minimum required CMake version to 2.8.12.2."Tobias Grosser2015-02-242-2/+2
| | | | | | | | | | | This reverts commit r230062. Debian stable (wheezy) ships still with cmake 2.8.9. The commit broke my LLVM/Polly buildbot, to my knowledge our only Linux+cmake buildbot. llvm-svn: 230343
* simplify control flow; NFCSanjay Patel2015-02-241-8/+9
| | | | llvm-svn: 230342
* Revert r230280: "Bugfix: SCEVExpander incorrectly marks increment operations ↵Hans Wennborg2015-02-241-31/+2
| | | | | | | | | | as no-wrap" This caused PR22674, failing this assert: Instructions.h:2281: llvm::Value* llvm::PHINode::getOperand(unsigned int) const: Assertion `i_nocapture < OperandTraits<PHINode>::operands(this) && "getOperand() out of range!"' failed. llvm-svn: 230341
* [x32] Mark RBX as reserved when EBX is the base pointer.Michael Kuperstein2015-02-241-1/+3
| | | | | | This should have gone into r230334. llvm-svn: 230339
* fix typo in comment; NFCSanjay Patel2015-02-241-1/+1
| | | | llvm-svn: 230338
* [x32] x32 should use ebx as the base pointer.Michael Kuperstein2015-02-241-8/+9
| | | | | | This fixes the original issue in PR22655, but not the secondary one. llvm-svn: 230334
* [SDAG] Handle LowerOperation returning its input consistentlyHal Finkel2015-02-242-5/+9
| | | | | | | | | | | | | | | | | | | For almost all node types, if the target requested custom lowering, and LowerOperation returned its input, we'd treat the original node as legal. This did not work, however, for many loads and stores, because they follow slightly different code paths, and we did not account for the possibility of LowerOperation returning its input at those call sites. I think that we now handle this consistently everywhere. At the call sites in LegalizeDAG, we used to assert in this case, so there's no functional change for any existing code there. For the call sites in LegalizeVectorOps, this really only affects whether or not we set Changed = true, but I think makes the semantics clearer. No test case here, but it will be covered by an upcoming PowerPC commit adding QPX support. llvm-svn: 230332
* [mips] Reformat some TableGen definitions. NFC.Toma Tabacu2015-02-242-14/+18
| | | | | | | | | | | | | | Summary: Separated some instruction and pseudo-instruction definitions from InstAlias definitions, added banner for pseudo-instructions and removed a redundant whitespace from a pseudo-instruction definition. No functional change. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7552 llvm-svn: 230327
* Fix alloca_instruments_all_paddings.cc test to work under higher -O levels ↵Kuba Brecka2015-02-241-7/+5
| | | | | | | | | | (llvm part) When AddressSanitizer only a single dynamic alloca and no static allocas, due to an early exit from FunctionStackPoisoner::poisonStack we forget to unpoison the dynamic alloca. This patch fixes that. Reviewed at http://reviews.llvm.org/D7810 llvm-svn: 230316
* [X86] Remove the AbsMem32 type from the assembly parser. Only really need ↵Craig Topper2015-02-242-12/+2
| | | | | | the 16-bit version which will automatically get prioritized over AbsMem. llvm-svn: 230313
* Beginning of alloca implementation for Mips fast-iselReed Kotler2015-02-241-20/+139
| | | | | | | | | | | | | | | | Summary: Begin to add various address modes; including alloca. Test Plan: Make sure there are no regressions in test-suite at O0/02 in mips32r1/r2 Reviewers: dsanders Reviewed By: dsanders Subscribers: echristo, rfuhler, llvm-commits Differential Revision: http://reviews.llvm.org/D6426 llvm-svn: 230300
* Fix handling of negative offsets for AddrModeT2_i8s4 in rewriteT2FrameIndex.Bob Wilson2015-02-241-5/+2
| | | | | | | | | | | | | | This is a follow up to r230233 to fix something that I noticed by inspection. The AddrModeT2_i8s4 addressing mode does not support negative offsets. I spent a good chunk of the day trying to come up with a testcase for this but was not successful. This addressing mode is used to spill and restore GPRPair registers in Thumb2 code and that does not happen often. We also make very limited used of negative offsets when lowering frame indexes. I am going ahead with the change anyway, because I am pretty confident that it is correct. I also added a missing assertion to check that the low bits of the scaled offset are zero. llvm-svn: 230297
* Fix bug 22641Sanjoy Das2015-02-241-17/+5
| | | | | | | | | | | | | | | The bug was a result of getPreStartForExtend interpreting nsw/nuw flags on an add recurrence more strongly than is legal. {S,+,X}<nsw> implies S+X is nsw only if the backedge of the loop is taken at least once. NOTE: I had accidentally committed an unrelated change with the commit message of this change in r230275 (r230275 was reverted in r230279). This is the correct change for this commit message. Differential Revision: http://reviews.llvm.org/D7808 llvm-svn: 230291
* [LTO API] add lto_codegen_set_module to set the destination module.Manman Ren2015-02-242-0/+20
| | | | | | | | | | | | | | | | | | When debugging LTO issues with ld64, we use -save-temps to save the merged optimized bitcode file, then invoke ld64 again on the single bitcode file to speed up debugging code generation passes and ld64 stuff after code generation. llvm linking a single bitcode file via lto_codegen_add_module will generate a different bitcode file from the single input. With the newly-added lto_codegen_set_module, we can make sure the destination module is the same as the input. lto_codegen_set_module will transfer the ownship of the module to code generator. rdar://19024554 llvm-svn: 230290
* [LoopAccesses] LAA::getInfo to use const reference for stride parameterAdam Nemet2015-02-241-25/+24
| | | | | | And other required const-correctness fixes to make this work. llvm-svn: 230289
* X86: Only use 'lea' in Win64 epilogues if a frame pointer existsDavid Majnemer2015-02-241-7/+21
| | | | | | | We can only use 'add' in epilogues, 'lea' is not permitted unless we've established a frame pointer in the prologue. llvm-svn: 230286
* New instcombine rule: max(~a,~b) -> ~min(a, b)Sanjoy Das2015-02-243-23/+66
| | | | | | | | | | This case is interesting because ScalarEvolutionExpander lowers min(a, b) as ~max(~a,~b). I think the profitability heuristics can be made more clever/aggressive, but this is a start. Differential Revision: http://reviews.llvm.org/D7821 llvm-svn: 230285
* Bugfix: SCEVExpander incorrectly marks increment operations as no-wrapSanjoy Das2015-02-231-2/+31
| | | | | | | | | | | | | | | | | | | | | When emitting the increment operation, SCEVExpander marks the operation as nuw or nsw based on the flags on the preincrement SCEV. This is incorrect because, for instance, it is possible that {-6,+,1} is <nuw> while {-6,+,1}+1 = {-5,+,1} is not. This change teaches SCEV to mark the increment as nuw/nsw only if it can explicitly prove that the increment operation won't overflow. Apart from the attached test case, another (more realistic) manifestation of the bug can be seen in Transforms/IndVarSimplify/pr20680.ll. NOTE: this change was landed with an incorrect commit message in rL230275 and was reverted for that reason in rL230279. This commit message is the correct one. Differential Revision: http://reviews.llvm.org/D7778 llvm-svn: 230280
* Revert 230275.Sanjoy Das2015-02-231-31/+2
| | | | | | | | 230275 got committed with an incorrect commit message due to a mixup on my side. Will re-land in a few moments with the correct commit message. llvm-svn: 230279
* Fix based on post-commit comment on D7816 & rL230177 - BUILD_VECTOR operand ↵Simon Pilgrim2015-02-231-4/+5
| | | | | | truncation was using the the BV's output scalar type instead of the input type. llvm-svn: 230278
* [X86] Teach how to custom lower double-to-half conversions under fast-math.Andrea Di Biagio2015-02-231-0/+15
| | | | | | | | | | | | | This patch teaches the backend how to expand a double-half conversion into a double-float conversion immediately followed by a float-half conversion. We do this only under fast-math, and if float-half conversions are legal for the target. Added test CodeGen/X86/fastmath-float-half-conversion.ll Differential Revision: http://reviews.llvm.org/D7832 llvm-svn: 230276
* Fix bug 22641Sanjoy Das2015-02-231-2/+31
| | | | | | | | | | | The bug was a result of getPreStartForExtend interpreting nsw/nuw flags on an add recurrence more strongly than is legal. {S,+,X}<nsw> implies S+X is nsw only if the backedge of the loop is taken at least once. Differential Revision: http://reviews.llvm.org/D7808 llvm-svn: 230275
* Fix invalid cast.Rafael Espindola2015-02-231-1/+1
| | | | | | | | Fixes PR22525. Patch by Ben Longbons with testcase by me. llvm-svn: 230271
* X86: Use a smaller 'mov' instruction for stack probe callsDavid Majnemer2015-02-231-3/+13
| | | | | | | | | | | | | Prologue emission, in some cases, requires calls to a stack probe helper function. The amount of stack to probe is passed as a register argument in the Win64 ABI but the instruction sequence used is pessimistic: it assumes that the number of bytes to probe is greater than 4 GB. Instead, select a more appropriate opcode depending on the number of bytes we are going to probe. llvm-svn: 230270
* X86: Use 'mov' instead of 'lea' in Win64 SEH prologues when possibleDavid Majnemer2015-02-231-2/+5
| | | | | | | 'mov' and 'lea' are equivalent when the displacement applied with 'lea' is zero. However, 'mov' should encode smaller. llvm-svn: 230269
* X86: Explain why we cannot use a 'mov' in a Win64 epilogueDavid Majnemer2015-02-231-0/+6
| | | | llvm-svn: 230268
* X86: Consistently use 'epilogue' instead of 'epilog'David Majnemer2015-02-231-1/+1
| | | | llvm-svn: 230267
* add newline for easier reading; NFCSanjay Patel2015-02-231-1/+1
| | | | llvm-svn: 230265
* [AsmPrinter] Access pointers to globals via pcrel GOT entriesBruno Cardoso Lopes2015-02-233-15/+231
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Front-ends could use global unnamed_addr to hold pointers to other symbols, like @gotequivalent below: @foo = global i32 42 @gotequivalent = private unnamed_addr constant i32* @foo @delta = global i32 trunc (i64 sub (i64 ptrtoint (i32** @gotequivalent to i64), i64 ptrtoint (i32* @delta to i64)) to i32) The global @delta holds a data "PC"-relative offset to @gotequivalent, an unnamed pointer to @foo. The darwin/x86-64 assembly output for this follows: .globl _foo _foo: .long 42 .globl _gotequivalent _gotequivalent: .quad _foo .globl _delta _delta: .long _gotequivalent-_delta Since unnamed_addr indicates that the address is not significant, only the content, we can optimize the case above by replacing pc-relative accesses to "GOT equivalent" globals, by a PC relative access to the GOT entry of the final symbol instead. Therefore, "delta" can contain a pc relative relocation to foo's GOT entry and we avoid the emission of "gotequivalent", yielding the assembly code below: .globl _foo _foo: .long 42 .globl _delta _delta: .long _foo@GOTPCREL+4 There are a couple of advantages of doing this: (1) Front-ends that need to emit a great deal of data to store pointers to external symbols could save space by not emitting such "got equivalent" globals and (2) IR constructs combined with this opt opens a way to represent GOT pcrel relocations by using the LLVM IR, which is something we previously had no way to express. Differential Revision: http://reviews.llvm.org/D6922 rdar://problem/18534217 llvm-svn: 230264
* Removing unused private field.Andrew Kaylor2015-02-231-3/+1
| | | | llvm-svn: 230259
* Second attempt to fix WinEHCatchDirector build failures.Andrew Kaylor2015-02-231-1/+0
| | | | llvm-svn: 230257
* Attempting to fix WinEHCatchDirector destructor related build failures.Andrew Kaylor2015-02-231-0/+1
| | | | llvm-svn: 230252
* Remap frame variables for native Windows exception handling.Andrew Kaylor2015-02-232-392/+649
| | | | | | Differential Revision: http://reviews.llvm.org/D7770 llvm-svn: 230249
* Revert "[X86][MMX] Add MMX instructions to foldable tables"Bruno Cardoso Lopes2015-02-231-82/+0
| | | | | | This reverts commit r230226 since it breaks win buildbots. llvm-svn: 230248
* Revert "Revert "Raising minimum required CMake version to 2.8.12.2.""Chad Rosier2015-02-232-2/+2
| | | | | | This reverts commit r230240, which was an accidental commit. llvm-svn: 230246
* Rewrite the global merge pass to be subprogram agnostic for now.Eric Christopher2015-02-237-42/+28
| | | | | | | | | | | | | It was previously using the subtarget to get values for the global offset without actually checking each function as it was generating code. Go ahead and solidify the current behavior and make the existing FIXMEs more prominent. As a note the ARM backend previously had a thumb1 and non-thumb1 set of defaults. Only the former was tested so I've changed the behavior to only use that for now. llvm-svn: 230245
* Prevent hoisting fmul from THEN/ELSE to IF if there is fmsub/fmadd opportunity.Chad Rosier2015-02-234-2/+41
| | | | | | | | | | | This patch adds the isProfitableToHoist API. For AArch64, we want to prevent a fmul from being hoisted in cases where it is more profitable to form a fmsub/fmadd. Phabricator Review: http://reviews.llvm.org/D7299 Patch by Lawrence Hu <lawrence@codeaurora.org> llvm-svn: 230241
* Revert "Raising minimum required CMake version to 2.8.12.2."Chad Rosier2015-02-232-2/+2
| | | | | | This reverts commit 247aed4710e8befde76da42b27313661dea7cf66. llvm-svn: 230240
* InstSimplify: simplify 0 / X if nnan and nszMehdi Amini2015-02-232-16/+34
| | | | | From: Fiona Glaser <fglaser@apple.com> llvm-svn: 230238
* [mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled.Daniel Sanders2015-02-232-5/+20
| | | | | | | | | | | | | | | | | | | Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
* Fix incorrect immediate size for AddrModeT2_i8s4 in rewriteT2FrameIndex.Bob Wilson2015-02-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The natural way to handle this addressing mode would be to say that it has 8 bits and gets scaled by 4, but since the MC layer is expecting the scaling to be already reflected in the immediate value, we have been setting the Scale to 1. That's fine, but then NumBits needs to be adjusted to reflect the effective increase in the range of the immediate. That adjustment was missing. The consequence is that the register scavenger can fail. The estimateRSStackSizeLimit() function in ARMFrameLowering.cpp correctly assumes that the AddrModeT2_i8s4 address mode can handle scaled offsets up to 1020. Under just the right circumstances, we fail to reserve space for the scavenger because it thinks that nothing will be needed. However, the overly pessimistic behavior in rewriteT2FrameIndex causes some frame indexes to be out of range and require scavenged registers, and so the scavenger asserts. Unfortunately I have not been able to come up with a testcase for this. I can only reproduce it on an internal branch where the frame layout and register allocation is slightly different than trunk. We really need a way to serialize MachineInstr-level IR to write reasonable tests for things like this. rdar://problem/19909005 llvm-svn: 230233
* Sync the __builtin_expects for our 3 quadratically probed hash table ↵Benjamin Kramer2015-02-232-11/+13
| | | | | | | | | | | | | | | | | | implementations. This assumes that a) finding the bucket containing the value is LIKELY b) finding an empty bucket is LIKELY c) growing the table is UNLIKELY I also switched the a) and b) cases for SmallPtrSet as we seem to use the set mostly more for insertion than for checking existence. In a simple benchmark consisting of 2^21 insertions of 2^20 unique pointers into a DenseMap or SmallPtrSet a few percent speedup on average, but nothing statistically significant. llvm-svn: 230232
* [X86][MMX] Add MMX instructions to foldable tablesBruno Cardoso Lopes2015-02-231-0/+82
| | | | | | | | Teach the peephole optimizer to work with MMX instructions by adding entries into the foldable tables. This covers folding opportunities not handled during isel. llvm-svn: 230226
* [X86][MMX] Support folding loads in psll, psrl and psra intrinsicsBruno Cardoso Lopes2015-02-232-0/+21
| | | | llvm-svn: 230225
* AVX-512: recommitted 229837 + bugfix + testElena Demikhovsky2015-02-235-47/+87
| | | | llvm-svn: 230223
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