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* [PEI] Remove required properties and use 'if' instead of std::functionReid Kleckner2017-10-061-49/+23
| | | | | | | | | | | | | | | | | | Summary: After r303360, we initialize UsesCalleeSaves in runOnMachineFunction, which runs after getRequiredProperties. UsesCalleeSaves was initialized to 'false', so getRequiredProperties would always return an empty set. We don't have a TargetMachine available early anymore after r303360. Just removing the requirement of NoVRegs seems to make things work, so let's do that. Reviewers: thegameg, dschuff, MatzeB Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D38597 llvm-svn: 315089
* Bitcode: add an auto-upgrade for LTO section nameSaleem Abdulrasool2017-10-063-1/+31
| | | | | | | | | | | The bitcode reader looks specifically for `__DATA, __objc_catlist` as a section name. However, SVN r304661 removed the spaces (the two names are functionally equivalent but do not compare equally lexicographically). This causes compatibility issues. Add an auto-upgrade path for removing the spaces as well as use the new name in the LTO plugin. llvm-svn: 315086
* [AMDGPU] New 64 bit div/rem expansionStanislav Mekhanoshin2017-10-061-19/+151
| | | | | | | | | | | Old expansion was 20 VGPRs, 78 SGPRs and ~380 instructions. This expansion is 11 VGPRs, 12 SGPRs and ~120 instructions. Passes OpenCL conformance test_integer_ops quick_[u]long_math Differential Revision: https://reviews.llvm.org/D38607 llvm-svn: 315081
* [MC] Use unique_ptr to manage WinFrameInfos, NFCReid Kleckner2017-10-062-16/+12
| | | | | | | | The FrameInfo cannot be stored directly in the vector because chained frames may refer to parent frames, so we need pointers that are stable across a vector resize. llvm-svn: 315080
* Support: Rewrite Windows implementation of sys::fs::rename to be more POSIXy.Peter Collingbourne2017-10-061-47/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of rename uses ReplaceFile if the destination file already exists. According to the documentation for ReplaceFile, the source file is opened without a sharing mode. This means that there is a short interval of time between when ReplaceFile renames the file and when it closes the file during which the destination file cannot be opened. This behaviour is not POSIX compliant because rename is supposed to be atomic. It was also causing intermittent link failures when linking with a ThinLTO cache; the ThinLTO cache implementation expects all cache files to be openable. This patch addresses that problem by re-implementing rename using CreateFile and SetFileInformationByHandle. It is roughly a reimplementation of ReplaceFile with a better sharing policy as well as support for renaming in the case where the destination file does not exist. This implementation is still not fully POSIX. Specifically in the case where the destination file is open at the point when rename is called, there will be a short interval of time during which the destination file will not exist. It isn't clear whether it is possible to avoid this using the Windows API. Differential Revision: https://reviews.llvm.org/D38570 llvm-svn: 315079
* Directly return promoted direct call instead of rely on stripPointerCast.Dehao Chen2017-10-062-11/+15
| | | | | | | | | | | | | | Summary: stripPointerCast is not reliably returning the value that's being type-casted. Instead it may look further at function attributes to further propagate the value. Instead of relying on stripPOintercast, the more reliable solution is to directly use the pointer to the promoted direct call. Reviewers: tejohnson, davidxl Reviewed By: tejohnson Subscribers: llvm-commits, sanjoy Differential Revision: https://reviews.llvm.org/D38603 llvm-svn: 315077
* [ARM] GlobalISel: Select shiftsDiana Picus2017-10-061-0/+16
| | | | | | | | | Unfortunately TableGen doesn't handle this yet: Unable to deduce gMIR opcode to handle Src (which is a leaf). Just add some temporary hand-written code to generate the proper MOVsr. llvm-svn: 315071
* [ARM] GlobalISel: Map shift operands to GPRsDiana Picus2017-10-061-0/+3
| | | | llvm-svn: 315067
* [llvm-dsymutil] Add support for __swift_ast MachO DWARF sectionFrancis Ricci2017-10-061-0/+4
| | | | | | | | | | | | | | | | | | | | Summary: Xcode's dsymutil emits a __swift_ast DWARF section, which is required for debugging, and which contains a byte-for-byte dump of the swiftmodule file. Add this feature to llvm-dsymutil. Tested with `gobjdump --dwarf=info -s`, by verifying that the contents of `__DWARF.__swift_ast` match between Xcode's dsymutil and llvm-dsymutil (Xcode's dwarfdump and llvm-dwarfdump don't currently recognize the __swift_ast section). Reviewers: aprantl, friss Subscribers: llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D38504 llvm-svn: 315066
* [ARM] GlobalISel: Mark shifts as legal for s32Diana Picus2017-10-061-0/+3
| | | | | | | The new legalize combiner introduces shifts all over the place, so we should support them sooner rather than later. llvm-svn: 315064
* [SystemZ] Enable machine scheduler.Jonas Paulsson2017-10-061-0/+5
| | | | | | | | | | | | | The machine scheduler (before register allocation) is enabled by default for SystemZ. The SelectionDAG scheduling preference now becomes source order scheduling (was regpressure). Review: Ulrich Weigand https://reviews.llvm.org/D37977 llvm-svn: 315063
* Revert "[MergeICmps] Disable mergeicmps if the target does not want to ↵Clement Courbet2017-10-061-36/+12
| | | | | | | | | | handle memcmp expansion." Still a few stability issues on windows. This reverts commit 67e3db9bc121ba244e20337aabc7cf341a62b545. llvm-svn: 315058
* Re-land "[MergeICmps] Disable mergeicmps if the target does not want to ↵Clement Courbet2017-10-061-12/+36
| | | | | | | | | | handle memcmp expansion." (fixed unit tests by making comparisons stable) This reverts commit 1b2d359ce256fd6737da4e93833346a0bd6d7583. llvm-svn: 315056
* Roll forward r314928Xinliang David Li2017-10-062-0/+238
| | | | | | | Fixed ThinLTO bootstrap failure : track new bitcast per incomingVal. Added new tests. llvm-svn: 315044
* [PM] Retire disable unit-at-a-time switch.Davide Italiano2017-10-061-33/+24
| | | | | | | | | | | | This is a vestige from the GCC-3 days, which disables IPO passes when set. I don't think anybody actually uses it as there are several IPO passes which still run with this flag set and nobody complained/noticed. This reduces the delta between current and new pass manager and allows us to easily review the difference when we decide to flip the switch (or audit which passes should run, FWIW). llvm-svn: 315043
* [CodeExtractor] Fix multiple bugs under certain shape of extracted regionJakub Kuderski2017-10-061-77/+31
| | | | | | | | | | | | | | | | Summary: If the extracted region has multiple exported data flows toward the same BB which is not included in the region, correct resotre instructions and PHI nodes won't be generated inside the exitStub. The solution is simply put the restore instructions right after the definition of output values instead of putting in exitStub. Unittest for this bug is included. Author: myhsu Reviewers: chandlerc, davide, lattner, silvas, davidxl, wmi, kuhar Subscribers: dberlin, kuhar, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D37902 llvm-svn: 315041
* NewGVN: Factor out duplicate parts of OpIsSafeForPHIOfOpsDaniel Berlin2017-10-061-45/+31
| | | | llvm-svn: 315040
* Revert "[llvm-dsymutil] Add support for __swift_ast MachO DWARF section"Francis Ricci2017-10-051-4/+0
| | | | | | | | Breaks aarch64 builders This reverts commit r315014. llvm-svn: 315034
* [MBP] Remove an invalid assert.Xin Tong2017-10-051-6/+0
| | | | | | | | | | | | The patch that this assert comes with is fixing a bug in MBP. The assert is invalid however. Thanks to @sergey.k.okunev for finding this Currently this fails SPECCPU2006 LTO. I will add a test case when I do more investigation and have one. llvm-svn: 315032
* ModuleUtils: Stop using comdat members to generate unique module ids.Peter Collingbourne2017-10-051-1/+1
| | | | | | | | | | | It is possible for two modules to define the same set of external symbols without causing a duplicate symbol error at link time, as long as each of the symbols is a comdat member. So we cannot use them as part of a unique id for the module. Differential Revision: https://reviews.llvm.org/D38602 llvm-svn: 315026
* [X86] Extract CATCHRET handling from emitEpilogue, NFCReid Kleckner2017-10-052-33/+42
| | | | llvm-svn: 315023
* [WebAssembly] Add the rest of the atomic loadsDerek Schuff2017-10-054-56/+198
| | | | | | | | | | Add extending loads and constant offset patterns A bit more refactoring of the tablegen to make the patterns fairly nice and uniform between the regular and atomic loads. Differential Revision: https://reviews.llvm.org/D38523 llvm-svn: 315022
* [InstCombine] improve folds for icmp gt/lt (shr X, C1), C2Sanjay Patel2017-10-051-37/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can always eliminate the shift in: icmp gt/lt (shr X, C1), C2 --> icmp gt/lt X, C' This patch was supposed to just be an efficiency improvement because we were doing this 3-step process to fold: IC: Visiting: %c = icmp ugt i4 %s, 1 IC: ADD: %s = lshr i4 %x, 1 IC: ADD: %1 = udiv i4 %x, 2 IC: Old = %c = icmp ugt i4 %1, 1 New = <badref> = icmp uge i4 %x, 4 IC: ADD: %c = icmp uge i4 %x, 4 IC: ERASE %2 = icmp ugt i4 %1, 1 IC: Visiting: %c = icmp uge i4 %x, 4 IC: Old = %c = icmp uge i4 %x, 4 New = <badref> = icmp ugt i4 %x, 3 IC: ADD: %c = icmp ugt i4 %x, 3 IC: ERASE %2 = icmp uge i4 %x, 4 IC: Visiting: %c = icmp ugt i4 %x, 3 IC: DCE: %1 = udiv i4 %x, 2 IC: ERASE %1 = udiv i4 %x, 2 IC: DCE: %s = lshr i4 %x, 1 IC: ERASE %s = lshr i4 %x, 1 IC: Visiting: ret i1 %c When we could go directly to canonical icmp form: IC: Visiting: %c = icmp ugt i4 %s, 1 IC: Old = %c = icmp ugt i4 %s, 1 New = <badref> = icmp ugt i4 %x, 3 IC: ADD: %c = icmp ugt i4 %x, 3 IC: ERASE %1 = icmp ugt i4 %s, 1 IC: ADD: %s = lshr i4 %x, 1 IC: DCE: %s = lshr i4 %x, 1 IC: ERASE %s = lshr i4 %x, 1 IC: Visiting: %c = icmp ugt i4 %x, 3 ...but then I noticed that the folds were incomplete too: https://godbolt.org/g/aB2hLE Here are attempts to prove the logic with Alive: https://rise4fun.com/Alive/92o Name: lshr_ult Pre: ((C2 << C1) u>> C1) == C2 %sh = lshr i8 %x, C1 %r = icmp ult i8 %sh, C2 => %r = icmp ult i8 %x, (C2 << C1) Name: ashr_slt Pre: ((C2 << C1) >> C1) == C2 %sh = ashr i8 %x, C1 %r = icmp slt i8 %sh, C2 => %r = icmp slt i8 %x, (C2 << C1) Name: lshr_ugt Pre: (((C2+1) << C1) u>> C1) == (C2+1) %sh = lshr i8 %x, C1 %r = icmp ugt i8 %sh, C2 => %r = icmp ugt i8 %x, ((C2+1) << C1) - 1 Name: ashr_sgt Pre: (C2 != 127) && ((C2+1) << C1 != -128) && (((C2+1) << C1) >> C1) == (C2+1) %sh = ashr i8 %x, C1 %r = icmp sgt i8 %sh, C2 => %r = icmp sgt i8 %x, ((C2+1) << C1) - 1 Name: ashr_exact_sgt Pre: ((C2 << C1) >> C1) == C2 %sh = ashr exact i8 %x, C1 %r = icmp sgt i8 %sh, C2 => %r = icmp sgt i8 %x, (C2 << C1) Name: ashr_exact_slt Pre: ((C2 << C1) >> C1) == C2 %sh = ashr exact i8 %x, C1 %r = icmp slt i8 %sh, C2 => %r = icmp slt i8 %x, (C2 << C1) Name: lshr_exact_ugt Pre: ((C2 << C1) u>> C1) == C2 %sh = lshr exact i8 %x, C1 %r = icmp ugt i8 %sh, C2 => %r = icmp ugt i8 %x, (C2 << C1) Name: lshr_exact_ult Pre: ((C2 << C1) u>> C1) == C2 %sh = lshr exact i8 %x, C1 %r = icmp ult i8 %sh, C2 => %r = icmp ult i8 %x, (C2 << C1) We did something similar for 'shl' in D28406. Differential Revision: https://reviews.llvm.org/D38514 llvm-svn: 315021
* [Hexagon] Make PS_fi and PS_fia extendable (they both expand to A2_addi)Krzysztof Parzyszek2017-10-051-3/+6
| | | | llvm-svn: 315019
* Annotate VP prof on indirect call if it is ICPed in the profiled binary.Dehao Chen2017-10-051-1/+3
| | | | | | | | | | | | | | Summary: In SamplePGO, when an indirect call is promoted in the profiled binary, before profile annotation, it will be promoted and inlined. For the original indirect call, the current implementation will not mark VP profile on it. This is an issue when profile becomes stale. This patch annotates VP prof on indirect calls during annotation. Reviewers: tejohnson Reviewed By: tejohnson Subscribers: sanjoy, llvm-commits Differential Revision: https://reviews.llvm.org/D38477 llvm-svn: 315016
* [llvm-dsymutil] Add support for __swift_ast MachO DWARF sectionFrancis Ricci2017-10-051-0/+4
| | | | | | | | | | | | | | | | | | | | Summary: Xcode's dsymutil emits a __swift_ast DWARF section, which is required for debugging, and which contains a byte-for-byte dump of the swiftmodule file. Add this feature to llvm-dsymutil. Tested with `gobjdump --dwarf=info -s`, by verifying that the contents of `__DWARF.__swift_ast` match between Xcode's dsymutil and llvm-dsymutil (Xcode's dwarfdump and llvm-dwarfdump don't currently recognize the __swift_ast section). Reviewers: aprantl, friss Subscribers: llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D38504 llvm-svn: 315014
* [Hexagon] Give uniform names to functions changing addressing modes, NFCKrzysztof Parzyszek2017-10-054-56/+81
| | | | | | | | | | | | | | | The new format is changeAddrMode_xx_yy, where xx is the current mode, and yy is the new one. Old name: New name: getBaseWithImmOffset changeAddrMode_abs_io getAbsoluteForm changeAddrMode_io_abs getBaseWithRegOffset changeAddrMode_io_rr xformRegToImmOffset changeAddrMode_rr_io getBaseWithLongOffset changeAddrMode_rr_ur getRegShlForm changeAddrMode_ur_rr llvm-svn: 315013
* Revert "[llvm-dsymutil] Add support for __swift_ast MachO DWARF section"Francis Ricci2017-10-051-4/+0
| | | | | | This reverts commit r315004, because of a failing test on non-apple platforms llvm-svn: 315009
* [llvm-dsymutil] Add support for __swift_ast MachO DWARF sectionFrancis Ricci2017-10-051-0/+4
| | | | | | | | | | | | | | | | | | | | Summary: Xcode's dsymutil emits a __swift_ast DWARF section, which is required for debugging, and which contains a byte-for-byte dump of the swiftmodule file. Add this feature to llvm-dsymutil. Tested with `gobjdump --dwarf=info -s`, by verifying that the contents of `__DWARF.__swift_ast` match between Xcode's dsymutil and llvm-dsymutil (Xcode's dwarfdump and llvm-dwarfdump don't currently recognize the __swift_ast section). Reviewers: aprantl, friss Subscribers: llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D38504 llvm-svn: 315004
* [NewPassManager] Run global dead code elimination after the inliner.Davide Italiano2017-10-051-0/+1
| | | | | | | | | This is the same exact change we did for the current pass manager in rL314997, but the new pass manager pipeline already happened to run GlobalOpt after the inliner, so we just insert a run of GDCE here. llvm-svn: 315003
* [X86] Simplify X86 epilogue frame size calculation, NFCReid Kleckner2017-10-051-39/+28
| | | | | | | | | | | | | | | | | | | | | Sink the insertion of "pop ebp" out of the frame size calculation branches. They all check for HasFP. Our handling of CLEANUPRET and CATCHRET was equivalent, both are funclets and use the same frame size. We can eliminate the CLEANUPRET case. Hoist the hasFP(MF) query into a local bool. Rename TargetMBB to CatchRetTarget to be more descriptive. Eliminate the Optional<unsigned> RetOpcode local, now that it has one use. It's only a net savings of 10 lines, but hopefully it's *slightly* more readable. llvm-svn: 315000
* [PassManager] Improve the interaction between -O2 and ThinLTO.Davide Italiano2017-10-051-13/+11
| | | | | | | Run GDCE slightly later so that we don't have to repeat it twice when preparing for Thin. Thanks to Mehdi for the suggestion. llvm-svn: 314999
* [PassManager] Run global optimizations after the inliner.Davide Italiano2017-10-051-0/+14
| | | | | | | | | | | | | | | The inliner performs some kind of dead code elimination as it goes, but there are cases that are not really caught by it. We might at some point consider teaching the inliner about them, but it is OK for now to run GlobalOpt + GlobalDCE in tandem as their benefits generally outweight the cost, making the whole pipeline faster. This fixes PR34652. Differential Revision: https://reviews.llvm.org/D38154 llvm-svn: 314997
* [SparsePropagation] Move member definitions to header (NFC)Matthew Simpson2017-10-052-365/+0
| | | | | | | | | AbstractLatticeFunction and SparseSolver are class templates parameterized by a lattice value, so we need to move these member functions over to the header. Differential Revision: https://reviews.llvm.org/D38561 llvm-svn: 314996
* [mips] implement .set dspr2 directivePetar Jovanovic2017-10-053-0/+14
| | | | | | | | | | | | Implement .set dspr2 directive with appropriate feature bits. This directive is a counterpart of -mattr=dspr2 command line option with the exception that it does not influence elf header flags. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D38537 llvm-svn: 314994
* AMDGPU: Set v2i32 any_extend to expandMatt Arsenault2017-10-051-0/+1
| | | | llvm-svn: 314993
* [RDF] Simplify construction of maximal registersKrzysztof Parzyszek2017-10-052-40/+12
| | | | | | | | The old algoritm was not correct, although it worked most of the time. Avoid the complex reachability analysis and simply calculate the maximal registers out of the set of all referenced registers. llvm-svn: 314991
* [ProfileData] Fix data racing in merging indexed profilesRong Xu2017-10-051-2/+0
| | | | | | | | | | There is data racing to the static variable RecordIndex in index profile reader when merging in multiple threads. Make it a member variable in IndexedInstrProfReader to fix this. Differential Revision: https://reviews.llvm.org/D38431 llvm-svn: 314990
* [X86] Fix chains update when lowering BUILD_VECTOR to a vector loadArtur Pilipenko2017-10-051-3/+10
| | | | | | | | | | | | | | | | | | The code which lowers BUILD_VECTOR of consecutive loads into a single vector load doesn't update chains properly. As a result the vector load can be reordered with the store to the same location. The current code in EltsFromConsecutiveLoads only updates the chain following the first load. The fix is to update the chains following all the loads comprising the vector. This is a fix for PR10114. Reviewed By: niravd Differential Revision: https://reviews.llvm.org/D38547 llvm-svn: 314988
* AMDGPU: Add and set AMDGPU-specific e_flagsKonstantin Zhuravlyov2017-10-054-18/+39
| | | | | | Differential Revision: https://reviews.llvm.org/D38556 llvm-svn: 314987
* [LV] Fix PR34743 - handle casts that sink after interleaved loadsAyal Zaks2017-10-051-1/+4
| | | | | | | | | | | When ignoring a load that participates in an interleaved group, make sure to move a cast that needs to sink after it. Testcase derived from reproducer of PR34743. Differential Revision: https://reviews.llvm.org/D38338 llvm-svn: 314986
* Revert "Re-land "[MergeICmps] Disable mergeicmps if the target does not want ↵Clement Courbet2017-10-051-25/+10
| | | | | | | | | | to handle memcmp expansion.""" broken test on windows This reverts commit c91479518344fd1fc071c5bd5848f6eb83e53dca. llvm-svn: 314985
* revert r314698 - [InstCombine] remove one-use restriction for icmp (shr ↵Sanjay Patel2017-10-051-6/+6
| | | | | | | | | | | exact X, C1), C2 --> icmp X, (C2<<C1) There is a bot failure that appears to be related to this change: http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15-selfhost-neon/builds/2117 ...so reverting to confirm that and attempting to keep the bot green while investigating. llvm-svn: 314984
* [LV] Fix PR34711 - widen instruction ranges when sinking castsAyal Zaks2017-10-051-23/+22
| | | | | | | | | | | | | | | | Instead of trying to keep LastWidenRecipe updated after creating each recipe, have tryToWiden() retrieve the last recipe of the current VPBasicBlock and check if it's a VPWidenRecipe when attempting to extend its range. This ensures that such extensions, optimized to maintain the original instruction order, do so only when the instructions are to maintain their relative order. The latter does not always hold, e.g., when a cast needs to sink to unravel first order recurrence (r306884). Testcase derived from reproducer of PR34711. Differential Revision: https://reviews.llvm.org/D38339 llvm-svn: 314981
* Re-land "[MergeICmps] Disable mergeicmps if the target does not want to ↵Clement Courbet2017-10-051-10/+25
| | | | | | handle memcmp expansion."" llvm-svn: 314980
* [mips] Place certain 64 bit FPU instructions in their own decoder namespaceSimon Dardis2017-10-054-25/+34
| | | | | | | | | | | Previously, instructions that were defined to use the FGR64 register class were associated with the Mips64 table which was incorrect. Reviewers: nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D38454 llvm-svn: 314976
* [DebugInfo] Insert DEBUG_VALUEs after each register redefinitionKarl-Johan Karlsson2017-10-051-18/+57
| | | | | | | | | | | | | | | | | | | | | | | | Summary: When reinserting debug values after register allocation, make sure to insert debug values after each redefinition of debug value register in the slot index range. The reason for this is that DwarfDebug will end the range of a debug variable when the physical reg is defined. For instructions with e.g. tied operands this result in prematurely ended debug range. This resolves pr34545 Patch by Karl-Johan Karlsson and Bjorn Pettersson Reviewers: rnk, aprantl Reviewed By: rnk Subscribers: bjope, llvm-commits Differential Revision: https://reviews.llvm.org/D38229 llvm-svn: 314974
* [MC] - llvm-mc hangs on non-english characters.George Rimar2017-10-051-1/+1
| | | | | | | | | | | | | | | | | | Currently llvm-mc just hangs inside infinite loop while trying to parse file which has ".section .с" inside, where section name is non-english character. Patch fixes the issue. In this patch I also moved content of non-english-characters.s to test/MC/AsmParser/Inputs folder so that non-english-characters.s becomes a single testcase for all invalid inputs containing non-english symbols. That is convinent because llvm-mc otherwise tries to parse and tokenize the whole testcase file with tools invocations and it is harder to isolate the issue. Differential revision: https://reviews.llvm.org/D38545 llvm-svn: 314973
* Revert "[MergeICmps] Disable mergeicmps if the target does not want to ↵Clement Courbet2017-10-051-15/+6
| | | | | | | | | | | handle memcmp expansion." Breaks clang-stage1-cmake-RA-incremental/llvm/test/Transforms/MergeICmps/X86/tuple-four-int8.ll This reverts commit 3038c459d67f8898ffa295d54a013b280690abfa. llvm-svn: 314972
* [InstCombine] Fix a vector splat handling bug in transformZExtICmp.Craig Topper2017-10-051-3/+1
| | | | | | | | | | We were using an i1 type and then zero extending to a vector. Instead just create the 0/1 directly as a ConstantInt with the correct type. No need to ask ConstantExpr to zero extend for us. This bug is a bit tricky to hit because it requires us to visit a zext of an icmp that would normally be simplified to true/false, but that icmp hasnt' been visited yet. In the test case this zext and icmp were created by visiting a udiv and due to worklist ordering we got to the zext first. Fixes PR34841. llvm-svn: 314971
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