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* Stop relying on physical register kill flags in isKilled() in the two-addressCameron Zwarich2013-02-211-3/+10
| | | | | | | | | | | | | | pass. One of the callers of isKilled() can cope with overapproximation of kills and the other can't, so I added a flag to indicate this. In theory this could pessimize code slightly, but in practice most physical register uses are kills, and most important kills of physical registers are the only uses of that register prior to register allocation, so we can recognize them as kills even without kill flags. This is relevant because LiveIntervals gets rid of all kill flags. llvm-svn: 175821
* Previously, parsing capability of the .debug_frame section was addedEli Bendersky2013-02-212-6/+171
| | | | | | | | | | | | | | | | to lib/DebugInfo, with dumping in llvm-dwarfdump. This patch adds initial ability to parse and dump CFA instructions contained in entries. To keep it manageable, the patch omits some more advanced capabilities (accounted in TODOs): * Parsing of instructions with BLOCK arguments (expression lists) * Dumping of actual instruction arguments (currently only names are dumped). This is quite tricky since the dumper has to effectively "interpret" the instructions. llvm-svn: 175820
* Allow GlobalValues to vectorize with AliasAnalysisRenato Golin2013-02-211-35/+154
| | | | | | | | | | | | | | | | | | | | | Storing the load/store instructions with the values and inspect them using Alias Analysis to make sure they don't alias, since the GEP pointer operand doesn't take the offset into account. Trying hard to not add any extra cost to loads and stores that don't overlap on global values, AA is *only* calculated if all of the previous attempts failed. Using biggest vector register size as the stride for the vectorization access, as we're being conservative and the cost model (which calculates the real vectorization factor) is only run after the legalization phase. We might re-think this relationship in the future, but for now, I'd rather be safe than sorry. llvm-svn: 175818
* Re-apply r175688, with the changes suggested by Jakob in PR15320.Lang Hames2013-02-211-24/+15
| | | | llvm-svn: 175809
* Remove dead code and whitespace.Chad Rosier2013-02-211-10/+0
| | | | llvm-svn: 175804
* Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky2013-02-2154-572/+543
| | | | | | | | | | | | | | | to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. llvm-svn: 175788
* Don't assert on empty attributes.Bill Wendling2013-02-211-2/+2
| | | | llvm-svn: 175785
* Hexagon: Expand cttz, ctlz, and ctpop for now.Anshuman Dasgupta2013-02-211-0/+5
| | | | llvm-svn: 175783
* Make RAFast::UsedInInstr indexed by register units.Jakob Stoklund Olesen2013-02-211-22/+30
| | | | | | | | | | This fixes some problems with too conservative checking where we were marking all aliases of a register as used, and then also checking all aliases when allocating a register. <rdar://problem/13249625> llvm-svn: 175782
* Radar numbers don't belong in source code.Evan Cheng2013-02-213-4/+1
| | | | llvm-svn: 175775
* Trivial cleanupBill Schmidt2013-02-211-2/+2
| | | | llvm-svn: 175771
* Large code model support for PowerPC.Bill Schmidt2013-02-215-15/+20
| | | | | | | | | | | Large code model is identical to medium code model except that the addis/addi sequence for "local" accesses is never used. All accesses use the addis/ld sequence. The coding changes are straightforward; most of the patch is taken up with creating variants of the medium model tests for large model. llvm-svn: 175767
* Revert r175688 - It broke a test case (see PR15320).Lang Hames2013-02-211-13/+25
| | | | llvm-svn: 175765
* getX86SubSuperRegister has a special mode with High=true for i64 whichEli Bendersky2013-02-211-17/+9
| | | | | | | | | | exists solely to enable it to call itself for i8 with some registers. The proposed patch simplifies the function somewhat to make the High bit only meaningful for the i8 mode, which makes sense. No functional difference (getX86SubSuperRegister is not getting called from anywhere outside with i64 and High=true). llvm-svn: 175762
* DAGCombiner: Make the post-legalize vector op optimization more aggressive.Benjamin Kramer2013-02-211-10/+0
| | | | | | | | A legal BUILD_VECTOR goes in and gets constant folded into another legal BUILD_VECTOR so we don't lose any legality here. The problematic PPC optimization that made this check necessary was fixed recently. llvm-svn: 175759
* R600/SI: inline V_ADD|SUB_F32 patternsChristian Konig2013-02-211-9/+5
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175758
* R600/SI: replace IMPLICIT_DEF with SIOperand.ZEROChristian Konig2013-02-211-1/+1
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175757
* R600/SI: replace SI_V_CNDLT with a patternChristian Konig2013-02-213-31/+5
| | | | | | | | | | | It actually fixes quite a bunch of piglit tests. This is a candidate for the mesa-stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175756
* R600/SI: use patterns for clamp, fabs, fnegChristian Konig2013-02-212-40/+22
| | | | | | | | | | Instead of using custom inserters, it's simpler and should make DAG folding easier. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175755
* R600/SI: add all the other missing asm operands v2Christian Konig2013-02-212-22/+29
| | | | | | | | | v2: put implicit parameters in [] Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175754
* R600/SI: add the missing M*BUF|IMG asm operandsChristian Konig2013-02-211-4/+8
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175753
* R600/SI: add the missing S_* asm operandsChristian Konig2013-02-211-18/+34
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175752
* R600/SI: rework VOP3 classesChristian Konig2013-02-211-14/+14
| | | | | | | | | Order the classes and add asm operands. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175751
* R600/SI: simplify VOPC_* pattern v2Christian Konig2013-02-213-255/+217
| | | | | | | | | | | Fixing asm operation names. v2: fix name of the e64 encoding, also add asm operands Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175750
* R600/SI: rework VOP2_* pattern v2Christian Konig2013-02-212-21/+19
| | | | | | | | | | | Fixing asm operation names. v2: use ZERO constant, also add asm operands Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175749
* R600/SI: rework VOP1_* patterns v2Christian Konig2013-02-211-17/+21
| | | | | | | | | | | Fixing asm operation names. v2: use ZERO constant, also add asm operands Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175748
* R600/SI: add constant for inline zero operandChristian Konig2013-02-211-4/+3
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175747
* R600/SI: cleanup SIInstrInfo.td and SIInstrFormat.tdChristian Konig2013-02-212-488/+527
| | | | | | | | | Those two files got mixed up. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175746
* R600: Fix for Unigine when MachineSched is enabledTom Stellard2013-02-211-0/+1
| | | | | | | | | | | Fixes for-loop.cl piglit test Patch By: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175742
* Code review cleanup for r175697Bill Schmidt2013-02-211-11/+7
| | | | llvm-svn: 175739
* R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32Michel Danzer2013-02-211-1/+2
| | | | | | | NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175733
* Don't rely on the isDead() MachineOperand flag when updating LiveIntervals.Cameron Zwarich2013-02-211-1/+3
| | | | llvm-svn: 175732
* Use getInterval() instead of getOrCreateInterval().Cameron Zwarich2013-02-211-1/+1
| | | | llvm-svn: 175731
* Make another kill check LiveIntervals-aware.Cameron Zwarich2013-02-211-1/+1
| | | | | | | This brings the number of remaining failures in 'make check' without LiveVariables down to 39, with 1 unexpectedly passing test. llvm-svn: 175727
* Split part of isKilled() into a separate function for use elsewhere.Cameron Zwarich2013-02-211-22/+28
| | | | llvm-svn: 175726
* Update isKilledAt in TwoAddressInstructionPass.cpp to use LiveIntervals whenCameron Zwarich2013-02-211-4/+26
| | | | | | | | | | available. With this commit there are no longer any assertion or verifier failures when running 'make check' without LiveVariables. There are still 56 failing tests with codegen differences and 1 unexpectedly passing test. llvm-svn: 175719
* Expand the sel pseudo/macro. This generates basic blocks where previouslyReed Kotler2013-02-213-1/+97
| | | | | | | there were inline br .+4 instructions. Soon everything can enjoy the full instruction scheduling experience. llvm-svn: 175718
* Mips specific standalone assembler addressing mode %hi and %lo.Jack Carter2013-02-211-0/+5
| | | | | | | | | | | | The constructs %hi() and %lo() represent the high and low 16 bits of the address. Because the 16 bit offset field of an LW instruction is interpreted as signed, if bit 15 of the low part is 1 then the low part will act as a negative and 1 needs to be added to the high part. Contributer: Vladimir Medic llvm-svn: 175707
* PPCDAGToDAGISel::PostprocessISelDAG()Bill Schmidt2013-02-211-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements the PPCDAGToDAGISel::PostprocessISelDAG virtual method to perform post-selection peephole optimizations on the DAG representation. One optimization is implemented here: folds to clean up complex addressing expressions for thread-local storage and medium code model. It will also be useful for large code model sequences when those are added later. I originally thought about doing this on the MI representation prior to register assignment, but it's difficult to do effective global dead code elimination at that point. DCE is trivial on the DAG representation. A typical example of a candidate code sequence in assembly: addis 3, 2, globalvar@toc@ha addi 3, 3, globalvar@toc@l lwz 5, 0(3) When the final instruction is a load or store with an immediate offset of zero, the offset from the add-immediate can replace the zero, provided the relocation information is carried along: addis 3, 2, globalvar@toc@ha lwz 5, globalvar@toc@l(3) Since the addi can in general have multiple uses, we need to only delete the instruction when the last use is removed. llvm-svn: 175697
* Provide a "None" value for convenience when using Optional<T>()David Blaikie2013-02-211-2/+2
| | | | | | | This implementation of NoneType/None does have some holes but I haven't found one that doesn't - open to improvement. llvm-svn: 175696
* Relocation enablement for PPC DAG postprocessing passBill Schmidt2013-02-214-11/+37
| | | | llvm-svn: 175693
* Formatting.Chad Rosier2013-02-201-2/+1
| | | | llvm-svn: 175692
* Don't allocate memory in LiveInterval::join().Jakob Stoklund Olesen2013-02-201-10/+7
| | | | | | | Rewrite value numbers directly in the 'Other' LiveInterval which is moribund anyway. This avoids allocating the OtherAssignments vector. llvm-svn: 175690
* Kill of TransferDeadFlag - Dead copies and subreg-to-reg instructions shouldLang Hames2013-02-201-25/+13
| | | | | | just be turned into kills on the spot. llvm-svn: 175688
* as the allocator is reset zero out the number of bytes allocated, this was justPedro Artigas2013-02-201-0/+1
| | | | | | missed before but probably what was intended. llvm-svn: 175687
* ELF symbol table field st_other support, Jack Carter2013-02-201-85/+84
| | | | | | | | | | | | | | | | | | | | excluding visibility bits. Mips specific standalone assembler directive "set at". This directive changes the general purpose register that the assembler will use when given the symbolic register name $at. This does not include negative testing. That will come in a future patch. A side affect of this patch recognizes the different GPR register names for temporaries between old abi and new abi so a test case for that is included. Contributer: Vladimir Medic llvm-svn: 175686
* Copy single reaching defs directly into the LiveInterval.Jakob Stoklund Olesen2013-02-202-47/+76
| | | | | | | | | | | | | | | | | | When findReachingDefs() finds that only one value can reach the basic block, just copy the work list of visited blocks directly into the live interval. Sort the block list and use a LiveRangeUpdater to make the bulk add fast. When multiple reaching defs are found, transfer the work list to the updateSSA() work list as before. Also use LiveRangeUpdater in updateLiveIns() following updateSSA(). This makes live interval analysis more than 3x faster on one huge test case. llvm-svn: 175685
* Add and remove the attribute from the correct slot.Bill Wendling2013-02-201-2/+12
| | | | | | | | | The slot that we're adding/removing the attribute from may not be the same as the attribute coming in. Make sure that they match up before we try to add/remove them. PR15313 llvm-svn: 175684
* Fix accidental concatenation for "outputuntil" in the -debug-buffer-size ↵Erik Verbruggen2013-02-201-1/+1
| | | | | | option description. llvm-svn: 175682
* MCParser: Update method names per coding guidelines.Jim Grosbach2013-02-2010-344/+344
| | | | | | | | | | | | | | | | | | | s/AddDirectiveHandler/addDirectiveHandler/ s/ParseMSInlineAsm/parseMSInlineAsm/ s/ParseIdentifier/parseIdentifier/ s/ParseStringToEndOfStatement/parseStringToEndOfStatement/ s/ParseEscapedString/parseEscapedString/ s/EatToEndOfStatement/eatToEndOfStatement/ s/ParseExpression/parseExpression/ s/ParseParenExpression/parseParenExpression/ s/ParseAbsoluteExpression/parseAbsoluteExpression/ s/CheckForValidSection/checkForValidSection/ http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly No functional change intended. llvm-svn: 175675
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