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* Remove the AsmWriterEmitter (unused) feature that rely on TargetSubtargetInfo.Evan Cheng2011-07-062-5/+0
| | | | llvm-svn: 134457
* Remove the ObjC ARC passes from the default optimization list, and addDan Gohman2011-07-051-4/+0
| | | | | | extension points to be used by clang. llvm-svn: 134444
* Preserve debug loc.Devang Patel2011-07-052-2/+2
| | | | llvm-svn: 134441
* Use memcmp.Benjamin Kramer2011-07-051-3/+1
| | | | llvm-svn: 134439
* Really fix typo :-(Rafael Espindola2011-07-051-1/+1
| | | | llvm-svn: 134436
* Fix typo.Rafael Espindola2011-07-051-2/+2
| | | | llvm-svn: 134433
* By default mkstemp() creates a temporary file with mode 0600, but the modeChad Rosier2011-07-051-0/+3
| | | | | | | | used for open is 0666. Therefore, add the necessary permission bits for consistency. rdar://8621462 llvm-svn: 134430
* Break infinite loop when the Hopfield network oscillates.Jakob Stoklund Olesen2011-07-051-8/+6
| | | | | | | | | | This is impossible in theory, I can prove it. In practice, our near-zero threshold can cause the network to oscillate between equally good solutions. <rdar://problem/9720596> llvm-svn: 134428
* Compare all 4 bytes of the header.Rafael Espindola2011-07-051-2/+3
| | | | llvm-svn: 134427
* Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, ↵Eli Friedman2011-07-053-35/+42
| | | | | | use proper aliases for the pclmullqlqdq and friends. PR10269. llvm-svn: 134424
* indvars -disable-iv-rewrite: avoid multiple IVs in weird cases.Andrew Trick2011-07-051-18/+30
| | | | | | Putting back the helper that I removed on 7/1 to do this right. llvm-svn: 134423
* ARM estimateStackSize() needs to account for simplified call frames.Jim Grosbach2011-07-051-7/+39
| | | | | | | | | | | | If the function allocates reserved stack space for callee argument frames, estimateStackSize() needs to account for that, as it doesn't show up as ordinary frame objects. Otherwise, a callee with a large argument list will throw off the calculations for whether to allocate an emergency spill slot and we get assert() failures in the register scavenger. rdar://9715469 llvm-svn: 134415
* Fix PR10277.Jakob Stoklund Olesen2011-07-052-0/+7
| | | | | | | | | | | | | | | Remat during spilling triggers dead code elimination. If a phi-def becomes unused, that may also cause live ranges to split into separate connected components. This type of splitting is different from normal live range splitting. In particular, there may not be a common original interval. When the split range is its own original, make sure that the new siblings are also their own originals. The range being split cannot be used as an original since it doesn't cover the new siblings. llvm-svn: 134413
* Tweak comment and debug output.Jakob Stoklund Olesen2011-07-051-2/+3
| | | | llvm-svn: 134412
* Fix warnings.Michael J. Spencer2011-07-051-3/+3
| | | | llvm-svn: 134408
* PR10267: Don't combine an equality compare with an AND into an inequality ↵Benjamin Kramer2011-07-041-1/+5
| | | | | | | | compare when the AND has more than one use. This can pessimize code, inequalities are generally more expensive. llvm-svn: 134379
* Remove accidentaly left node from previous iteration of the patch.Roman Divacky2011-07-041-3/+0
| | | | | | Noticed by Benjamin Kramer! llvm-svn: 134376
* Move early tail duplication earlier.Rafael Espindola2011-07-041-6/+6
| | | | | | | | | | | | | | This fixes the issue noted in PR10251 where early tail dup of bbs with indirectbr would cause a bb to be duplicated into a loop preheader and then into its predecessors, creating phi nodes with identical operands just before register allocation. This helps with jsinterp.o size (__TEXT goes from 163568 to 126656) and a bit with performance 1.005x faster on sunspider (jits still enabled). The result on webkit with the jit disabled is more significant: 1.021x faster. llvm-svn: 134372
* Move most of the pre BB code to TailDuplicateAndUpdate. Change theRafael Espindola2011-07-041-112/+125
| | | | | | HasIndirectbr variable to be just that. No functionality change. llvm-svn: 134371
* Reduce indentation and fix the count of how many PHIs we have inserted.Rafael Espindola2011-07-041-75/+80
| | | | llvm-svn: 134370
* Fix PR10244.Jakob Stoklund Olesen2011-07-041-4/+4
| | | | | | | | | | | | A split point inserted in a block with a landing pad successor may be hoisted above the call to ensure that it dominates all successors. The code that handles the rest of the basic block must take this into account. I am not including a test case, it would be very fragile. PR10244 comes from building clang with exceptions enabled. llvm-svn: 134369
* Make the i64 and f64 be 64bit ABI aligned in the target description.Roman Divacky2011-07-031-1/+1
| | | | | | This is what both the ABI and clang says. llvm-svn: 134367
* Fix an easy fixme.Rafael Espindola2011-07-031-6/+10
| | | | llvm-svn: 134364
* Remove unused array.Duncan Sands2011-07-021-21/+0
| | | | llvm-svn: 134323
* Revert previous commit. It seems that whether casting to voidDuncan Sands2011-07-021-1/+1
| | | | | | is valid or not depends on which system you build. llvm-svn: 134321
* Supress gcc-4.5 warning about the result not being used.Duncan Sands2011-07-021-1/+1
| | | | llvm-svn: 134319
* Use getVNInfoAt.Rafael Espindola2011-07-021-2/+1
| | | | llvm-svn: 134312
* Consistent diagnostic capitalization and redundant context elimination.Jakob Stoklund Olesen2011-07-021-8/+5
| | | | llvm-svn: 134311
* Better diagnostics when inline asm fails to allocate.Jakob Stoklund Olesen2011-07-022-22/+18
| | | | | | | | asm.c:2:7: error: ran out of registers during register allocation asm(""::"r"(0), "r"(1), "r"(2), "r"(3), "r"(4), "r"(5), "r"(6), "r"(7), "r"(8), "r"(9)); ^ llvm-svn: 134310
* Check the VN of the src register at the two copies, not just theRafael Espindola2011-07-021-1/+6
| | | | | | register number. llvm-svn: 134309
* Include a source location when complaining about bad inline assembly.Jakob Stoklund Olesen2011-07-022-10/+36
| | | | | | | | | | | | | | | | Add a MI->emitError() method that the backend can use to report errors related to inline assembly. Call it from X86FloatingPoint.cpp when the constraints are wrong. This enables proper clang diagnostics from the backend: $ clang -c pr30848.c pr30848.c:5:12: error: Inline asm output regs must be last on the x87 stack __asm__ ("" : "=u" (d)); /* { dg-error "output regs" } */ ^ 1 error generated. llvm-svn: 134307
* indvars -disable-iv-rewrite: bug fix involving weird geps and related cleanup.Andrew Trick2011-07-021-46/+51
| | | | llvm-svn: 134306
* Use a new strategy for preventing eviction loops in RAGreedy.Jakob Stoklund Olesen2011-07-021-57/+74
| | | | | | | | | | | | | | | | | | | Every live range is assigned a cascade number the first time it is involved in an eviction. As the evictor, it gets a new cascade number. Every evictee is assigned the same cascade number as the evictor. Eviction is prohibited if the evictor has a lower assigned cascade number than the evictee. This means that assigned cascade numbers are monotonically increasing with every eviction, yet they are bounded by NextCascade which can only be incremented by new live ranges. Thus, infinite loops cannot happen, but eviction cascades can still be triggered by new live ranges as we want. Thanks to Andy for explaining this to me. llvm-svn: 134303
* Add getFeatureBits to extract feature bits for a given CPU.Evan Cheng2011-07-021-0/+8
| | | | llvm-svn: 134298
* Take a stab at fixing the llvm-x86_64-linux-checks failure.Cameron Zwarich2011-07-011-0/+2
| | | | llvm-svn: 134287
* TargetConstant immediates won't be placed into registers so tightenEric Christopher2011-07-011-3/+4
| | | | | | | | up the valid constant check earlier. rdar://9692967 llvm-svn: 134286
* Add initial *-*-rtems* target, from Joel SherrillDouglas Gregor2011-07-011-0/+1
| | | | llvm-svn: 134282
* Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng2011-07-0153-58/+55
| | | | llvm-svn: 134281
* Add MCSubtargetInfo target registry stuff.Evan Cheng2011-07-011-0/+28
| | | | llvm-svn: 134279
* Teach IVUsers to stop at non-affine expressions unless they are bothDan Gohman2011-07-011-7/+10
| | | | | | | | | | | | | | | | | outside the loop and reducible. This more completely hides them from LSR, which isn't usually able to do anything meaningful with non-affine expressions anyway, and this consequently hides them from SCEVExpander, which is acutely unprepared for non-affine expressions. Replace test/CodeGen/X86/lsr-nonaffine.ll with a new test that tests the new behavior. This works around the bug in PR10117 / rdar://problem/9633149, and is generally an improvement besides. llvm-svn: 134268
* Generalize @llvm.ctlz, @llvm.cttz, and @llvm.ctpop to work on vectors of ↵Owen Anderson2011-07-011-2/+6
| | | | | | integers, and fix the one optimization pass that I'm aware of that needs updating for this. At least one current target, ARM NEON, can implement these operations on vectors directly. llvm-svn: 134265
* Calling-convention specifications for illegal types are no-ops. Simplify ↵Eli Friedman2011-07-011-30/+11
| | | | | | based on this. llvm-svn: 134264
* ARMv7M vs. ARMv7E-M support.Jim Grosbach2011-07-016-49/+114
| | | | | | | | | | | | | | The DSP instructions in the Thumb2 instruction set are an optional extension in the Cortex-M* archtitecture. When present, the implementation is considered an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation." Add a subtarget feature hook for the v7e-m instructions and hook it up. The cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is a v7e-m implementation. rdar://9572992 llvm-svn: 134261
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-0133-76/+77
| | | | llvm-svn: 134259
* - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-0128-28/+201
| | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. llvm-svn: 134257
* Fix off-by-one error.Jim Grosbach2011-07-011-1/+1
| | | | | | (low two bits always zero, so off by one bit of encoded value). llvm-svn: 134247
* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-0127-51/+85
| | | | llvm-svn: 134244
* Pseudo-ize t2MOVCC[ri].Jim Grosbach2011-07-014-55/+18
| | | | | | | | t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them. The Thumb1 versions, tMOVCC[ri] were only present for use by the size- reduction pass, so they're no longer necessary at all and can be deleted. llvm-svn: 134242
* Eliminate one extra conversion.Evan Cheng2011-07-011-1/+1
| | | | llvm-svn: 134240
* Disable commit 134216 ("Add 134199 back, but disable the optimization when ↵Duncan Sands2011-07-011-0/+1
| | | | | | | | | the second copy is a kill") to see if it fixes the i386 dragonegg buildbot, which is timing out because gcc built with dragonegg is going into an infinite loop. llvm-svn: 134237
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