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* switch off of 'Section' onto MCSection. We're not properly usingChris Lattner2009-07-3116-117/+128
| | | | | | MCSection subclasses yet, but this is a step in the right direction. llvm-svn: 77708
* Remove Annotation.h, which is no longer used in the LLVM tree.Dan Gohman2009-07-311-130/+0
| | | | llvm-svn: 77706
* Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .alignEvan Cheng2009-07-311-0/+7
| | | | | | | | to ensure the instruction that follows a TBB (when the number of table entries is odd) is 2-byte aligned. Patch by Sandeep Patel. llvm-svn: 77705
* MachineFunction no longer needs Annotation.Dan Gohman2009-07-311-2/+1
| | | | llvm-svn: 77704
* - Teach TBB / TBH offset limits are 510 and 131070 respectively since the offsetEvan Cheng2009-07-312-9/+14
| | | | | | | is scaled by two. - Teach GetInstSizeInBytes about TBB and TBH. llvm-svn: 77701
* Fix printing of Alloca instructions with null operands.Dan Gohman2009-07-311-1/+1
| | | | llvm-svn: 77697
* Fix some problems with ASTCallbackVH in its use as a DenseMap key.Dan Gohman2009-07-311-4/+6
| | | | llvm-svn: 77696
* Process DbgDeclareInst.Devang Patel2009-07-311-0/+15
| | | | llvm-svn: 77694
* Normalize target registration code.Daniel Dunbar2009-07-311-1/+1
| | | | llvm-svn: 77692
* Reapply r77654 with a fix: MachineFunctionPass's getAnalysisUsageDan Gohman2009-07-3111-104/+121
| | | | | | | | shouldn't do AU.setPreservesCFG(), because even though CodeGen passes don't modify the LLVM IR CFG, they may modify the MachineFunction CFG, and passes like MachineLoop are registered with isCFGOnly set to true. llvm-svn: 77691
* refactor section construction in TLOF to be through an explicitChris Lattner2009-07-317-10/+24
| | | | | | initialize method, which can be called when an MCContext is available. llvm-svn: 77687
* Move getTrue() and getFalse() to 2.5-like APIs.Owen Anderson2009-07-3114-160/+154
| | | | llvm-svn: 77685
* split MCSection stuff out to its own .cpp file, add a newChris Lattner2009-07-313-12/+32
| | | | | | MCSectionWithKind subclass of MCSection. llvm-svn: 77684
* create sections with MCSection::Create instead of Context->getOrCreateSection.Chris Lattner2009-07-311-8/+15
| | | | | | This is needed to allow polymorphic sections. llvm-svn: 77680
* fix PR4650: we only track sizes for certain objects, so only put somethingChris Lattner2009-07-311-1/+4
| | | | | | | | into the mergable section if it is one of our special cases. This could obviously be improved, but this is the minimal fix and restores us to the previous behavior. llvm-svn: 77679
* Work around a dangling pointer dereference when enumerating NamedMDNodes.Benjamin Kramer2009-07-311-0/+3
| | | | llvm-svn: 77675
* Fix a struct/class mismatch, to silence a MSVC warning.Benjamin Kramer2009-07-311-1/+1
| | | | llvm-svn: 77673
* define target names for std libcalls.Sanjiv Gupta2009-07-312-12/+34
| | | | llvm-svn: 77667
* Revert r77654, it appears to be causing llvm-gcc bootstrap failures, and manyDaniel Dunbar2009-07-3111-119/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | failures when building assorted projects with clang. --- Reverse-merging r77654 into '.': U include/llvm/CodeGen/Passes.h U include/llvm/CodeGen/MachineFunctionPass.h U include/llvm/CodeGen/MachineFunction.h U include/llvm/CodeGen/LazyLiveness.h U include/llvm/CodeGen/SelectionDAGISel.h D include/llvm/CodeGen/MachineFunctionAnalysis.h U include/llvm/Function.h U lib/Target/CellSPU/SPUISelDAGToDAG.cpp U lib/Target/PowerPC/PPCISelDAGToDAG.cpp U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/MachineVerifier.cpp U lib/CodeGen/MachineFunction.cpp U lib/CodeGen/PrologEpilogInserter.cpp U lib/CodeGen/MachineLoopInfo.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp D lib/CodeGen/MachineFunctionAnalysis.cpp D lib/CodeGen/MachineFunctionPass.cpp U lib/CodeGen/LiveVariables.cpp llvm-svn: 77661
* llvm-mc: Match a few X86 instructions.Daniel Dunbar2009-07-311-8/+71
| | | | | | | | | | | - This is "experimental" code, I am feeling my way around and working out the best way to do things (and learning tblgen in the process). Comments welcome, but keep in mind this stuff will change radically. - This is enough to match "subb" and friends, but not much else. The next step is to automatically generate the matchers for individual operands. llvm-svn: 77657
* Manage MachineFunctions with an analysis Pass instead of the AnnotableDan Gohman2009-07-3111-104/+119
| | | | | | | mechanism. To support this, make MachineFunctionPass a little more complete. llvm-svn: 77654
* Fix cmake build.Benjamin Kramer2009-07-311-1/+0
| | | | llvm-svn: 77649
* Add getOrInsertNamedMetadata().Devang Patel2009-07-301-3/+14
| | | | llvm-svn: 77646
* When fp is not eliminated, instructions with T2_i12 modes will be changed to ↵Evan Cheng2009-07-302-3/+10
| | | | | | T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. llvm-svn: 77642
* Removed the BigBlock register allocator.Lang Hames2009-07-301-892/+0
| | | | llvm-svn: 77640
* Do not use abbrev while writing NamedMDNode name.Devang Patel2009-07-301-9/+4
| | | | llvm-svn: 77637
* Enumerate NamedMDNode elements first.Devang Patel2009-07-301-4/+0
| | | | llvm-svn: 77636
* Move more code back to 2.5 APIs.Owen Anderson2009-07-3041-221/+180
| | | | llvm-svn: 77635
* Remove redundant match for frame index from imm8 addrmode, it is handled by ↵David Goodwin2009-07-301-24/+14
| | | | | | the imm12 addrmode. llvm-svn: 77632
* Darwin assembler now recognizes "orn", so remove workaround.David Goodwin2009-07-301-5/+3
| | | | llvm-svn: 77627
* Darwin assembler now supports "rrx", so remove workaround.David Goodwin2009-07-301-2/+1
| | | | llvm-svn: 77625
* Twine: Directly support int, long, and long long types.Daniel Dunbar2009-07-301-17/+29
| | | | | | - This should resolve Cygwin gcc ambiguities. llvm-svn: 77624
* Use CallbackVH in AliasSetTracker to avoid getting stuck withDan Gohman2009-07-301-4/+20
| | | | | | dangling Value*s. llvm-svn: 77623
* Cleanup and include code selection for some frame index cases.David Goodwin2009-07-301-20/+49
| | | | llvm-svn: 77622
* Start using DebugInfoFinder.Devang Patel2009-07-301-13/+11
| | | | llvm-svn: 77621
* Do not use getNamedValue() to lookup NamedMDNode. NamedMDNode is not a ↵Devang Patel2009-07-301-1/+1
| | | | | | | | GlobalValue. Thanks Benjamin Kramer! llvm-svn: 77619
* Twine: Use raw_ostream::write_hex, remove unused itohexstr method.Daniel Dunbar2009-07-301-2/+1
| | | | llvm-svn: 77617
* s/DebugInfoEnumerator/DebugInfoFinder/gDevang Patel2009-07-301-31/+31
| | | | llvm-svn: 77615
* Add raw_ostream::write_hexDaniel Dunbar2009-07-301-4/+7
| | | | llvm-svn: 77614
* Add missing D* register clobbers for Thumb-2 call.David Goodwin2009-07-301-0/+1
| | | | llvm-svn: 77611
* Twines: Don't allow implicit conversion from integers, this is too tricky.Daniel Dunbar2009-07-304-13/+13
| | | | llvm-svn: 77605
* walk DbgRegionStartInst and DbgRegionEndInstDevang Patel2009-07-301-2/+20
| | | | llvm-svn: 77604
* Minor whitespace tidiness.Dan Gohman2009-07-301-3/+0
| | | | llvm-svn: 77602
* Rename GRAD to GR32_AD, to follow the naming convention of otherDan Gohman2009-07-302-2/+4
| | | | | | classes. And define its SubRegClassList. llvm-svn: 77601
* add a random codegen deficiency.Chris Lattner2009-07-301-0/+46
| | | | llvm-svn: 77598
* fix a unitialized pointer in NamedMDNode (and reenable unittest)Benjamin Kramer2009-07-301-1/+1
| | | | llvm-svn: 77597
* Allow targets to define libcall names for mem(cpy,set,move) intrinsics, ↵Sanjiv Gupta2009-07-302-3/+9
| | | | | | rather than hardcoding them in DAG lowering. llvm-svn: 77586
* Add a note.Evan Cheng2009-07-301-0/+20
| | | | llvm-svn: 77584
* Optimize some common usage patterns of atomic built-ins ↵Evan Cheng2009-07-306-14/+281
| | | | | | | | | | | | __sync_add_and_fetch() and __sync_sub_and_fetch. When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix. This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection. Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix. llvm-svn: 77582
* Switch obvious clients to Twine instead of utostr (when they were already usingDaniel Dunbar2009-07-305-20/+15
| | | | | | | | | a Twine, e.g., for names). - I am a little ambivalent about this; we don't want the string conversion of utostr, but using overload '+' mixed with string and integer arguments is sketchy. On the other hand, this particular usage is something of an idiom. llvm-svn: 77579
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