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* [coroutines] Part 4[ab]: Coroutine Devirtualization: Lower coro.resume and ↵David Majnemer2016-08-045-6/+225
| | | | | | | | | | | | | | | | coro.destroy. This is the forth patch in the coroutine series. CoroEaly pass now lowers coro.resume and coro.destroy intrinsics by replacing them with an indirect call to an address returned by coro.subfn.addr intrinsic. This is done so that CGPassManager recognizes devirtualization when CoroElide replaces a call to coro.subfn.addr with an appropriate function address. Patch by Gor Nishanov! Differential Revision: https://reviews.llvm.org/D22998 llvm-svn: 277765
* [InstCombine] use m_APInt to allow icmp eq (and X, C1), C2 folds for splat ↵Sanjay Patel2016-08-041-14/+9
| | | | | | constant vectors llvm-svn: 277762
* [OpenCL] Add missing tests for getOCLTypeNameYaxun Liu2016-08-041-1/+1
| | | | | | | | | | Adding missing tests for OCL type names for half, float, double, char, short, long, and unknown. Patch by Aaron En Ye Shi. Differential Revision: https://reviews.llvm.org/D22964 llvm-svn: 277759
* [CodeView] Use llvm::Error instead of std::error_code.Zachary Turner2016-08-043-103/+126
| | | | | | | This eliminates the remnants of std::error_code from the DebugInfo libraries. llvm-svn: 277758
* AArch64: don't assume all i128s are BUILD_PAIRsTim Northover2016-08-041-6/+13
| | | | | | | It leads to a crash when they're not. I'm *sure* I've made this mistake before, at least once. llvm-svn: 277755
* [InstCombine] use m_APInt to allow icmp eq (or X, C1), C2 folds for splat ↵Sanjay Patel2016-08-041-9/+7
| | | | | | constant vectors llvm-svn: 277752
* GlobalISel: also add G_TRUNC to IRTranslator.Tim Northover2016-08-041-1/+3
| | | | llvm-svn: 277749
* GlobalISel: add code to widen scalar G_ADDTim Northover2016-08-043-1/+39
| | | | llvm-svn: 277747
* [WebAssembly] Check return value of getRegForValue in FastISelDerek Schuff2016-08-041-0/+13
| | | | | | | | | | | | Previously, FastISel for WebAssembly wasn't checking the return value of `getRegForValue` in certain cases, which would generate instructions referencing NoReg. This patch fixes this behavior. Patch by Dominic Chen Differential Revision: https://reviews.llvm.org/D23100 llvm-svn: 277742
* [Hexagon] Validate register class when doing bit simplificationKrzysztof Parzyszek2016-08-041-10/+33
| | | | llvm-svn: 277740
* [InstCombine] use m_APInt to allow icmp eq (op X, Y), C folds for splat ↵Sanjay Patel2016-08-042-18/+6
| | | | | | | | | constant vectors I'm removing a misplaced pair of more specific folds from InstCombine in this patch as well, so we know where those folds are happening in InstSimplify. llvm-svn: 277738
* [X86][SSE] Rename target shuffle unary permute matching function. NFCI.Simon Pilgrim2016-08-041-6/+6
| | | | | | In preparation for adding a binary permute matching function. llvm-svn: 277737
* LoadStoreVectorizer: Remove TargetBaseAlign. Keep alignment for stack ↵Alina Sbirlea2016-08-043-14/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | adjustments. Summary: TargetBaseAlign is no longer required since LSV checks if target allows misaligned accesses. A constant defining a base alignment is still needed for stack accesses where alignment can be adjusted. Previous patch (D22936) was reverted because tests were failing. This patch also fixes the cause of those failures: - x86 failing tests either did not have the right target, or the right alignment. - NVPTX failing tests did not have the right alignment. - AMDGPU failing test (merge-stores) should allow vectorization with the given alignment but the target info considers <3xi32> a non-standard type and gives up early. This patch removes the condition and only checks for a maximum size allowed and relies on the next condition checking for %4 for correctness. This should be revisited to include 3xi32 as a MVT type (on arsenm's non-immediate todo list). Note that checking the sizeInBits for a MVT is undefined (leads to an assertion failure), so we need to create an EVT, hence the interface change in allowsMisaligned to include the Context. Reviewers: arsenm, jlebar, tstellarAMD Subscribers: jholewinski, arsenm, mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D23068 llvm-svn: 277735
* [mips] Set Personality and LSDA encoding for FreeBSDDaniel Sanders2016-08-041-0/+8
| | | | | | | | | | Reviewers: seanbruno, sdardis Subscribers: tberghammer, danalbert, srhines, dsanders, sdardis, llvm-commits, seanbruno Differential Revision: https://reviews.llvm.org/D23113 llvm-svn: 277732
* [InstCombine] use m_APInt to allow icmp eq (sub C1, X), C2 folds for splat ↵Sanjay Patel2016-08-041-4/+4
| | | | | | constant vectors llvm-svn: 277731
* [X86][SSE] Split off shuffle mask canonicalization from lowerVectorShuffle. ↵Simon Pilgrim2016-08-041-52/+67
| | | | | | | | | | NFCI. The new function now returns true if the shuffle should be commuted. This will allow target shuffle combines to share the code. llvm-svn: 277728
* [Hexagon] Clear kill flags from modified registers in peephole optimizerKrzysztof Parzyszek2016-08-041-1/+4
| | | | llvm-svn: 277727
* [X86] Heuristic to selectively build Newton-Raphson SQRT estimationNikolai Bozhenov2016-08-049-7/+54
| | | | | | | | | | | | | | | | | | | | | On modern Intel processors hardware SQRT in many cases is faster than RSQRT followed by Newton-Raphson refinement. The patch introduces a simple heuristic to choose between hardware SQRT instruction and Newton-Raphson software estimation. The patch treats scalars and vectors differently. The heuristic is that for scalars the compiler should optimize for latency while for vectors it should optimize for throughput. It is based on the assumption that throughput bound code is likely to be vectorized. Basically, the patch disables scalar NR for big cores and disables NR completely for Skylake. Firstly, scalar SQRT has shorter latency than NR code in big cores. Secondly, vector SQRT has been greatly improved in Skylake and has better throughput compared to NR. Differential Revision: https://reviews.llvm.org/D21379 llvm-svn: 277725
* [mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructionsHrvoje Varga2016-08-045-7/+35
| | | | | | Differential Revision: https://reviews.llvm.org/D22347 llvm-svn: 277719
* [X86][SSE] Add initial costs for vector CTTZ/CTLZSimon Pilgrim2016-08-041-4/+41
| | | | llvm-svn: 277716
* [X86][SSE] Don't decide when to scalarize CTTZ/CTLZ for performance at ↵Simon Pilgrim2016-08-041-12/+4
| | | | | | | | lowering - this is what cost models are for Improved CTTZ/CTLZ costings will be added shortly llvm-svn: 277713
* [mips] Enable tail calls by defaultSimon Dardis2016-08-048-10/+61
| | | | | | | | | | | | | | | | | | Enable tail calls by default for (micro)MIPS(64). microMIPS is slightly more tricky than doing it for MIPS(R6) or microMIPSR6. microMIPS has two instruction encodings: 16bit and 32bit along with some restrictions on the size of the instruction that can fill the delay slot. For safe tail calls for microMIPS, the delay slot filler attempts to find a correct size instruction for the delay slot of TAILCALL pseudos. Reviewers: dsanders, vkalintris Subscribers: jfb, dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D21138 llvm-svn: 277708
* Typo fix in comment. NFCDiana Picus2016-08-041-1/+1
| | | | llvm-svn: 277704
* [XRay] Align entry and return sleds to 2 byte boundariesDean Michael Berris2016-08-041-2/+4
| | | | | | | | | | | | | | | | | | | | This should ensure that we can atomically write two bytes (on top of the retq and the one past it) and have those two bytes not straddle cache lines. We also move the label past the alignment instruction so that we can refer to the actual first instruction, as opposed to potential padding before the aligned instruction. Update the tests to allow us to reflect the new order of assembly. Reviewers: rSerge, echristo, majnemer Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D23101 llvm-svn: 277701
* Add popcount(n) == bitsize(n) -> n == -1 transformation.Amaury Sechet2016-08-041-4/+10
| | | | | | | | | | | | Summary: As per title. Reviewers: majnemer, spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23139 llvm-svn: 277694
* Forgot the dyn_cast_or_null intended for r277691.David Majnemer2016-08-041-1/+1
| | | | llvm-svn: 277693
* Reinstate "[CloneFunction] Don't remove side effecting calls"David Majnemer2016-08-042-4/+37
| | | | | | | This reinstates r277611 + r277614 and reverts r277642. A cast_or_null should have been a dyn_cast_or_null. llvm-svn: 277691
* Revert "GVN-hoist: enable by default" & "Make GVN Hoisting obey optnone/bisect."Bruno Cardoso Lopes2016-08-041-2/+2
| | | | | | | | This reverts commits r277685 & r277688. r277685 broke compiler-rt compilation http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_build/23335 and r277685 is a followup from it. llvm-svn: 277690
* [PM] Change the name of the repeating utility to something lessChandler Carruth2016-08-041-4/+4
| | | | | | | | | | | overloaded (and simpler). Sean rightly pointed out in code review that we've started using "wrapper pass" as a specific part of the old pass manager, and in fact it is more applicable there. Here, we really have a pass *template* to build a repeated pass, so call it that. llvm-svn: 277689
* GVN-hoist: enable by defaultSebastian Pop2016-08-041-2/+2
| | | | | | | | | | As we addressed all compilation time problems with GVN-hoist https://llvm.org/bugs/show_bug.cgi?id=28670 this patch turns GVN-hoist back by default. Differential Revision: https://reviews.llvm.org/D23136 llvm-svn: 277685
* pdbdump: Fix crash bug.Rui Ueyama2016-08-031-1/+4
| | | | | | | | | | pdbdump calls DbiStreamBuilder::commit through PDBFileBuilder::commit without calling DbiStreamBuilder::finalize. Because `finalize` initializes `Header` member, `Header` remained nullptr which caused a crash bug. Differential Revision: https://reviews.llvm.org/D23143 llvm-svn: 277681
* RenameIndependentSubregs: Fix liveness query in rewriteOperands()Matthias Braun2016-08-031-7/+6
| | | | | | | | rewriteOperands() always performed liveness queries at the base index rather than the RegSlot/Base as apropriate for the machine operand. This could lead to illegal rewriting in some cases. llvm-svn: 277661
* [InstCombine] use m_APInt to allow icmp eq (add X, C1), C2 folds for splat ↵Sanjay Patel2016-08-031-6/+8
| | | | | | constant vectors llvm-svn: 277659
* Clean up of libObject/Archive interfaces and change the last three uses of ↵Kevin Enderby2016-08-031-40/+75
| | | | | | | | | | | | ErrorOr<> changing them to Expected<> to allow them to pass through llvm Errors. No functional change. This commit by itself will break the next lld builds.  I’ll be committing the matching change for lld immediately next. llvm-svn: 277656
* [PPC] Handling CallInst in PPCBoolRetToIntGuozhi Wei2016-08-031-7/+13
| | | | | | | | This patch fixes pr25548. Current implementation of PPCBoolRetToInt doesn't handle CallInst correctly, so it failed to do the intended optimization when there is a CallInst with parameters. This patch fixed that. llvm-svn: 277655
* Revert "[ARM] Constant Materialize: imms with specific value can be encoded ↵Bruno Cardoso Lopes2016-08-031-3/+1
| | | | | | | | | | | into mov.w" This reverts commit r277610 / d619aa8878c3dafcc0d29a46517f63ff3209fdd4. This make subtarget-no-movt.ll fail in http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental_check/26892, llvm-svn: 277654
* [MSSA] Fix a bug in MemorySSA's move ctor.George Burgess IV2016-08-031-0/+2
| | | | | | | Not a correctness issue, but it would be nice if we didn't have to recompute our block numbering (worst-case) every time we move MSSA. llvm-svn: 277652
* GVN-hoist: limit the length of dependent instructionsSebastian Pop2016-08-031-0/+10
| | | | | | | | | | Limit the number of times the while(1) loop is executed. With this restriction the number of hoisted instructions does not change in a significant way on the test-suite. Differential Revision: https://reviews.llvm.org/D23028 llvm-svn: 277651
* GVN-hoist: compute DFS numbers onceSebastian Pop2016-08-031-12/+22
| | | | | | | | | With this patch we compute the DFS numbers of instructions only once and update them during the code generation when an instruction gets hoisted. Differential Revision: https://reviews.llvm.org/D23021 llvm-svn: 277650
* GVN-hoist: compute MSSA once per function (PR28670)Sebastian Pop2016-08-031-12/+49
| | | | | | | | With this patch we compute the MemorySSA once and update it in the code generator. Differential Revision: https://reviews.llvm.org/D22966 llvm-svn: 277649
* Revert "[CloneFunction] Don't remove side effecting calls"Reid Kleckner2016-08-032-37/+4
| | | | | | | | | This reverts commit r277611 and the followup r277614. Bootstrap builds and chromium builds are crashing during inlining after this change. llvm-svn: 277642
* [MSSA] clang-format. NFC.George Burgess IV2016-08-031-8/+4
| | | | | | | Didn't want to fold this in with r277640, since it touches bits that aren't entirely related to r277640. llvm-svn: 277641
* [MSSA] Add special handling for invariant/constant loads.George Burgess IV2016-08-031-0/+23
| | | | | | | This is a follow-up to r277637. It teaches MemorySSA that invariant loads (and loads of provably constant memory) are always liveOnEntry. llvm-svn: 277640
* [InstCombine] use m_APInt to allow icmp eq (srem X, C1), C2 folds for splat ↵Sanjay Patel2016-08-031-4/+3
| | | | | | constant vectors llvm-svn: 277638
* [MSSA] Add logic for special handling of atomics/volatiles.George Burgess IV2016-08-031-0/+58
| | | | | | | | | | | | | | | This patch makes MemorySSA recognize atomic/volatile loads, and makes MSSA treat said loads specially. This allows us to be a bit more aggressive in some cases. Administrative note: Revision was LGTM'ed by reames in person. Additionally, this doesn't include the `invariant.load` recognition in the differential revision, because I feel it's better to commit that separately. Will commit soon. Differential Revision: https://reviews.llvm.org/D16875 llvm-svn: 277637
* [InstCombine] Refactor optimization of zext(or(icmp, icmp)) to enable more ↵Tobias Grosser2016-08-032-6/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | aggressive cast-folding Summary: InstCombine unfolds expressions of the form `zext(or(icmp, icmp))` to `or(zext(icmp), zext(icmp))` such that in a later iteration of InstCombine the exposed `zext(icmp)` instructions can be optimized. We now combine this unfolding and the subsequent `zext(icmp)` optimization to be performed together. Since the unfolding doesn't happen separately anymore, we also again enable the folding of `logic(cast(icmp), cast(icmp))` expressions to `cast(logic(icmp, icmp))` which had been disabled due to its interference with the unfolding transformation. Tested via `make check` and `lnt`. Background ========== For a better understanding on how it came to this change we subsequently summarize its history. In commit r275989 we've already tried to enable the folding of `logic(cast(icmp), cast(icmp))` to `cast(logic(icmp, icmp))` which had to be reverted in r276106 because it could lead to an endless loop in InstCombine (also see http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160718/374347.html). The root of this problem is that in `visitZExt()` in InstCombineCasts.cpp there also exists a reverse of the above folding transformation, that unfolds `zext(or(icmp, icmp))` to `or(zext(icmp), zext(icmp))` in order to expose `zext(icmp)` operations which would then possibly be eliminated by subsequent iterations of InstCombine. However, before these `zext(icmp)` would be eliminated the folding from r275989 could kick in and cause InstCombine to endlessly switch back and forth between the folding and the unfolding transformation. This is the reason why we now combine the `zext`-unfolding and the elimination of the exposed `zext(icmp)` to happen at one go because this enables us to still allow the cast-folding in `logic(cast(icmp), cast(icmp))` without entering an endless loop again. Details on the submitted changes ================================ - In `visitZExt()` we combine the unfolding and optimization of `zext` instructions. - In `transformZExtICmp()` we have to use `Builder->CreateIntCast()` instead of `CastInst::CreateIntegerCast()` to make sure that the new `CastInst` is inserted in a `BasicBlock`. The new calls to `transformZExtICmp()` that we introduce in `visitZExt()` would otherwise cause according assertions to be triggered (in our case this happend, for example, with lnt for the MultiSource/Applications/sqlite3 and SingleSource/Regression/C++/EH/recursive-throw tests). The subsequent usage of `replaceInstUsesWith()` is necessary to ensure that the new `CastInst` replaces the `ZExtInst` accordingly. - In InstCombineAndOrXor.cpp we again allow the folding of casts on `icmp` instructions. - The instruction order in the optimized IR for the zext-or-icmp.ll test case is different with the introduced changes. - The test cases in zext.ll have been adopted from the reverted commits r275989 and r276105. Reviewers: grosser, majnemer, spatel Subscribers: eli.friedman, majnemer, llvm-commits Differential Revision: https://reviews.llvm.org/D22864 Contributed-by: Matthias Reisinger <d412vv1n@gmail.com> llvm-svn: 277635
* Pass EphValues by const-ref as it is not modified in the calleeSebastian Pop2016-08-031-1/+1
| | | | | | | | Patch by Aditya Kumar. Differential Revision: https://reviews.llvm.org/D22967 llvm-svn: 277634
* [X86][SSE] Enable target shuffle combining to combine multiple shuffle inputs.Simon Pilgrim2016-08-031-28/+78
| | | | | | | | | | | | | | We currently only support combining target shuffles that consist of a single source input (plus elements known to be undef/zero). This patch generalizes the recursive combining of the target shuffle to collect all the inputs, merging any duplicates along the way, into a full set of src ops and its shuffle mask. We uncover a number of cases where we have failed to combine a unary shuffle because the input has been duplicated and separated during lowering. This will allow us to combine to 2-input shuffles in a future patch. Differential Revision: https://reviews.llvm.org/D22859 llvm-svn: 277631
* Reapply "More fixes to get good error messages for bad archives."Vedant Kumar2016-08-032-16/+66
| | | | | | | | This reverts commit the revert commit r277627. The build errors mentioned in r277627 were likely caused by an unclean build directory. Sorry for the noise. llvm-svn: 277630
* [InstCombine] use m_APInt to allow icmp (binop X, Y), C folds with constant ↵Sanjay Patel2016-08-031-14/+20
| | | | | | | | | splat vectors This removes the restriction for the icmp constant, but as noted by the FIXME comments, we still need to change individual checks for binop operand constants. llvm-svn: 277629
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