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* Even though no caller actually uses the new valueDuncan Sands2008-09-011-1/+2
| | | | | | | (what matters is that it is added to the worklist), it seems more logical to return it. llvm-svn: 55606
* Add a small pass that sets the readnone/readonlyDuncan Sands2008-09-011-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | attributes on functions, based on the result of alias analysis. It's not hardwired to use GlobalsModRef even though this is the only (AFAIK) alias analysis that results in this pass actually doing something. Enable as follows: opt ... -globalsmodref-aa -markmodref ... Advantages of this pass: (1) records the result of globalsmodref in the bitcode, meaning it is available for use by later passes (currently the pass manager isn't smart enough to magically make an advanced alias analysis available to all later passes), which may expose more optimization opportunities; (2) hopefully speeds up compilation when code is optimized twice, for example when a file is compiled to bitcode, then later LTO is done on it: marking functions readonly/readnone when producing the initial bitcode should speed up alias analysis during LTO; (3) good for discovering that globalsmodref doesn't work very well :) Not currently turned on by default. llvm-svn: 55604
* Control flow instruction encodings.Evan Cheng2008-09-012-17/+71
| | | | llvm-svn: 55601
* ldm / stm instruction encodings.Evan Cheng2008-09-012-6/+28
| | | | llvm-svn: 55599
* AXI2 and AXI3 instruction encodings.Evan Cheng2008-09-012-10/+94
| | | | llvm-svn: 55598
* Reorganize instruction formats again; AXI1 encoding.Evan Cheng2008-09-011-34/+35
| | | | llvm-svn: 55597
* addrmode3 instruction encodings.Evan Cheng2008-09-012-42/+208
| | | | llvm-svn: 55596
* Reorganize some instruction format definitions. No functionality change.Evan Cheng2008-09-011-18/+29
| | | | llvm-svn: 55594
* Rest of addrmode2 instruction encodings.Evan Cheng2008-09-012-14/+106
| | | | llvm-svn: 55593
* Addr2 word / byte load encodings.Evan Cheng2008-08-312-4/+24
| | | | llvm-svn: 55591
* Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.Evan Cheng2008-08-311-4/+5
| | | | llvm-svn: 55590
* fix a bunch of 80-col violationsGabor Greif2008-08-315-33/+65
| | | | llvm-svn: 55588
* Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTRBill Wendling2008-08-311-3/+7
| | | | | | | | instructions in CellSPU as "Expand" so that they won't be generated. I added a "FIXME" so that this hack can be addressed and reverted once ISD::ROTR is supported in the .td files. llvm-svn: 55582
* Expand for ROTR with MVT::i64.Bill Wendling2008-08-311-0/+1
| | | | | | Dale, Could you please review this? llvm-svn: 55581
* Cosmetic changes to Machine LICM. No functionality change.Bill Wendling2008-08-311-31/+36
| | | | llvm-svn: 55578
* Another situation where ROTR is cheaper than ROTL.Bill Wendling2008-08-311-3/+3
| | | | llvm-svn: 55577
* For this pattern, ROTR is the cheaper option.Bill Wendling2008-08-311-4/+4
| | | | llvm-svn: 55576
* - Fix comment so that it describes how the code really works:Bill Wendling2008-08-311-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> // (rotl x, y) // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> // (rotr x, (sub 32, y)) Example: (x == 0xDEADBEEF and y == 4) (x << 4) | (x >> 28) => 0xEADBEEF0 | 0x0000000D => 0xEADBEEFD (rotl x, 4) => 0xEADBEEFD (rotr x, 28) => 0xEADBEEFD - Fix comment and code for second version. It wasn't using the rot* propertly. // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> // (rotr x, y) // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> // (rotl x, (sub 32, y)) (x << 28) | (x >> 4) => 0xD0000000 | 0x0DEADBEE => 0xDDEADBEE (rotl x, 4) => 0xEADBEEFD (rotr x, 28) => (0xEADBEEFD) llvm-svn: 55575
* typoGabor Greif2008-08-301-1/+1
| | | | llvm-svn: 55574
* fix some 80-col violationsGabor Greif2008-08-301-19/+23
| | | | llvm-svn: 55571
* PR2731: C and Ocaml bindings for setTailCall and isTailCall.Gordon Henriksen2008-08-301-0/+10
| | | | | | Based on patch by Giorgos Korfiatis. llvm-svn: 55570
* Fix ConstantExpr::getInsertElement.Gordon Henriksen2008-08-301-2/+1
| | | | | | | Breakage was exposed in the Ocaml bindings tests after Chris uncommented an assertion in r55084. llvm-svn: 55566
* fix some 80-col violationsGabor Greif2008-08-302-3/+5
| | | | llvm-svn: 55565
* Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer ↵Evan Cheng2008-08-302-4/+83
| | | | | | the implicit defs onto the remat'ed instruction. llvm-svn: 55564
* Fold isRematerializable checks into isSafeToReMat.Evan Cheng2008-08-301-1/+3
| | | | llvm-svn: 55563
* For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But ↵Evan Cheng2008-08-301-1/+1
| | | | | | various passes cannot handle remating these. llvm-svn: 55562
* Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 ↵Evan Cheng2008-08-303-0/+116
| | | | | | shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). llvm-svn: 55558
* Fix an issue where a use might be selected before a def, and then we didn't ↵Owen Anderson2008-08-301-8/+23
| | | | | | | | | | | respect the pre-chosen vreg assignment when selecting the def. This is the naive solution to the problem: insert a copy to the pre-chosen vreg. Other solutions might be preferable, such as: 1) Passing the dest reg into FastEmit_. However, this would require the higher level code to know about reg classes, which they don't currently. 2) Selecting blocks in reverse postorder. This has some compile time cost for computing the order, and we'd need to measure its impact. llvm-svn: 55555
* Add ppc partial-word ATOMIC_CMP_SWAP.Dale Johannesen2008-08-301-4/+143
| | | | llvm-svn: 55554
* Swap fp comparison operands and change predicate to allow load folding ↵Evan Cheng2008-08-291-16/+50
| | | | | | (safely this time). llvm-svn: 55553
* Use static_cast instead of C style cast.Evan Cheng2008-08-291-1/+2
| | | | llvm-svn: 55552
* Fix 80 col. violations.Evan Cheng2008-08-291-2/+4
| | | | llvm-svn: 55551
* Back out 55498. It broken Apple style bootstrapping.Evan Cheng2008-08-291-106/+81
| | | | llvm-svn: 55549
* Backing out 55521. Not safe.Evan Cheng2008-08-293-49/+5
| | | | llvm-svn: 55548
* Add partial word version of ATOMIC_SWAP.Dale Johannesen2008-08-291-50/+29
| | | | llvm-svn: 55546
* Add initial support for fast isel of instructions that have inputs pinned to ↵Owen Anderson2008-08-291-0/+1
| | | | | | physical registers. llvm-svn: 55545
* regenerateChris Lattner2008-08-293-1455/+1531
| | | | llvm-svn: 55542
* Asmprint nameless instructions as:Chris Lattner2008-08-291-1/+8
| | | | | | | | | | | | | %4 = add ... instead of: add ... ; 4 This makes opt -print-cfg output actually usable and makes .ll files generally easier to read. This fixes PR2480 llvm-svn: 55541
* Add support for parsing .ll files that have numbers in front ofChris Lattner2008-08-291-5/+39
| | | | | | | | | | nameless values, such as: %3 = add i32 4, 2 This fixes the first half of PR2480 llvm-svn: 55539
* TableGen'ing instruction encodings.Evan Cheng2008-08-291-1/+2
| | | | llvm-svn: 55533
* addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 ↵Evan Cheng2008-08-291-3/+10
| | | | | | encode the opcode. llvm-svn: 55531
* MVN is addrmode1.Evan Cheng2008-08-291-7/+7
| | | | llvm-svn: 55530
* More refactoring.Evan Cheng2008-08-292-45/+55
| | | | llvm-svn: 55528
* Swap fp comparison operands and change predicate to allow load folding.Evan Cheng2008-08-283-5/+49
| | | | llvm-svn: 55521
* Refactor ARM instruction format definitions into a separate file. No ↵Evan Cheng2008-08-282-215/+232
| | | | | | functionality changes. llvm-svn: 55518
* Add a target callback for FastISel.Dan Gohman2008-08-282-2/+27
| | | | llvm-svn: 55512
* remove tabs, fix > 80 colsGabor Greif2008-08-281-10/+16
| | | | llvm-svn: 55511
* rename destroy -> releaseMemory to properly hook into passmgr.Chris Lattner2008-08-281-2/+2
| | | | llvm-svn: 55508
* Add support for JIT exceptions on Darwin. Since we're dealing with libgcc,Nicolas Geoffray2008-08-281-2/+135
| | | | | | | whose darwin code was written after the ability to dynamically register frames, we need to do special hacks to make things work. llvm-svn: 55507
* erect abstraction boundaries for accessing SDValue members, rename Val -> ↵Gabor Greif2008-08-2834-1105/+1113
| | | | | | Node to reflect semantics llvm-svn: 55504
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