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* Add PeekDavid Greene2011-10-192-0/+5
| | | | | | | | | | | | | Add a peek function to let the Lexer look at a character arbitrarily far ahead in the stream without consuming anything. We need this to disambiguate numbers and operands of a paste operation. For example: def foo#8i Without lookahead the lexer will treat '8' as a number rather than as part of a string to be pasted to form an identifier. llvm-svn: 142512
* Resolve Record NamesDavid Greene2011-10-191-0/+6
| | | | | | | When resolving Record values, be sure to update the Record name as it may contain references to the value. llvm-svn: 142511
* Allow Names Changes on Unregistered RecordsDavid Greene2011-10-191-4/+3
| | | | | | | | | | | Add Record names to be changed even on Records that aren't yet registered. We need to be able to do this for paste functionality because we do not want to register def names before they are unique and that can only happen once all paste operations are done. This change lets us update Record names formed by paste operations and register the result later. llvm-svn: 142510
* Fix Name AccessDavid Greene2011-10-191-1/+1
| | | | | | Ask for the Record name as a string explicitly to avoid a possible assert. llvm-svn: 142506
* Fix Name AccessDavid Greene2011-10-191-1/+1
| | | | | | | Ask for the Record name as a string explicitly to avoid a possible assert. llvm-svn: 142505
* Fix Name AccessDavid Greene2011-10-191-1/+1
| | | | | | | Ask for the record name as a string explicitly to avoid a potential assert. llvm-svn: 142504
* Add Record InitDavid Greene2011-10-191-0/+4
| | | | | | Add an init function to be shared among Record constructors. llvm-svn: 142501
* Make Template Arg Names InitsDavid Greene2011-10-193-34/+43
| | | | | | | | Allow template arg names to be Inits. This is further work to implement paste as it allows template names to participate in paste operations. llvm-svn: 142500
* Let SetValue Take and Init NameDavid Greene2011-10-192-9/+17
| | | | | | | Convert SetValue to take the value name as an Init. This allows us to set values for variables whose names are not yet fully resolved. llvm-svn: 142499
* Add Utility to Scope NamesDavid Greene2011-10-191-0/+36
| | | | | | | | Add a couple of utility functions to take a variable name and qualify it with the namespace of the enclosing class and/or multiclass. This is inpreparation for making template arg names first-class Inits. llvm-svn: 142498
* Make VarInit Name an InitDavid Greene2011-10-191-1/+13
| | | | | | | | Make the VarInit name an Init itself. We need this to implement paste functionality so we can reference variables whose names are not yet completely resolved. llvm-svn: 142497
* Add Value AccessorsDavid Greene2011-10-191-0/+12
| | | | | | | | Add accessors to get Record values by Init name. This lets us look up Record values whose names are not yet fully resolved. More work toward paste. llvm-svn: 142496
* Generalize the reading of probability metadata to work for both branchesChandler Carruth2011-10-191-16/+24
| | | | | | | | | and switches, with arbitrary numbers of successors. Still optimized for the common case of 2 successors for a conditional branch. Add a test case for switch metadata showing up in the BlockFrequencyInfo pass. llvm-svn: 142493
* Teach the BranchProbabilityInfo analysis pass to read any metadataChandler Carruth2011-10-191-0/+38
| | | | | | | | | | | encoding of probabilities. In the absense of metadata, it continues to fall back on static heuristics. This allows __builtin_expect, after lowering through llvm.expect a branch instruction's metadata, to actually enter the branch probability model. This is one component of resolving PR2577. llvm-svn: 142492
* Add pass printing support to BlockFrequencyInfo pass. The implementationChandler Carruth2011-10-191-0/+4
| | | | | | | | | | | | | layer already had support for printing the results of this analysis, but the wiring was missing. Now that printing the analysis works, actually bring some of this analysis, and the BranchProbabilityInfo analysis that it wraps, under test! I'm planning on fixing some bugs and doing other work here, so having a nice place to add regression tests and a way to observe the results is really useful. llvm-svn: 142491
* Add support for the vector-widening of vselect and vector-setccNadav Rotem2011-10-192-1/+28
| | | | llvm-svn: 142488
* Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, ↵Bill Wendling2011-10-191-5/+27
| | | | | | use a constant pool. llvm-svn: 142485
* Remove some dead code.Bill Wendling2011-10-191-6/+0
| | | | llvm-svn: 142484
* Rename PEXTR to PEXT. Add intrinsics for BMI instructions.Craig Topper2011-10-191-24/+47
| | | | llvm-svn: 142480
* Adding dependencies to allow -DBUILD_SHARED_LIBS=true to complete.Joe Abbey2011-10-191-0/+1
| | | | llvm-svn: 142464
* Emit the MOVT instruction only if the # LPads is > 64K.Bill Wendling2011-10-181-10/+20
| | | | llvm-svn: 142460
* For Thumb mode, we need to use a constant pool if the value is too large to beBill Wendling2011-10-181-3/+20
| | | | | | used with the CMP instruction. llvm-svn: 142458
* Revert "Turn on the vzeroupper pass by default."Eric Christopher2011-10-181-1/+1
| | | | | | This reverts commit 494f7ac3e8d2ab3d94e52317abf9c42a949fe1f3. llvm-svn: 142455
* ARM VTBL (one register) assembly parsing and encoding.Jim Grosbach2011-10-184-3/+101
| | | | llvm-svn: 142441
* Use the integer compare when the value is small enough. Use the "move into aBill Wendling2011-10-181-2/+17
| | | | | | | register and then compare against that" method when it's too large. We have to move the value into the register in the "movw, movt" pair of instructions. llvm-svn: 142440
* Turn on the vzeroupper pass by default.Eric Christopher2011-10-181-1/+1
| | | | | | I'll remove/rename the option in a few days. llvm-svn: 142439
* Use the integer compare when the value is small enough. Use the "move into aBill Wendling2011-10-181-6/+19
| | | | | | | register and then compare against that" method when it's too large. We have to move the value into the register in the "movw, movt" pair of instructions. llvm-svn: 142437
* Missed a spot!Nick Lewycky2011-10-181-1/+1
| | | | llvm-svn: 142436
* Fix some typo/formatting issues. No functionality change.Nick Lewycky2011-10-182-10/+10
| | | | llvm-svn: 142435
* Fix a bug in the legalization of vector anyext-load and trunc-store. Mem ↵Nadav Rotem2011-10-181-7/+9
| | | | | | Index starts with zero. llvm-svn: 142434
* Teach fast isel about vector stores, and make DoSelectCall return false when ↵Lang Hames2011-10-181-3/+24
| | | | | | it fails to emit a store. This fixes <rdar://problem/10215997>. llvm-svn: 142432
* The value we're comparing against may be too large for the ARM CMPBill Wendling2011-10-181-12/+16
| | | | | | | instruction. Move the value into a register and then use that for the CMP. <rdar://problem/10305266> llvm-svn: 142431
* The immediate may be too large for the CMP instruction. Move it into a registerBill Wendling2011-10-181-8/+13
| | | | | | | and use that in the CMP. <rdar://problem/10305266> llvm-svn: 142429
* Yet more ARM NEON assembly parsing for the lane index operand.Jim Grosbach2011-10-181-18/+18
| | | | llvm-svn: 142416
* ARM vmla/vmls assembly parsing for the lane index operand.Jim Grosbach2011-10-181-4/+4
| | | | llvm-svn: 142413
* ARM vmov assembly parsing for the lane index operand.Jim Grosbach2011-10-181-16/+16
| | | | llvm-svn: 142412
* The MCJITMemoryManager takes ownership of the JMM, so don't leak it.Jim Grosbach2011-10-181-0/+2
| | | | llvm-svn: 142410
* Object/COFF: Remove useless test.Michael J. Spencer2011-10-181-1/+1
| | | | llvm-svn: 142408
* Object/COFF: Change type from a struct to a uint16_t. The struct would beMichael J. Spencer2011-10-181-1/+1
| | | | | | incorrect for bigendian systems. llvm-svn: 142403
* Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.Andrew Trick2011-10-184-119/+112
| | | | | | | | Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
* Use isIntN and isUIntN to check for valid signed/unsigned numbers.Bob Wilson2011-10-181-3/+2
| | | | llvm-svn: 142395
* whitespaceAndrew Trick2011-10-182-7/+7
| | | | llvm-svn: 142394
* A landing pad could have more than one predecessor. In that case, we want thatBill Wendling2011-10-181-1/+8
| | | | | | | | | | predecessor to remove the jump to it as well. Delay clearing the 'landing pad' flag until after the jumps have been removed. (There is an implicit assumption in several modules that an MBB which jumps to a landing pad has only two successors.) <rdar://problem/10304224> llvm-svn: 142390
* ARM vmla/vmls assembly parsing for the lane index operand.Jim Grosbach2011-10-181-8/+8
| | | | llvm-svn: 142389
* ARM vqdmulh assembly parsing for the lane index operand.Jim Grosbach2011-10-181-4/+4
| | | | llvm-svn: 142386
* ARM vmul assembly parsing for the lane index operand.Jim Grosbach2011-10-181-4/+4
| | | | llvm-svn: 142381
* Final patch that completes old JIT support for Mips:Bruno Cardoso Lopes2011-10-187-91/+173
| | | | | | | | | | | | | | | | -Fix binary codes and rename operands in .td files so that automatically generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct encoding for instructions. -Define new class FMem for instructions that access memory. -Define new class FFRGPR for instructions that move data between GPR and FPU general and control registers. -Define custom encoder methods for memory operands, and also for size operands of ext and ins instructions. -Only static relocation model is currently implemented. Patch by Sasa Stankovic llvm-svn: 142378
* Fix incorrect check for sign-extended constant BUILD_VECTOR.Bob Wilson2011-10-181-1/+1
| | | | | | <rdar://problem/10298332> llvm-svn: 142371
* Fix a DAG combiner assertion failure when constant folding BUILD_VECTORS.Bob Wilson2011-10-181-2/+13
| | | | | | | | | svn r139159 caused SelectionDAG::getConstant() to promote BUILD_VECTOR operands with illegal types, even before type legalization. For this testcase, that led to one BUILD_VECTOR with i16 operands and another with promoted i32 operands, which triggered the assertion. llvm-svn: 142370
* ARM vqdmlal assembly parsing for the lane index operand.Jim Grosbach2011-10-181-2/+2
| | | | llvm-svn: 142365
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