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* Remove dead code.Eric Christopher2015-03-102-25/+0
| | | | llvm-svn: 231883
* Add missing section symbol to COFF's .debug_types.dwo.Rafael Espindola2015-03-101-1/+1
| | | | | | | | | Should bring the cygwin bots back. I added a triple to the test that was failing so that it would have failed on Linux. llvm-svn: 231882
* If a conditional branch jumps to the same target, remove the conditionPhilip Reames2015-03-101-0/+9
| | | | | | | | | | | | Given that large parts of inst combine is restricted to instructions which have one use, getting rid of a use on the condition can help the effectiveness of the optimizer. Also, it allows the condition to potentially be deleted by instcombine rather than waiting for another pass. I noticed this completely by accident in another test case. It's not anything that actually came from a real workload. p.s. We should probably do the same thing for switch instructions. Differential Revision: http://reviews.llvm.org/D8220 llvm-svn: 231881
* Emit correct linkage-name attribute based on DWARF version.Paul Robinson2015-03-103-13/+15
| | | | | | | | | | There are still 4 tests that check for DW_AT_MIPS_linkage_name, because they specify DWARF 2 or 3 in the module metadata. So, I didn't create an explicit version-based test for the attribute. Differential Revision: http://reviews.llvm.org/D8227 llvm-svn: 231880
* Infer known bits from dominating conditionsPhilip Reames2015-03-101-0/+212
| | | | | | | | | | | | | | | | | This patch adds limited support in ValueTracking for inferring known bits of a value from conditional expressions which must be true to reach the instruction we're trying to optimize. At this time, the feature is off by default. Once landed, I'm hoping for feedback from others on both profitability and compile time impact. Forms of conditional value propagation have been tried in LLVM before and have failed due to compile time problems. In an attempt to side step that, this patch only considers conditions where the edge leaving the branch dominates the context instruction. It does not attempt full dataflow. Even with that restriction, it handles many interesting cases: * Early exits from functions * Early exits from loops (for context instructions in the loop and after the check) * Conditions which control entry into loops, including multi-version loops (such as those produced during vectorization, IRCE, loop unswitch, etc..) Possible applications include optimizing using information provided by constructs such as: preconditions, assumptions, null checks, & range checks. This patch implements two approaches to the problem that need further benchmarking. Approach 1 is to directly walk the dominator tree looking for interesting conditions. Approach 2 is to inspect other uses of the value being queried for interesting comparisons. From initial benchmarking, it appears that Approach 2 is faster than Approach 1, but this needs to be further validated. Differential Revision: http://reviews.llvm.org/D7708 llvm-svn: 231879
* Remove the use of the subtarget in MCCodeEmitter creation andEric Christopher2015-03-1023-57/+22
| | | | | | | update all ports accordingly. Required a couple of small rewrites in handling subtarget features during creation in PPC. llvm-svn: 231861
* Create symbols marking the start of a section earlier.Rafael Espindola2015-03-106-102/+122
| | | | | | | | | This lets us pass the symbol to the constructor and avoid the mutable field. This also opens the way for outputting the symbol only when needed, instead of outputting them at the start of the file. llvm-svn: 231859
* Remove createAMDGPUMCCodeEmitter and instead just register the correctEric Christopher2015-03-103-16/+7
| | | | | | | MCCodeEmitter creation routine based on TargetMachine since the only 64-bit R600 gpus are part of the GCN target. llvm-svn: 231856
* [CodeGenPrepare] Refine the cost model provided by the promotion helper.Quentin Colombet2015-03-101-61/+77
| | | | | | | | | | | | | | | | | - Use TargetLowering to check for the actual cost of each extension. - Provide a factorized method to check for the cost of an extension: TargetLowering::isExtFree. - Provide a virtual method TargetLowering::isExtFreeImpl for targets to be able to tune the cost of non-free extensions. This refactoring offers a better granularity to model what really happens on different targets. No performance changes and very few code differences. Part of <rdar://problem/19267165> llvm-svn: 231855
* [LoopAccesses] Add debug message to indicate the result of the analysisAdam Nemet2015-03-101-4/+7
| | | | | | | | | | The debug message was pretty confusing here. It only reported the situation with memchecks without the result of the dependence analysis. Now it prints whether the loop is safe from the POV of the dependence analysis and if yes, whether we need memchecks. llvm-svn: 231854
* Move a non-trivial virtual function out of line.Rafael Espindola2015-03-101-0/+11
| | | | llvm-svn: 231853
* [Hexagon] Adding frame index + add load/store patterns.Colin LeMahieu2015-03-102-5/+20
| | | | llvm-svn: 231850
* clang-format code that is about to change.Rafael Espindola2015-03-102-283/+219
| | | | llvm-svn: 231848
* [Hexagon] Simplifying deallocret definitions.Colin LeMahieu2015-03-101-12/+3
| | | | llvm-svn: 231847
* [Hexagon] Separating InstHexagon from OpcodeHexagon.Colin LeMahieu2015-03-103-47/+57
| | | | llvm-svn: 231844
* Add support for part-word atomics for PPCNemanja Ivanovic2015-03-107-67/+141
| | | | | | http://reviews.llvm.org/D8090#inline-67337 llvm-svn: 231843
* [AArch64] Avoid going through GPRs for across-vector instructions.Ahmed Bougacha2015-03-103-119/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds new node types for each intrinsic. For instance, for addv, we have AArch64ISD::UADDV, such that: (v4i32 (uaddv ...)) is the same as (v4i32 (scalar_to_vector (i32 (int_aarch64_neon_uaddv ...)))) that is, (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (i32 (int_aarch64_neon_uaddv ...)), ssub) In a combine, we transform all such across-vector-lanes intrinsics to: (i32 (extract_vector_elt (uaddv ...), 0)) This has one big advantage: by making the extract_element explicit, we enable the existing patterns for lane-aware instructions to fire. This lets us avoid needlessly going through the GPRs. Consider: uint32x4_t test_mul(uint32x4_t a, uint32x4_t b) { return vmulq_n_u32(a, vaddvq_u32(b)); } We now generate: addv.4s s1, v1 mul.4s v0, v0, v1[0] instead of the previous: addv.4s s1, v1 fmov w8, s1 dup.4s v1, w8 mul.4s v0, v1, v0 rdar://20044838 llvm-svn: 231840
* [AArch64] Remove integer INSvi*lane patterns. NFCI.Ahmed Bougacha2015-03-101-4/+0
| | | | | | | | | | | | | | | | | | | | | | | Most are redundant, and they never seem to fire. The V128 integer patterns already exist in the INS multiclass. The duplicates only fire when the vector index type isn't i64, because they accept "imm" instead of an explicit "i64", as the instruction definition patterns do. TLI::getVectorIdxTy is i64 on AArch64, so this should never happen. Also, one of them had a typo: for i64, INSvi32lane was used. I noticed because I mistakenly used an explicit i32 as the idx type, and got ins.s for an i64 vector_insert. The V64 patterns also don't seem to ever fire, as V64 vector extract/insert are legalized to V128. The equivalent float patterns are unique and useful, so keep them. No functional change intended; none exhibited on the LIT and LNT tests. llvm-svn: 231838
* Don't evaluate rend() on every iteration of the loop.Chad Rosier2015-03-101-1/+3
| | | | llvm-svn: 231837
* LoopAccessAnalysis: Silence -Wreturn-type diagnostic from GCCDavid Majnemer2015-03-101-0/+3
| | | | llvm-svn: 231836
* Don't use LLVM_LIBRARY_VISIBILITY in cpp files.Benjamin Kramer2015-03-101-1/+3
| | | | llvm-svn: 231831
* [AsmPrinter][TLOF] Reintroduce AArch64 testBruno Cardoso Lopes2015-03-101-11/+12
| | | | | | | | | | | | Follow up from r231505. Fix the non-determinism by using a MapVector and reintroduce the AArch64 testcase. Defer deleting the got candidates up to the end and remove them in a bulk, avoiding linear time removal of each element. Thanks to Renato Golin for trying it out on other platforms. llvm-svn: 231830
* [Hexagon] Adding nodes for PIC support.Colin LeMahieu2015-03-102-9/+55
| | | | llvm-svn: 231829
* [Hexagon] Adding DuplexInst instruction format and duplex class defs.Colin LeMahieu2015-03-103-3/+116
| | | | llvm-svn: 231828
* Change the generation of the vmuluwm instruction to be based on the MUL opcode.Kit Barton2015-03-102-3/+9
| | | | | | Phabricator review: http://reviews.llvm.org/D8185 llvm-svn: 231827
* remove function names from comments; NFCSanjay Patel2015-03-101-29/+26
| | | | llvm-svn: 231826
* [Hexagon] Adding nodes for vector insert/extract lowering.Colin LeMahieu2015-03-102-0/+76
| | | | llvm-svn: 231825
* [Hexagon] Renaming HexagonJT to JT and adding CP for constantpool.Colin LeMahieu2015-03-103-6/+9
| | | | llvm-svn: 231824
* Change the datatype of DwarfExpression::Emit(Un)Signed to (u)int64_tAdrian Prantl2015-03-103-10/+10
| | | | | | so it matches the one used by ByteStreamer::Emit(U|S)LEB128. llvm-svn: 231823
* NVPTX: move NVPTXAllocaHoisting into the cpp fileBenjamin Kramer2015-03-103-34/+35
| | | | | | Also initialize without using static initialization. llvm-svn: 231822
* [LAA-memchecks] Comment improvementAdam Nemet2015-03-101-2/+2
| | | | | | I forgot to roll this into r231816. It was requested by Hal in D8122. llvm-svn: 231821
* Enable loop-rotate before loop-vectorize by defaultMichael Zolotukhin2015-03-101-2/+1
| | | | llvm-svn: 231820
* [LAA-memchecks 3/3] Introduce pointer partitions for memchecksAdam Nemet2015-03-101-10/+36
| | | | | | | | | | | | | | | | | This is the final patch that actually introduces the new parameter of partition mapping to RuntimePointerCheck::needsChecking. Another API (LAI::getInstructionsForAccess) is also exposed that helps to map pointers to instructions because ultimately we partition instructions. The WIP version of the Loop Distribution pass in D6930 has been adapted to use all this. See for example, how InstrPartitionContainer::computePartitionSetForPointers sets up the partitions using the above API and then calls to LAI::addRuntimeCheck with the pointer partitions. llvm-svn: 231818
* [LAA-memchecks 2/3] Move number of memcheck threshold checking to LVAdam Nemet2015-03-102-28/+16
| | | | | | | | | | | | | | | | | | | | | Now the analysis won't "fail" if the memchecks exceed the threshold. It is the transform pass' responsibility to perform the check. This allows the transform pass to further analyze/eliminate the memchecks. E.g. in Loop distribution we only need to check pointers that end up in different partitions. Note that there is a slight change of functionality here. The logic in analyzeLoop is that if dependence checking fails due to non-constant distance between the pointers, another attempt is made to prove safety of the dependences purely using run-time checks. Before this patch we could fail the loop due to exceeding the memcheck threshold after the first step, now we only check the threshold in the client after the full analysis. There is no measurable compile-time effect but I wanted to record this here. llvm-svn: 231817
* [LAA-memchecks 1/3] Split out NumComparisons checks. NFCAdam Nemet2015-03-101-22/+30
| | | | | | | | | | | | | | | The check for the number of memchecks will be moved to the client of this analysis. Besides allowing for transform-specific thresholds, this also lets Loop Distribution post-process the memchecks; Loop Distribution only needs memchecks between pointers of different partitions. The motivation for this first patch is to untangle the CanDoRT check from the NumComparison check before moving the NumComparison part. CanDoRT means that we couldn't determine the bounds for the pointer. Note that NumComparison is set independent of this flag. llvm-svn: 231816
* remove names from comments; NFCSanjay Patel2015-03-101-11/+9
| | | | llvm-svn: 231813
* fix typos; NFCSanjay Patel2015-03-101-2/+2
| | | | llvm-svn: 231812
* NVPTX: Remove copy of LLVMInitializeNVPTXAsmPrinter.Benjamin Kramer2015-03-101-7/+0
| | | | | | | | If anyone is using this for some strange reason, LLVMInitializeNVPTXAsmPrinter does exactly the same thing and is what other LLVM tools are calling. llvm-svn: 231810
* Hexagon: Remove unused InstrMapping.Benjamin Kramer2015-03-101-8/+0
| | | | llvm-svn: 231809
* [LoopAccesses 3/3] Print the dependences with -analyzeAdam Nemet2015-03-101-1/+20
| | | | | | | | | | The dependences are now expose through the new getInterestingDependences API so we can use that with -analyze too and fix the FIXME. This lets us remove the test that relied on -debug to check the dependences. llvm-svn: 231807
* [LoopAccesses 2/3] Allow querying of interesting dependencesAdam Nemet2015-03-101-20/+100
| | | | | | | | | | | | | | | | | | | | | | | Gather an array of interesting dependences rather than just failing after the first unsafe one and regarding the loop unsafe. Loop Distribution needs to be able to collect all dependences in order to isolate the dependence cycles into their own partition. Since the dependence checking algorithm is quadratic in terms of accesses sharing the same underlying pointer, I am applying a cut-off threshold (MaxInterestingDependence). Exceeding that, the logic reverts back to the original approach deeming the loop unsafe upon encountering the first unsafe dependence. The main idea of the patch is to split isDepedent from directly answering the question whether the dep is safe for vectorization to return a dependence type which then gets mapped to old boolean result using Dependence::isSafeForVectorization. Tested that this was compile-time neutral on SpecINT2006 LTO bitcode inputs. No assembly change on the testsuite including external. llvm-svn: 231806
* [LoopAccesses 1/3] Expose MemoryDepChecker to LAA usersAdam Nemet2015-03-101-127/+8
| | | | | | | | | | | | LoopDistribution needs to query various results of the dependence analysis. This series will expose some more APIs and state of the dependence checker. This patch is a simple one to just expose the DepChecker instance. The set is compile-time neutral measured with LTO bitcode files of SpecINT2006. Also there is no assembly change on the testsuite. llvm-svn: 231805
* Store an optional section start label in MCSection.Rafael Espindola2015-03-1012-137/+92
| | | | | | | | | | | | This makes code that uses section relative expressions (debug info) simpler and less brittle. This is still a bit awkward as the symbol is created late and has to be stored in a mutable field. I will move the symbol creation earlier in the next patch. llvm-svn: 231802
* remove function names from comments; NFCSanjay Patel2015-03-101-11/+9
| | | | llvm-svn: 231801
* Teach lowering to correctly handle invoke statepoint and gc results tied to ↵Igor Laevsky2015-03-103-22/+92
| | | | | | | | | | | them. Note that we still can not lower gc.relocates for invoke statepoints. Also it extracts getCopyFromRegs helper function in SelectionDAGBuilder as we need to be able to customize type of the register exported from basic block during lowering of the gc.result. (Resubmitting this change after not being able to reproduce buildbot failure) Differential Revision: http://reviews.llvm.org/D7760 llvm-svn: 231800
* [BranchFolding] Remove MMOs during tail merge to preserve dependencies.Chad Rosier2015-03-101-0/+57
| | | | | | | | | | | | | | | | | | When tail merging it may be necessary to remove MMOs from memory operations to ensures later passes (e.g., MI sched) conservatively compute dependencies. Currently, we only remove the MMO from the common tail if the MMO doesn't match with the relative instruction in the non-common tail(s). A more robust solution would be to add multiple MMOs from the duplicate MIs to the new MI. Currently ScheduleDAGInstrs.cpp ignores all MMOs on instructions with multiple MMOs, so this solution is equivalent for the time being. No test case included as this is incredibly difficult to reproduce. Patch was a collaborative effort between Ana Pazos and myself. Phabricator: http://reviews.llvm.org/D7769 llvm-svn: 231799
* R600/SI: Add _IDXEN and _BOTHEN variants for buffer_storeTom Stellard2015-03-101-0/+15
| | | | llvm-svn: 231798
* R600/SI: Re-order MUBUF operands to match asm strings.Tom Stellard2015-03-103-20/+19
| | | | llvm-svn: 231797
* R600/SI: Move kill flag to second instruction when splitting SMRDTom Stellard2015-03-101-5/+12
| | | | | | | This fixes a machine verifier error in the salu-to-valu.ll, which would have been exposed by a future commit. llvm-svn: 231796
* R600/SI: Add 32-bit encoding of v_cndmask_b32Tom Stellard2015-03-103-6/+25
| | | | | | | This was done by refactoring the v_cndmask_b32 tablegen definition to use inherit from VOP2Inst. llvm-svn: 231795
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