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* Fold predicable instructions into MOVCC / t2MOVCC.Jakob Stoklund Olesen2012-08-155-2/+104
| | | | | | | | | | | | | | The ARM select instructions are just predicated moves. If the select is the only use of an operand, the instruction defining the operand can be predicated instead, saving one instruction and decreasing register pressure. This implementation can turn AND/ORR/EOR instructions into their corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to predicate any instruction, but we don't yet support predicated instructions in SSA form. llvm-svn: 161994
* Remove dead flag.Bill Wendling2012-08-151-9/+3
| | | | llvm-svn: 161990
* Fixed a problem in the JIT memory allocator whereSean Callanan2012-08-151-0/+3
| | | | | | | | | | allocations of executable memory would not be padded to account for the size of the allocation header. This resulted in undersized allocations, meaning that when the allocation was written to later the next allocation's header would be corrupted. llvm-svn: 161984
* Properly test the LLVM_USE_RVALUE_REFERENCES macro.Michael J. Spencer2012-08-152-2/+2
| | | | llvm-svn: 161978
* [PathV2] Add mapped_file_region. Implementation for Windows and POSIX.Michael J. Spencer2012-08-152-0/+311
| | | | llvm-svn: 161976
* Fix another roundToIntegral bug where very large values could become ↵Owen Anderson2012-08-151-0/+6
| | | | | | infinity. Problem and solution identified by Steve Canon. llvm-svn: 161969
* Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows ↵Evan Cheng2012-08-154-2/+50
| | | | | | unaligned access. rdar://12091029 llvm-svn: 161962
* Fix typo in comment.Owen Anderson2012-08-151-1/+1
| | | | llvm-svn: 161956
* Add missing Rfalse operand to the predicated pseudo-instructions.Jakob Stoklund Olesen2012-08-153-28/+41
| | | | | | | | | | | | | | | | | | | | | | | When predicating this instruction: Rd = ADD Rn, Rm We need an extra operand to represent the value given to Rd when the predicate is false: Rd = ADDCC Rfalse, Rn, Rm, pred The Rd and Rfalse operands are different registers while in SSA form. Rfalse is tied to Rd to make sure they get the same register during register allocation. Previously, Rd and Rn were tied, but that is not required. Compare to MOVCC: Rd = MOVCC Rfalse, Rtrue, pred llvm-svn: 161955
* Set the branch probability of branching to the 'normal' destination of an invokeBill Wendling2012-08-151-2/+30
| | | | | | | | | | instruction to something absurdly high, while setting the probability of branching to the 'unwind' destination to the bare minimum. This should set cause the normal destination's invoke blocks to be moved closer to the invoke. PR13612 llvm-svn: 161944
* [asan] implement --asan-always-slow-path, which is a part of the improvement ↵Kostya Serebryany2012-08-151-2/+5
| | | | | | to handle unaligned partially OOB accesses. See http://code.google.com/p/address-sanitizer/issues/detail?id=100 llvm-svn: 161937
* Fix a problem with APFloat::roundToIntegral where it would return incorrect ↵Owen Anderson2012-08-151-0/+12
| | | | | | results for negative inputs to trunc. Add unit tests to verify this behavior. llvm-svn: 161929
* fix infinite loop in instcombine with more than 4GB memcpyMichael Liao2012-08-151-6/+4
| | | | | | | | | | | | - memcpy size is wrongly truncated into 32-bit and treat 8GB memcpy is 0-sized memcpy - as 0-sized memcpy/memset is already removed before SimplifyMemTransfer and SimplifyMemSet in visitCallInst, replace 0 checking with assertions. - replace getZExtValue() with getLimitedValue() according to Eli Friedman llvm-svn: 161923
* Fix a typo that led to a failure to correctly verify bitcast instructions.Nick Lewycky2012-08-151-1/+1
| | | | | | Patch by Stephen Hines! llvm-svn: 161921
* Fix undefined behavior: don't perform array indexing through a potentially nullRichard Smith2012-08-151-1/+2
| | | | | | pointer. llvm-svn: 161919
* The names of VFP variants of half-to-float conversion instructions wereAnton Korobeynikov2012-08-141-7/+7
| | | | | | | | reversed. This leads to wrong codegen for float-to-half conversion intrinsics which are used to support storage-only fp16 type. NEON variants of same instructions are fine. llvm-svn: 161907
* This needs braces. Spotted by Bill.Eric Christopher2012-08-141-1/+2
| | | | llvm-svn: 161906
* minor fix of X86ISD::VSEXT_MOVL dumpMichael Liao2012-08-141-0/+1
| | | | llvm-svn: 161902
* fix PR11334Michael Liao2012-08-144-0/+99
| | | | | | | | | | | | - FP_EXTEND only support extending from vectors with matching elements. This results in the scalarization of extending to v2f64 from v2f32, which will be legalized to v4f32 not matching with v2f64. - add X86-specific VFPEXT supproting extending from v4f32 to v2f64. - add BUILD_VECTOR lowering helper to recover back the original extending from v4f32 to v2f64. - test case is enhanced to include different vector width. llvm-svn: 161894
* Switch the fixed-length disassembler to be table-driven.Jim Grosbach2012-08-142-419/+437
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
* Fix the construction of the magic constant for roundToIntegral to be 64-bit ↵Owen Anderson2012-08-141-2/+2
| | | | | | safe. Fixes c-torture/execute/990826-0.c llvm-svn: 161885
* [asan] insert crash basic blocks inline as opposed to inserting them at the ↵Kostya Serebryany2012-08-141-30/+27
| | | | | | end of the function. This doesn't seem to fix or break anything, but is considered to be more friendly to downstream passes llvm-svn: 161870
* Factor duplicate calls to getUNDEF in several functions.Craig Topper2012-08-141-10/+10
| | | | llvm-svn: 161860
* Re-factor intrinsic lowering to combine common parts of similar intrinsics. ↵Craig Topper2012-08-141-34/+133
| | | | | | Reduces compiled code size a little bit. llvm-svn: 161859
* Change greater than to greater than or equal so that an identical sized ↵Craig Topper2012-08-141-1/+1
| | | | | | store to the same offset is treated as completing overwriting. llvm-svn: 161857
* Fix undefined behavior: binding null pointer to reference. No functionality ↵Richard Smith2012-08-141-1/+1
| | | | | | change. llvm-svn: 161853
* During the CodeGenPrepare we often lower intrinsics (such as objsize)Nadav Rotem2012-08-141-0/+39
| | | | | | | | | | | and allow some optimizations to turn conditional branches into unconditional. This commit adds a simple control-flow optimization which merges two consecutive basic blocks which are connected by a single edge. This allows the codegen to operate on larger basic blocks. rdar://11973998 llvm-svn: 161852
* Grammar.Eric Christopher2012-08-141-1/+1
| | | | llvm-svn: 161851
* Typo.Eric Christopher2012-08-141-1/+1
| | | | llvm-svn: 161826
* Add a roundToIntegral method to APFloat, which can be parameterized over ↵Owen Anderson2012-08-133-0/+86
| | | | | | various rounding modes. Use this to implement SelectionDAG constant folding of FFLOOR, FCEIL, and FTRUNC. llvm-svn: 161807
* Transfer weights in transferSuccessorsAndUpdatePHIs().Jakob Stoklund Olesen2012-08-131-5/+7
| | | | llvm-svn: 161805
* Print out MachineBasicBlock successor weights when available.Jakob Stoklund Olesen2012-08-131-1/+4
| | | | llvm-svn: 161804
* LICM uses AliasSet information to hoist and sink instructions. However, ↵Nadav Rotem2012-08-131-0/+5
| | | | | | | | | | | | other passes, such as LoopRotate may invalidate its AliasSet because SSAUpdater does not update the AliasSet properly. This patch teaches SSAUpdater to notify AliasSet that it made changes. The testcase in PR12901 is too big to be useful and I could not reduce it to a normal size. rdar://11872059 PR12901 llvm-svn: 161803
* MemoryDependenceAnalysis attempts to find the first memory dependency for ↵Nadav Rotem2012-08-131-2/+7
| | | | | | | | | | | function calls. Currently, if GetLocation reports that it did not find a valid pointer (this is the case for volatile load/stores), we ignore the result. This patch adds code to handle the cases where we did not obtain a valid pointer. rdar://11872864 PR12899 llvm-svn: 161802
* Remove the TII::scheduleTwoAddrSource() hook.Jakob Stoklund Olesen2012-08-133-58/+0
| | | | | | | | | | | | | | | It never does anything when running 'make check', and it get's in the way of updating live intervals in 2-addr. The hook was originally added to help form IT blocks in Thumb2 code before register allocation, but the pass ordering has changed since then, and we run if-conversion after register allocation now. When the MI scheduler is enabled, there will be no less than two schedulers between 2-addr and Thumb2ITBlockPass, so this hook is unlikely to help anything. llvm-svn: 161794
* ARM: enable struct byval for AAPCS-VFP.Manman Ren2012-08-131-0/+3
| | | | | | | | This change is to be enabled in clang. rdar://9877866 llvm-svn: 161789
* Whitespace cleanup.Bill Wendling2012-08-131-7/+7
| | | | llvm-svn: 161788
* Count triangles and diamonds in early if-conversion.Jakob Stoklund Olesen2012-08-131-0/+16
| | | | llvm-svn: 161783
* Delete dead typedef.Jakob Stoklund Olesen2012-08-131-2/+0
| | | | llvm-svn: 161782
* Handle extra Tail predecessors in if-conversion.Jakob Stoklund Olesen2012-08-131-20/+67
| | | | | | | | It is still possible to if-convert if the tail block has extra predecessors, but the tail phis must be rewritten instead of being removed. llvm-svn: 161781
* [Hexagon] Don't mark callee saved registers as clobbered by a tail callArnold Schwaighofer2012-08-131-9/+3
| | | | | | | | | | This was causing unnecessary spills/restores of callee saved registers. Fixes PR13572. Patch by Pranav Bhandarkar! llvm-svn: 161778
* Do not optimize (or (and X,Y), Z) into BFI and other sequences if the AND ↵Nadav Rotem2012-08-131-1/+5
| | | | | | | | ISDNode has more than one user. rdar://11876519 llvm-svn: 161775
* X86: move Int_CVTSD2SSrr, Int_CVTSI2SSrr, Int_CVTSI2SDrr, Int_CVTSS2SDrr fromManman Ren2012-08-131-6/+6
| | | | | | | | | OpTbl1 to OpTbl2 since they have 3 operands and the last operand can be changed to a memory operand. PR13576 llvm-svn: 161769
* Add support for the %H output modifier.Eric Christopher2012-08-131-2/+15
| | | | | | Patch by Weiming Zhao. llvm-svn: 161768
* X86: when auto-detecting the subtarget features, make sure use IsIntel to detectManman Ren2012-08-131-2/+2
| | | | | | Nehalem, Westmere and Sandy Bridge. AMD also has processor family 6. llvm-svn: 161763
* [asan] remove the code for --asan-merge-callbacks as it appears to be a bad ↵Kostya Serebryany2012-08-131-78/+8
| | | | | | idea. (partly related to Bug 13225) llvm-svn: 161757
* Use correct loads for vector types during extending-load operations.Tim Northover2012-08-131-36/+36
| | | | | | | | Previously, we used VLD1.32 in all cases, however there are both 16 and 64-bit accesses being selected, so we need to use an appropriate width load in those cases. llvm-svn: 161748
* Tidy up VSETCC lowering code a bit more by adding an llvm_unreachable and ↵Craig Topper2012-08-131-7/+9
| | | | | | putting an a couple if conditions in a better order. llvm-svn: 161746
* Refactor code a bit to share commonalities. No functional change intended.Craig Topper2012-08-131-20/+21
| | | | llvm-svn: 161745
* Fix an unused variable warning from r161742.Craig Topper2012-08-131-3/+0
| | | | llvm-svn: 161743
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