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* This patch addresses PR13949.Bill Schmidt2012-10-161-6/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the PowerPC 64-bit ELF Linux ABI, aggregates of size less than 8 bytes are to be passed in the low-order bits ("right-adjusted") of the doubleword register or memory slot assigned to them. A previous patch addressed this for aggregates passed in registers. However, small aggregates passed in the overflow portion of the parameter save area are still being passed left-adjusted. The fix is made in PPCTargetLowering::LowerCall_Darwin_Or_64SVR4 on the caller side, and in PPCTargetLowering::LowerFormalArguments_64SVR4 on the callee side. The main fix on the callee side simply extends existing logic for 1- and 2-byte objects to 1- through 7-byte objects, and correcting a constant left over from 32-bit code. There is also a fix to a bogus calculation of the offset to the following argument in the parameter save area. On the caller side, again a constant left over from 32-bit code is fixed. Additionally, some code for 1, 2, and 4-byte objects is duplicated to handle the 3, 5, 6, and 7-byte objects for SVR4 only. The LowerCall_Darwin_Or_64SVR4 logic is getting fairly convoluted trying to handle both ABIs, and I propose to separate this into two functions in a future patch, at which time the duplication can be removed. The patch adds a new test (structsinmem.ll) to demonstrate correct passing of structures of all seven sizes. Eight dummy parameters are used to force these structures to be in the overflow portion of the parameter save area. As a side effect, this corrects the case when aggregates passed in registers are saved into the first eight doublewords of the parameter save area: Previously they were stored left-justified, and now are properly stored right-justified. This requires changing the expected output of existing test case structsinregs.ll. llvm-svn: 166022
* Issue:Stepan Dyatkovskiy2012-10-163-12/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stack is formed improperly for long structures passed as byval arguments for EABI mode. If we took AAPCS reference, we can found the next statements: A: "If the argument requires double-word alignment (8-byte), the NCRN (Next Core Register Number) is rounded up to the next even register number." (5.5 Parameter Passing, Stage C, C.3). B: "The alignment of an aggregate shall be the alignment of its most-aligned component." (4.3 Composite Types, 4.3.1 Aggregates). So if we have structure with doubles (9 double fields) and 3 Core unused registers (r1, r2, r3): caller should use r2 and r3 registers only. Currently r1,r2,r3 set is used, but it is invalid. Callee VA routine should also use r2 and r3 regs only. All is ok here. This behaviour is guessed by rounding up SP address with ADD+BFC operations. Fix: Main fix is in ARMTargetLowering::HandleByVal. If we detected AAPCS mode and 8 byte alignment, we waste odd registers then. P.S.: I also improved LDRB_POST_IMM regression test. Since ldrb instruction will not generated by current regression test after this patch. llvm-svn: 166018
* Reapply r165661, Patch by Shuxin Yang <shuxin.llvm@gmail.com>.NAKAMURA Takumi2012-10-161-0/+41
| | | | | | | | | | | | | | | | | | | | | | | Original message: The attached is the fix to radar://11663049. The optimization can be outlined by following rules: (select (x != c), e, c) -> select (x != c), e, x), (select (x == c), c, e) -> select (x == c), x, e) where the <c> is an integer constant. The reason for this change is that : on x86, conditional-move-from-constant needs two instructions; however, conditional-move-from-register need only one instruction. While the LowerSELECT() sounds to be the most convenient place for this optimization, it turns out to be a bad place. The reason is that by replacing the constant <c> with a symbolic value, it obscure some instruction-combining opportunities which would otherwise be very easy to spot. For that reason, I have to postpone the change to last instruction-combining phase. The change passes the test of "make check-all -C <build-root/test" and "make -C project/test-suite/SingleSource". Original message since r165661: My previous change has a bug: I negated the condition code of a CMOV, and go ahead creating a new CMOV using the *ORIGINAL* condition code. llvm-svn: 166017
* Cleanup whitespace.Bill Wendling2012-10-161-1/+2
| | | | llvm-svn: 166016
* Move X86MCInstLower class definition into implementation file. It's not ↵Craig Topper2012-10-163-54/+25
| | | | | | needed outside. llvm-svn: 166014
* Cleanup whitespace.Bill Wendling2012-10-161-37/+35
| | | | llvm-svn: 166013
* Have AttributesImpl defriend the Attributes class.Bill Wendling2012-10-162-3/+3
| | | | llvm-svn: 166012
* Have AttrBuilder defriend the Attributes class.Bill Wendling2012-10-161-3/+3
| | | | llvm-svn: 166011
* Use the Attributes::get method which takes an AttrVal value directly to ↵Bill Wendling2012-10-163-34/+13
| | | | | | simplify the code a bit. No functionality change. llvm-svn: 166009
* Put simple c'tors inline.Bill Wendling2012-10-161-6/+1
| | | | llvm-svn: 166008
* Pass in the context to the Attributes::get method.Bill Wendling2012-10-161-1/+1
| | | | llvm-svn: 166007
* Fix filename in file header.Craig Topper2012-10-161-1/+1
| | | | llvm-svn: 166004
* misched: Added handleMove support for updating all kill flags, not just for ↵Andrew Trick2012-10-162-8/+21
| | | | | | | | | allocatable regs. This is a medium term workaround until we have a more robust solution in the form of a register liveness utility for postRA passes. llvm-svn: 166001
* Remove unused BitVectors from getAllocatableSet().Jakob Stoklund Olesen2012-10-163-9/+1
| | | | llvm-svn: 165999
* Remove RegisterClassInfo::isReserved() and isAllocatable().Jakob Stoklund Olesen2012-10-156-17/+18
| | | | | | Clients can use the equivalent functions in MRI. llvm-svn: 165990
* Add __builtin_setjmp/_longjmp supprt in X86 backendMichael Liao2012-10-157-1/+260
| | | | | | | | | | | - Besides used in SjLj exception handling, __builtin_setjmp/__longjmp is also used as a light-weight replacement of setjmp/longjmp which are used to implementation continuation, user-level threading, and etc. The support added in this patch ONLY addresses this usage and is NOT intended to support SjLj exception handling as zero-cost DWARF exception handling is used by default in X86. llvm-svn: 165989
* Remove LIS::isAllocatable() and isReserved() helpers.Jakob Stoklund Olesen2012-10-154-7/+5
| | | | | | All callers can simply use the corresponding MRI functions. llvm-svn: 165985
* Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen2012-10-1510-40/+25
| | | | | | | Using the cached bit vector in MRI avoids comstantly allocating and recomputing the reserved register bit vector. llvm-svn: 165983
* Freeze the reserved registers as soon as isel is complete.Jakob Stoklund Olesen2012-10-152-9/+10
| | | | | | | | | | | | | Also provide an MRI::getReservedRegs() function to access the frozen register set, and isReserved() and isAllocatable() methods to test individual registers. The various implementations of TRI::getReservedRegs() are quite complicated, and many passes need to look at the reserved register set. This patch makes it possible for these passes to use the cached copy in MRI, avoiding a lot of malloc traffic and repeated calculations. llvm-svn: 165982
* ARM: v1i64 and v2i64 VBSL intrinsic support.Jim Grosbach2012-10-151-0/+17
| | | | | | rdar://12502028 llvm-svn: 165981
* Move the Attributes::Builder outside of the Attributes class and into its ↵Bill Wendling2012-10-1516-71/+109
| | | | | | own class named AttrBuilder. No functionality change. llvm-svn: 165960
* [ms-inline asm] If we parsed a statement and the opcode is valid, then it's ↵Chad Rosier2012-10-152-5/+5
| | | | | | an instruction. llvm-svn: 165955
* Make sure we iterate over newly created instructions. Fixes pr13625. Testcase toRafael Espindola2012-10-151-0/+5
| | | | | | follow in one sec. llvm-svn: 165951
* misched: ILP scheduler for experimental heuristics.Andrew Trick2012-10-152-20/+197
| | | | llvm-svn: 165950
* [ms-inline asm] Update the end loc for ParseIntelMemOperand.Chad Rosier2012-10-151-0/+1
| | | | llvm-svn: 165947
* [ms-inline asm] Add a few new APIs to the AsmParser class in support of MS-StyleChad Rosier2012-10-151-13/+34
| | | | | | | | | inline assembly. For the time being, these will be called directly by clang. However, in the near future I expect these to be sunk back into the MC layer and more basic APIs (e.g., getClobbers(), getConstraints(), etc.) will be called by clang. llvm-svn: 165946
* [ms-inline asm] Use incoming argument rather than hard coding to false.Chad Rosier2012-10-151-1/+1
| | | | llvm-svn: 165945
* Resubmit the changes to llvm core to update the functions to support ↵Micah Villmow2012-10-1535-92/+144
| | | | | | different pointer sizes on a per address space basis. llvm-svn: 165941
* PowerPC: add EmitTCEntry class for TOC creationAdhemerval Zanella2012-10-154-2/+23
| | | | | | | This patch replaces the EmitRawText by a EmitTCEntry class (specialized for each Streamer) in PowerPC64 TOC entry creation. llvm-svn: 165940
* [asan] make AddressSanitizer to be a FunctionPass instead of ModulePass. ↵Kostya Serebryany2012-10-151-63/+52
| | | | | | This will simplify chaining other FunctionPasses with asan. Also some minor cleanup llvm-svn: 165936
* Update the memcpy rewriting to fully support widened int rewriting. ThisChandler Carruth2012-10-151-8/+26
| | | | | | | | includes extracting ints for copying elsewhere and inserting ints when copying into the alloca. This should fix the CanSROA assertion coming out of Clang's regression test suite. llvm-svn: 165931
* Follow-up fix to r165928: handle memset rewriting for widened integers,Chandler Carruth2012-10-151-30/+25
| | | | | | | and generally clean up the memset handling. It had rotted a bit as the other rewriting logic got polished more. llvm-svn: 165930
* Fixed PR13938: the ARM backend was crashing because it couldn't select a ↵Silviu Baranga2012-10-151-2/+19
| | | | | | VDUPLANE node with the vector input size different from the output size. This was bacause the BUILD_VECTOR lowering code didn't check that the size of the input vector was correct for using VDUPLANE. llvm-svn: 165929
* First major step toward addressing PR14059. This teaches SROA to handleChandler Carruth2012-10-151-53/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cases where we have partial integer loads and stores to an otherwise promotable alloca to widen[1] those loads and stores to cover the entire alloca and bitcast them into the appropriate type such that promotion can proceed. These partial loads and stores stem from an annoying confluence of ARM's calling convention and ABI lowering and the FCA pre-splitting which takes place in SROA. Clang lowers a { double, double } in-register function argument as a [4 x i32] function argument to ensure it is placed into integer 32-bit registers (a really unnerving implicit contract between Clang and the ARM backend I would add). This results in a FCA load of [4 x i32]* from the { double, double } alloca, and SROA decomposes this into a sequence of i32 loads and stores. Inlining proceeds, code gets folded, but at the end of the day, we still have i32 stores to the low and high halves of a double alloca. Widening these to be i64 operations, and bitcasting them to double prior to loading or storing allows promotion to proceed for these allocas. I looked quite a bit changing the IR which Clang produces for this case to be more friendly, but small changes seem unlikely to help. I think the best representation we could use currently would be to pass 4 i32 arguments thereby avoiding any FCAs, but that would still require this fix. It seems like it might eventually be nice to somehow encode the ABI register selection choices outside of the parameter type system so that the parameter can be a { double, double }, but the CC register annotations indicate that this should be passed via 4 integer registers. This patch does not address the second problem in PR14059, which is the reverse: when a struct alloca is loaded as a *larger* single integer. This patch also does not address some of the code quality issues with the FCA-splitting. Those don't actually impede any optimizations really, but they're on my list to clean up. [1]: Pedantic footnote: for those concerned about memory model issues here, this is safe. For the alloca to be promotable, it cannot escape or have any use of its address that could allow these loads or stores to be racing. Thus, widening is always safe. llvm-svn: 165928
* Hoist the canConvertValue predicate and the convertValue transform outChandler Carruth2012-10-151-44/+52
| | | | | | | into static helper functions. They're really quite generic and are going to be needed elsewhere shortly. llvm-svn: 165927
* Add an enum for the return and function indexes into the AttrListPtr object. ↵Bill Wendling2012-10-1510-69/+109
| | | | | | This gets rid of some magic numbers. llvm-svn: 165924
* Use a ::get method to create the attribute from Attributes::AttrVals instead ↵Bill Wendling2012-10-151-8/+7
| | | | | | of a constructor. llvm-svn: 165923
* Move the AttributesImpl header file into the VMCore directory so that it can ↵Bill Wendling2012-10-153-1/+57
| | | | | | be opaque. llvm-svn: 165920
* Attributes RewriteBill Wendling2012-10-1516-94/+134
| | | | | | | | | | Convert the internal representation of the Attributes class into a pointer to an opaque object that's uniqued by and stored in the LLVMContext object. The Attributes class then becomes a thin wrapper around this opaque object. Eventually, the internal representation will be expanded to include attributes that represent code generation options, etc. llvm-svn: 165917
* instcombine: Migrate strcmp and strncmp optimizationsMeador Inge2012-10-152-105/+99
| | | | | | | This patch migrates the strcmp and strncmp optimizations from the simplify-libcalls pass into the instcombine library call simplifier. llvm-svn: 165915
* Simplify code. No functionality change.Benjamin Kramer2012-10-141-5/+3
| | | | llvm-svn: 165904
* Unquadratize SetVector removal loops in DSE.Benjamin Kramer2012-10-141-27/+36
| | | | | | | | | Erasing from the beginning or middle of the vector is expensive, remove_if can do it in linear time even though it's a bit ugly without lambdas. No functionality change. llvm-svn: 165903
* Remove dead methods.Bill Wendling2012-10-141-8/+0
| | | | llvm-svn: 165902
* Remove operator cast method in favor of querying with the correct method.Bill Wendling2012-10-145-22/+39
| | | | llvm-svn: 165899
* Fix use after free when deleting attributes in a chained folding set.Benjamin Kramer2012-10-141-3/+5
| | | | | | Can't follow the intrusive linked list when the element is gone. llvm-svn: 165898
* Don't use the new syntax just yet.Bill Wendling2012-10-141-2/+2
| | | | llvm-svn: 165897
* Remove the bitwise AND operators from the Attributes class. Replace it with ↵Bill Wendling2012-10-144-14/+9
| | | | | | the equivalent from the builder class. llvm-svn: 165896
* Remove the bitwise assignment OR operator from the Attributes class. Replace ↵Bill Wendling2012-10-147-24/+35
| | | | | | it with the equivalent from the builder class. llvm-svn: 165895
* Remove the bitwise OR operator from the Attributes class. Replace it with ↵Bill Wendling2012-10-141-7/+9
| | | | | | the equivalent from the builder class. llvm-svn: 165894
* Remove the bitwise XOR operator from the Attributes class. Replace it with ↵Bill Wendling2012-10-143-7/+6
| | | | | | the equivalent from the builder class. llvm-svn: 165893
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