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* Delay creating an alias for @@@.Rafael Espindola2018-03-097-68/+30
| | | | | | | | | | | With this we only create an alias for @@@ once we know if it should use @ or @@. This avoids last minutes renames and hacks to handle MS names. This only handles the ELF writer. LTO still has issues with @@@ aliases. llvm-svn: 327160
* [X86][AVX] createVariablePermute - fix v2i64/v2f64 VPERMILPD index creation. Simon Pilgrim2018-03-091-0/+2
| | | | | | The input indices vector will put the index in bit0, but VPERMILPD actually selects off bit1 - so we need to scale accordingly. llvm-svn: 327159
* TableGen: Remove space at EOL in TGLexer.{h,cpp}Nicolai Haehnle2018-03-092-34/+34
| | | | | Change-Id: Ica5f39470174e85f173d3b6db95789033f75ce17 llvm-svn: 327158
* [X86][SSE] createVariablePermute - move source vector canonicalization to ↵Simon Pilgrim2018-03-091-8/+8
| | | | | | | | top of function. NFCI. This is to make it easier to return early from the switch statement with custom lowering. llvm-svn: 327157
* [AMDGPU] Supported ds_read_b128 generation; Widened vector length for local ↵Farhana Aleen2018-03-096-10/+33
| | | | | | | | | | | | | | | | | | | | address-space. Summary: Starting from GCN 2nd generation, ISA supports ds_read_b128 on top of ds_read_b64. This patch supports ds_read_b128 instruction pattern and generation of this instruction. In the vectorizer, this patch also widen the vector length so that vectorizer generates 128 bit loads for local address-space which gets translated to ds_read_b128. Since the performance benefit is not clear; compiler generates ds_read_b128 under -amdgpu-ds128. Author: FarhanaAleen Reviewed By: rampitec, arsenm Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D44210 llvm-svn: 327153
* [GISel]: Add helpers for easy building G_FCONSTANT along with matchersAditya Nandakumar2018-03-092-0/+22
| | | | | | | | | | | | | | | | | | Added helpers to build G_FCONSTANT, along with matching ConstantFP and unit tests for the same. Sample usage. auto MIB = Builder.buildFConstant(s32, 0.5); // Build IEEESingle For Matching the above const ConstantFP* Tmp; mi_match(DstReg, MRI, m_GFCst(Tmp)); https://reviews.llvm.org/D44128 reviewed by: volkan llvm-svn: 327152
* [JumpThreading] Don't restrict cast-traversal to i1Chad Rosier2018-03-091-3/+1
| | | | | | | | | | | | | | | | | | | In r263618, JumpThreading learned to look trough simple cast instructions, but only if the source of those cast instructions was a phi/cmp i1 (in an effort to limit compile time effects). I think this condition is too restrictive. For switches with limited value range, InstCombine will readily introduce an extra trunc instruction to a smaller integer type (e.g. from i8 to i2), leaving us in the somewhat perverse situation that jump-threading would work before running instcombine, but not after. Since instcombine produces this pattern, I think we need to consider it canonical and support it in JumpThreading. In general, for limiting recursion, I think the existing restriction to phi and cmp nodes should be sufficient to avoid looking through unprofitable chains of instructions. Patch by Keno Fischer! Differential Revision: https://reviews.llvm.org/D42262 llvm-svn: 327150
* [WebAssembly] Disallow weak undefined globals in the object formatNicholas Wilson2018-03-092-0/+8
| | | | | | | | This implements https://github.com/WebAssembly/tool-conventions/pull/47 Differential Revision: https://reviews.llvm.org/D44201 llvm-svn: 327146
* Revert "[PowerPC] LSR tunings for PowerPC"Stefan Pintilie2018-03-092-16/+0
| | | | | | | | Revert the rest of the LST tune commit. It seems that the LSR tune commit breaks internal tests. Reverting the commit. llvm-svn: 327143
* Tidyup comment that was destroyed by clang-format. NFCI.Simon Pilgrim2018-03-091-3/+4
| | | | llvm-svn: 327141
* [X86][SSE] createVariablePermute - move index vector canonicalization to top ↵Simon Pilgrim2018-03-091-11/+11
| | | | | | | | of function. NFCI. This is to make it easier to return early from the switch statement with custom lowering. llvm-svn: 327140
* [x86][aarch64] ask the backend whether it has a vector blend instructionSebastian Pop2018-03-092-24/+28
| | | | | | | | | | | | | The code to match and produce more x86 vector blends was enabled for all architectures even though the transform may pessimize the code for other architectures that do not provide a vector blend instruction. Added an aarch64 testcase to check that a VZIP instruction is generated instead of byte movs. Differential Revision: https://reviews.llvm.org/D44118 llvm-svn: 327132
* TableGen: Add a defset statementNicolai Haehnle2018-03-094-9/+97
| | | | | | | | | | | | | | | | | | | | | | | | Allows capturing a list of concrete instantiated defs. This can be combined with foreach to create parallel sets of def instantiations with less repetition in the source. This purpose is largely also served by multiclasses, but in some cases multiclasses can't be used. The motivating example for this change is having a large set of intrinsics, which are generated from the IntrinsicsBackend.td file included by Intrinsics.td, and a corresponding set of instruction selection patterns, which are generated via the backend's .td files. Multiclasses cannot be used to eliminate the redundancy in this case, because a multiclass cannot span both LLVM's common .td files and the backend .td files at the same time. Change-Id: I879e35042dceea542a5e6776fad23c5e0e69e76b Differential revision: https://reviews.llvm.org/D44109 llvm-svn: 327121
* TableGen: Allow arbitrary list values as ranges of foreachNicolai Haehnle2018-03-092-27/+25
| | | | | | | | | The changes to FieldInit are required to make field references (Def.field) work inside a ForeachDeclaration: previously, Def.field wasn't resolved immediately when Def was already a fully resolved DefInit. Change-Id: I9875baec2fc5aac8c2b249e45b9cf18c65ae699b llvm-svn: 327120
* TableGen: Remove unused ParseForeachModeNicolai Haehnle2018-03-092-3/+2
| | | | | | | | | | | | | | | Use the default ParseValueMode instead of ParseForeachMode when parsing the rule ForeachDeclaration ::= ID '=' '[' ValueList ']' because the only difference between the two is how an open brace '{' is handled at the end. In the context of foreach, the 'in' keyword will appear after the ForeachDeclaration, so this special handling of '{' is not required. Change-Id: I4d86bb73bab9ec26752e1273e5213df77cf28d1d llvm-svn: 327119
* TableGen: More helpful error messagesNicolai Haehnle2018-03-091-8/+22
| | | | | Change-Id: Ic78afd0cd765fdb4cf1b7ecfb6bba22653ce6d29 llvm-svn: 327118
* TableGen: add !isa operationNicolai Haehnle2018-03-094-1/+92
| | | | | | | | Change-Id: Iddb724c3ae706d82933a2d82c91d07e0e36b30e3 Differential revision: https://reviews.llvm.org/D44105 llvm-svn: 327117
* [DebugInfo/AccelTable] Fix inconsistency in getDIEOffset implementationsPavel Labath2018-03-091-8/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Even though the getDIEOffset offset function was common for the two accelerator table implementations, it was doing two different things: for the Apple tables, it was returning the die offset relative to the start of the section, whereas for DWARF v5 tables, it was relative to the start of the CU. I resolve this by renaming the function to getDIESectionOffset to make it obvious what the function returns, and change the DWARF implementation to return the section offset. I also keep the CU-relative accessor, but only in the DWARF implementation (there is no way to get this information for the Apple tables). This was not caught by existing tests because the hand-written inputs also erroneously used section offsets instead of CU-relative ones. While looking at this, I noticed that the Apple implementation was not fully correct either -- the header contains a DIEOffsetBase field, which should be added to offsets encoded with the DW_FORM_ref*** family, but this was not being used. This went unnoticed because all current writers set this field to zero anyway. I fix this as well and add a hand-written test which demonstrates the issue. Reviewers: JDevlieghere, dblaikie Subscribers: aprantl, llvm-commits Differential Revision: https://reviews.llvm.org/D44202 llvm-svn: 327116
* [LV] Fix vectorizer's isUniform() abuse triggers assert in SCEVRenato Golin2018-03-091-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes PR36311. See more detailed analysis in https://bugs.llvm.org/show_bug.cgi?id=36311. isUniform() information is recomputed after LV started transforming the underlying IR and that triggered an assert in SCEV. From vectorizer's architectural perspective, such information, while still useful in vector code gen, should not be recomputed after the start of transforming the LLVM IR. Instead, we should collect and cache such information during the analysis phase of LV and use the cached info during code gen. From the symptom perspective, this assert as it stands right now is not very useful. Legality already rejected loops that would trigger the assert. As such, commenting out the assert is NFC from vectorizer's functionality perspective. On top of that, just above the assertion, we check for unit-strided load/store or gather scatter. Addresses can't be uniform below that check. From vectorization theory point of view, we don't have to reject all cases of stores to uniform addresses. Eventually, we should support safe/profitable cases. This patch resolves the issue by removing the useless assertion that is invoking LAA's isUniform() that requires up-to-date DomTree ---- once vector code gen starts modifying CFG, we don't have an up-to-date DomTree. Patch by Hideki Saito <hideki.saito@intel.com>. llvm-svn: 327109
* [Support] Move syntax highlighting into supportJonas Devlieghere2018-03-099-128/+89
| | | | | | | | | | | | Move the DWARF syntax highlighting into support. This has several advantages, most notably that this makes the WithColor RAII wrapper available outside libDebugInfo. Furthermore, several projects all have their own code for handling colored output. This provides a place to centralize it. Differential revision: https://reviews.llvm.org/D44215 llvm-svn: 327108
* [AMDGPU] Fixed V_DIV_FIXUP_F16 selection on GFX9Stanislav Mekhanoshin2018-03-091-13/+12
| | | | | | | | GFX9 should select opsel version. Differential Revision: https://reviews.llvm.org/D44279 llvm-svn: 327106
* [X86] Remove duplicate isel pattern. NFCCraig Topper2018-03-091-1/+0
| | | | llvm-svn: 327104
* Don't treat .symver as a regular alias definition.Rafael Espindola2018-03-094-3/+20
| | | | | | | | | | | | | | This patch starts simplifying the handling of .symver. For now it just moves the responsibility for creating an alias down to the streamer. With that the asm streamer can pass a .symver unchanged, which is nice since gas cannot parse "foo@bar = zed". In a followup I hope to move the handling down to the writer so that we don't need special hacks for avoiding breaking names with @@@ on windows. llvm-svn: 327101
* Revert "[ThinLTO] Keep available_externally symbols live"Eric Christopher2018-03-091-19/+3
| | | | | | This reverts commit r327041 and the followup attempts at fixing the testcase as they're still failing. llvm-svn: 327094
* [X86] Remove SRAs from v16i8 multiply lowering on sse2 targetsCraig Topper2018-03-091-8/+10
| | | | | | | | | | Previously we unpacked the even bytes of each input into the high byte of 16-bit elements then did an v8i16 arithmetic shift right by 8 bits to fill the upper bits of each word with sign bits. Then we did the v8i16 multiply and then masked to zero the upper 8-bits of each result. The similar was done for all the odd bytes. The results are then packed together with packuswb Since we are masking each multiply result element to 8-bits, and those 8-bits are determined only by the lower 8-bits of each of the inputs, we don't need to fill the upper bits with sign bits. So we can just unpack into the low byte of each element and treat the upper bits as garbage. This is what gcc also does. Differential Revision: https://reviews.llvm.org/D44267 llvm-svn: 327093
* LowerDbgDeclare: ignore dbg.declares for allocas with volatile accessAdrian Prantl2018-03-091-17/+28
| | | | | | | | | | | There is no point in lowering a dbg.declare describing an alloca that has volatile loads or stores as users, since the alloca cannot be elided. Lowering the dbg.declare will result in larger debug info that may also have worse coverage than just describing the alloca. rdar://problem/34496278 llvm-svn: 327092
* Fix header comment on SHA1 code.Eric Christopher2018-03-091-1/+1
| | | | llvm-svn: 327086
* Revert "[DWARF] Fix mixing assembler -g with DWARF .file directives."Paul Robinson2018-03-091-29/+14
| | | | | | | This reverts commit d6d9ac1ab5039ba1fe0f63c36eac2bdd9f0a79c9. aka r327073 llvm-svn: 327083
* Propagate flags to SDValue in SplitVecOp_VECREDUCESameer AbuAsal2018-03-081-2/+2
| | | | | | | | | | | | This patch is a fix for PR36642. While legalizing long vector types, make sure the smaller types get the flags of the wider type. bugzilla link: https://bugs.llvm.org/show_bug.cgi?id=36642 Change-Id: I0c2829639f094c862c10a6b51b342d4c2563e1fa llvm-svn: 327079
* For llvm-objdump and Mach-O files, update the printing of some thread statesKevin Enderby2018-03-081-1/+49
| | | | | | | | | | | from core files. I tested this against the couple of core files that were getting errors about unknown thread flavors and it now produce the same output as the Xcode otool-classic(1) tool. Since the core files are huge I didn’t include them as test cases. rdar://38216356 llvm-svn: 327077
* [DWARF] Fix mixing assembler -g with DWARF .file directives.Paul Robinson2018-03-081-14/+29
| | | | | | | | | | | We were effectively overriding an explicit '.file' directive with info for the assembler source. That shouldn't happen. Fixes PR36636. Differential Revision: https://reviews.llvm.org/D44265 llvm-svn: 327073
* [DebugInfo] Add DW_AT_byte_size to vectorsMatt Davis2018-03-081-1/+32
| | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds the DW_AT_byte_size dwarf attribute to vectors. This fixes PR21924 LLVM will round a vector up to the next alignable address, which can result in the vector's representation in the object file being larger than what the debugger will calculate via NumberOfElements * ElementSize. In such a case calling sizeof(MyVec) in the source will result in a different value than what a debugger might present. This situation can occur because LLVM permits non-power of two 'vector_size' attributes. Reviewers: echristo, dexonsmith, aprantl Reviewed By: aprantl Subscribers: probinson, aprantl, llvm-commits, JDevlieghere Tags: #debug-info Differential Revision: https://reviews.llvm.org/D44048 llvm-svn: 327072
* [TargetLowering] Remove redundant if condition in SimplifySetcc. NFCCraig Topper2018-03-081-1/+1
| | | | | | We were checking the condition code a second time when we were already in a block with this same condition code check. llvm-svn: 327069
* [DebugInfo] Move RangeListEntries instead of copying.Benjamin Kramer2018-03-081-2/+2
| | | | | | | This is needed for correctness as RangeListEntry is not copy-assignable, which std::vector might rely on. llvm-svn: 327067
* [NFC] Factor out a helper function for checking if a block has a potential ↵Philip Reames2018-03-083-10/+14
| | | | | | early implicit exit. llvm-svn: 327065
* Fix compilation failure with MSVC.Zachary Turner2018-03-081-1/+1
| | | | llvm-svn: 327063
* [asan] Fix a false positive ODR violation due to LTO ConstantMerge pass ↵Kuba Mracek2018-03-081-0/+10
| | | | | | | | | | [llvm part, take 3] This fixes a false positive ODR violation that is reported by ASan when using LTO. In cases, where two constant globals have the same value, LTO will merge them, which breaks ASan's ODR detection. Differential Revision: https://reviews.llvm.org/D43959 llvm-svn: 327061
* Fix signed-unsigned comparison warning.Zachary Turner2018-03-081-1/+1
| | | | llvm-svn: 327060
* [DWARF v5] Support for verbose dumping of .debug_rnglist entriesWolfgang Pieb2018-03-084-28/+98
| | | | | | | | | | | | | | | | Adding verbose dumping to the recent implementation of dumping of v5 range list entries. We're capturing the entries as is as they come in during extraction, including their file offset, so we can dump them in more detail. The offset table entries which are table-relative are shown as is (as in non-verbose mode) and with the actual file offset they map to. Reviewers: dblaikie, aprantl, jdevlieghere, jhenderson Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D43366 llvm-svn: 327059
* [ConstantFold] fp_binop undef, undef --> undefSanjay Patel2018-03-081-1/+4
| | | | | | | | | | | | | | | | | These are uncontroversial and independent of a proposed LangRef edits (D44216). I tried to fix tests that would fold away: rL327004 rL327028 rL327030 rL327034 I'm not sure if the Reassociate tests are meaningless yet, but they probably will be as we add more folds, so if anyone has suggestions or wants to fix those, please do. Differential Revision: https://reviews.llvm.org/D44258 llvm-svn: 327058
* [Support] Add WriteThroughMemoryBuffer.Zachary Turner2018-03-083-6/+57
| | | | | | | | | | | This is like MemoryBuffer (read-only) and WritableMemoryBuffer (writable private), but where the underlying file can be modified after writing. This is useful when you want to open a file, make some targeted edits, and then write it back out. Differential Revision: https://reviews.llvm.org/D44230 llvm-svn: 327057
* Revert r327053.Kuba Mracek2018-03-081-7/+0
| | | | llvm-svn: 327055
* [X86][AVX] Pull out variable permute creation from ↵Simon Pilgrim2018-03-081-136/+140
| | | | | | | | LowerBUILD_VECTORAsVariablePermute. NFCI. This will make it easier to handle more complex cases than basic scaling or index masks. llvm-svn: 327054
* [asan] Fix a false positive ODR violation due to LTO ConstantMerge pass ↵Kuba Mracek2018-03-081-0/+7
| | | | | | | | | | [llvm part, take 2] This fixes a false positive ODR violation that is reported by ASan when using LTO. In cases, where two constant globals have the same value, LTO will merge them, which breaks ASan's ODR detection. Differential Revision: https://reviews.llvm.org/D43959 llvm-svn: 327053
* Fix detection of COFF executable files.Zachary Turner2018-03-081-8/+6
| | | | | | | | | | | | One overload of this function would try to identify a file by opening it and using the first 32 bytes to identify the magic of the file. This didn't work properly when more than 32 bytes is actually needed for magic detection to succeed. So now we have this overload read in the entire file. Differential Revision: https://reviews.llvm.org/D44225 llvm-svn: 327050
* [DebugInfo] Add verifier for DICompositeType vectorMatt Davis2018-03-081-0/+8
| | | | | | | | | | | | | | | | | | | Summary: This patch adds verification logic for DICompositeType vectors, ensuring that they only have one element, and that element is of type subrange. This patch complements https://reviews.llvm.org/D44048 Reviewers: aprantl Reviewed By: aprantl Subscribers: JDevlieghere, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D44262 llvm-svn: 327048
* [ThinLTO] Keep available_externally symbols liveVlad Tsyrklevich2018-03-081-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change fixes PR36483. The bug was originally introduced by a change that marked non-prevailing symbols dead. This broke LowerTypeTests handling of available_externally functions, which are non-prevailing. LowerTypeTests uses liveness information to avoid emitting thunks for unused functions. Marking available_externally functions dead is incorrect, the functions are used though the function definitions are not. This change keeps them live, and lets the EliminateAvailableExternally/GlobalDCE passes remove them later instead. I've also enabled EliminateAvailableExternally for all optimization levels, I believe it being disabled for O1 was an oversight. Reviewers: pcc, tejohnson Reviewed By: tejohnson Subscribers: grimar, mehdi_amini, inglorion, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D43690 llvm-svn: 327041
* [Hexagon] Ignore indexed loads when handling unaligned loadsKrzysztof Parzyszek2018-03-081-3/+4
| | | | llvm-svn: 327037
* Expose must/may alias info in MemorySSA.Alina Sbirlea2018-03-081-35/+89
| | | | | | | | | | | | | | | | Summary: Building MemorySSA gathers alias information for Defs/Uses. Store and expose this information when optimizing uses (when building MemorySSA), and when optimizing defs or updating uses (getClobberingMemoryAccess). Current patch does not propagate alias information through MemoryPhis. Reviewers: gbiv, dberlin Subscribers: Prazek, sanjoy, llvm-commits Differential Revision: https://reviews.llvm.org/D38569 llvm-svn: 327035
* Revert r327029Kuba Mracek2018-03-081-6/+0
| | | | llvm-svn: 327033
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