summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* Remove a non-modular header (& inline it into its one use)David Blaikie2017-12-142-68/+55
| | | | llvm-svn: 320768
* [AArch64] Test patchEvandro Menezes2017-12-141-0/+1
| | | | | | Fix formatting by adding a missing blank line to test new network setup. llvm-svn: 320760
* EmitFuncArgumentDbgValue: Prefer stack slots over registers for stack argumentsAdrian Prantl2017-12-141-7/+7
| | | | | | | | | | | | | | | | | | While investigating LLVM PR22316 (http://llvm.org/bugs/show_bug.cgi?id=22316) I started wondering if it were not always preferable to emit the initial DBG_VALUEs for stack arguments as FI locations instead of describing the first register they get copied into. The advantage of doing this is that the arguments will be available as soon as the stack is setup. As illustrated by the testcase in the PR, the first copy of the FI into a register may be sunk by MachineSink.cpp into a later basic block. By describing the argument on the stack, we nicely circumvent this problem. <rdar://problem/19583723> Differential Revision: https://reviews.llvm.org/D41135 llvm-svn: 320758
* [X86] Remove an unnecessary SmallVector that was collecting chains for two ↵Craig Topper2017-12-141-5/+3
| | | | | | | | SDNode's we're still holding SDValues for. NFCI We can just get the chains from those SDValues to create the TokenFactor. llvm-svn: 320757
* TLI: Allow using PSV for intrinsic mem operandsMatt Arsenault2017-12-1416-3/+19
| | | | llvm-svn: 320756
* Fix many -Wsign-compare and -Wtautological-constant-compare warnings.Zachary Turner2017-12-149-10/+10
| | | | | | | | | | | | Most of the -Wsign-compare warnings are due to the fact that enums are signed by default in the MS ABI, while the tautological comparison warnings trigger on x86 builds where sizeof(size_t) is 4 bytes, so N > numeric_limits<unsigned>::max() is always false. Differential Revision: https://reviews.llvm.org/D41256 llvm-svn: 320750
* [SimplifyCFG] don't sink common insts too soon (PR34603)Sanjay Patel2017-12-146-15/+36
| | | | | | | | | | | | This should solve: https://bugs.llvm.org/show_bug.cgi?id=34603 ...by preventing SimplifyCFG from altering redundant instructions before early-cse has a chance to run. It changes the default (canonical-forming) behavior of SimplifyCFG, so we're only doing the sinking transform later in the optimization pipeline. Differential Revision: https://reviews.llvm.org/D38566 llvm-svn: 320749
* DAG: Expose all MMO flags in getTgtMemIntrinsicMatt Arsenault2017-12-1410-146/+73
| | | | | | | | | | | | | | Rather than adding more bits to express every MMO flag you could want, just directly use the MMO flags. Also fixes using a bunch of bool arguments to getMemIntrinsicNode. On AMDGPU, buffer and image intrinsics should always have MODereferencable set, but currently there is no way to do that directly during the initial intrinsic lowering. llvm-svn: 320746
* [Hexagon] Generate HVX code for comparisons and selectsKrzysztof Parzyszek2017-12-145-7/+111
| | | | llvm-svn: 320744
* [WebAssembly] Add support for init functions linking metadataSam Clegg2017-12-142-1/+27
| | | | | | | | | | | | | | | Summary: This change lays the groundwork lowering of @llvm.global_ctors and @llvm.global_dtors for the wasm object format. Some parts of this patch are subset of: https://reviews.llvm.org/D40759 See https://github.com/WebAssembly/tool-conventions/issues/25 Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish Differential Revision: https://reviews.llvm.org/D41208 llvm-svn: 320742
* [SLPVectorizer] Don't ignore scalar extraction instructions of aggregate valueGuozhi Wei2017-12-141-3/+7
| | | | | | | | | In SLPVectorizer, the vector build instructions (insertvalue for aggregate type) is passed to BoUpSLP.buildTree, it is treated as UserIgnoreList, so later in cost estimation, the cost of these instructions are not counted. For aggregate value, later usage are more likely to be done in scalar registers, either used as individual scalars or used as a whole for function call or return value. Ignore scalar extraction instructions may cause too aggressive vectorization for aggregate values, and slow down performance. So for vectorization of aggregate value, the scalar extraction instructions are required in cost estimation. Differential Revision: https://reviews.llvm.org/D41139 llvm-svn: 320736
* Add MVT::v128i1, NFCKrzysztof Parzyszek2017-12-141-0/+2
| | | | | | | Hexagon HVX has type v128i8, comparing two vectors of that type will produce v128i1 types in SelectionDAG. llvm-svn: 320732
* [MC] Allow .file directives to be out-of-orderPaul Robinson2017-12-141-1/+2
| | | | llvm-svn: 320727
* [X86] Don't zero the upper bits of the k-register before extracting a single ↵Craig Topper2017-12-141-6/+3
| | | | | | | | bit from a vXi1. This doesn't match the semantics of the extract_vector_elt operation. Nothing downstream knows the bits were zeroed so they still get masked or sign extended after the extrat anyway. llvm-svn: 320723
* [Hexagon] Remove vectors of i64 from valid HVX typesKrzysztof Parzyszek2017-12-145-69/+24
| | | | | | HVX does not support operations on 64-bit integers. llvm-svn: 320722
* [COFF] Teach LLD to use the COFF .debug$H section.Zachary Turner2017-12-142-13/+116
| | | | | | | | | | | | This adds the /DEBUG:GHASH option to LLD which will look for the existence of .debug$H sections in linker inputs and use them to accelerate type merging. The clang-cl side has already been added, so this completes the work necessary to begin experimenting with this feature. Differential Revision: https://reviews.llvm.org/D40980 llvm-svn: 320719
* [ARM] Fix isRenamable flag setting on expanded VSTMDIA opcode.Geoff Berry2017-12-141-1/+3
| | | | | | Fixes expensive-check ARM buildbot failure. llvm-svn: 320718
* Revert CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu2017-12-143-19/+11
| | | | | | This commit might have caused regression on ppc64. Revert it to verify that. llvm-svn: 320712
* Re-commit: [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.Sander de Smalen2017-12-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand. This is because the code will only update the diagnostic if it is more specific than the previous diagnostic. However, when having validated operands and 'moved on' to a next operand (for some instruction/alias for which all previous operands are valid), if the diagnostic is InvalidOperand, than that should be set as the diagnostic, not the more specific message about a previous operand for some other instruction/alias candidate. (Re-committed with an extra whitespace in SVEInstrFormats.td to trigger rebuild of AArch64GenAsmMatcher.inc, since the llvm-clang-x86_64-expensive-checks-win builder does not seem to rebuild AArch64GenAsmMatcher.inc with the newly built TableGen due to a missing dependency somewhere (see: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119555.html)) Reviewers: craig.topper, olista01, rengolin, stoklund Reviewed By: olista01 Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40011 llvm-svn: 320711
* [mips] Add partial support for R6 in the long branch passSimon Dardis2017-12-141-46/+116
| | | | | | | | | | | | | | | | | | | | MIPSR6 introduced several new jump instructions and deprecated the use of the 'j' instruction. For microMIPS32R6, 'j' was removed entirely and it only has non delay slot jumps. This patch adds support for MIPSR6 by using some R6 instructions-- 'bc' instead of 'j', 'jic $reg, 0' instead of 'jalr $zero, $reg'-- and modifies the sequences not to use delay slots for R6. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: dschuff, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D40786 llvm-svn: 320703
* [ScalarEvolution] Fix base condition in isNormalAddRecPHI.Bjorn Pettersson2017-12-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The function is meant to recurse until it comes upon the phi it's looking for. However, with the current condition, it will recurse until it finds anything _but_ the phi. The function will even fail for simple cases like: %i = phi i32 [ %inc, %loop ], ... ... %inc = add i32 %i, 1 because the base condition will not happen when the phi is recursed to, and the recursion will end with a 'false' result since the previous instruction is a phi. Reviewers: sanjoy, atrick Reviewed By: sanjoy Subscribers: Ka-Ka, bjope, llvm-commits Committing on behalf of: Bevin Hansson (bevinh) Differential Revision: https://reviews.llvm.org/D40946 llvm-svn: 320700
* [InlineCost] Tracking Values through PHI NodesHaicheng Wu2017-12-141-6/+138
| | | | | | | | | | | | This patch fix this FIXME in visitPHI() FIXME: We should potentially be tracking values through phi nodes, especially when they collapse to a single value due to deleted CFG edges during inlining. Differential Revision: https://reviews.llvm.org/D38594 llvm-svn: 320699
* Revert "[DAGCombine] Move AND nodes to multiple load leaves"Benjamin Kramer2017-12-141-124/+0
| | | | | | This reverts commit r320679. Causes miscompiles. llvm-svn: 320698
* Any Target Asm comments should start from MachineInstr::TAsmComments value.Andrew V. Tischenko2017-12-141-1/+4
| | | | llvm-svn: 320693
* [AVX512] Adding support for load truncate store of I1Michael Zuckerman2017-12-141-0/+3
| | | | | | | | | | store operation on a truncated memory (load) of vXi1 is poorly supported by LLVM and most of the time end with an assertion. This patch fixes this issue. Differential Revision: https://reviews.llvm.org/D39547 Change-Id: Ida5523dd09c1ad384acc0a27e9e59273d28cbdc9 llvm-svn: 320691
* [PM][InstCombine] fixing omission of AliasAnalysis in new-pass-manager's ↵Fedor Sergeev2017-12-141-2/+3
| | | | | | | | | | | | | | | | | | version of InstCombine Summary: Passing AliasAnalysis results instead of nullptr appears to work just fine. A couple new-pass-manager tests updated to align with new order of analyses. Reviewers: chandlerc, spatel, craig.topper Reviewed By: chandlerc Subscribers: mehdi_amini, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D41203 llvm-svn: 320687
* Remove redundant includes from lib/Target/AArch64.Fedor Sergeev2017-12-141-1/+0
| | | | llvm-svn: 320686
* [CodeGen] Print MCSymbol operands as <mcsymbol sym> in both MIR and debug outputFrancis Visoiu Mistrih2017-12-142-5/+3
| | | | | | | | | Work towards the unification of MIR and debug output by printing `<mcsymbol sym>` instead of `<MCSym=sym>`. Only debug syntax is affected. llvm-svn: 320685
* [CodeGen] Move printing MO_Metadata operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-142-6/+2
| | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. llvm-svn: 320684
* [CodeGen] Print live-out register lists as liveout(...) in both MIR and ↵Francis Visoiu Mistrih2017-12-142-18/+20
| | | | | | | | | | | debug output Work towards the unification of MIR and debug output by printing `liveout(...)` instead of `<regliveout>`. Only debug syntax is affected. llvm-svn: 320683
* [CodeGen] Print global addresses as @foo in both MIR and debug outputFrancis Visoiu Mistrih2017-12-146-95/+92
| | | | | | | | | | | | Work towards the unification of MIR and debug output by printing `@foo` instead of `<ga:@foo>`. Also print target flags in the MIR format since most of them are used on global address operands. Only debug syntax is affected. llvm-svn: 320682
* [CodeGen] Print external symbols as $symbol in both MIR and debug outputFrancis Visoiu Mistrih2017-12-142-17/+13
| | | | | | | | | Work towards the unification of MIR and debug output by printing `$symbol` instead of `<es:symbol>`. Only debug syntax is affected. llvm-svn: 320681
* [Verifier] Check that GEP indexes has correct typesIgor Laevsky2017-12-141-0/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D40391 llvm-svn: 320680
* [DAGCombine] Move AND nodes to multiple load leavesSam Parker2017-12-141-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | Recommitting rL319773, which was reverted due to a recursive issue causing timeouts. This happened because I failed to check whether the discovered loads could be narrowed further. In the case of a tree with one or more narrow loads, that could not be further narrowed, as well as a node that would need masking, an AND could be introduced which could then be visited and recombined again with the same load. This could again create the masking load, with would be combined again... We now check that the load can be narrowed so that this process stops. Original commit message: Search from AND nodes to find whether they can be propagated back to loads, so that the AND and load can be combined into a narrow load. We search through OR, XOR and other AND nodes and all bar one of the leaves are required to be loads or constants. The exception node then needs to be masked off meaning that the 'and' isn't removed, but the loads(s) are narrowed still. Differential Revision: https://reviews.llvm.org/D41177 llvm-svn: 320679
* [X86] Make ANY_EXTEND from vXi1 Custom for more types.Craig Topper2017-12-141-0/+6
| | | | | | We should be able to support ANY_EXTEND for any types we support ZERO_EXTEND for. llvm-svn: 320675
* [SelectionDAG][X86] Improve legalization of v32i1 CONCAT_VECTORS of v16i1 ↵Craig Topper2017-12-141-0/+15
| | | | | | | | | | for AVX512F. A v32i1 CONCAT_VECTORS of v16i1 uses promotion to v32i8 to legalize the v32i1. This results in a bunch of extract_vector_elts and a build_vector that ultimately gets scalarized. This patch checks to see if v16i8 is legal and inserts a any_extend to that so that we can concat v16i8 to v32i8 and avoid creating the extracts. llvm-svn: 320674
* [X86] Remove redundant setOperationAction calls.Craig Topper2017-12-141-2/+0
| | | | | | These calls already exist earlier under AVX2 feature. llvm-svn: 320673
* [LV] Support efficient vectorization of an induction with redundant castsDorit Nuzman2017-12-143-20/+257
| | | | | | | | | | | | | | | | | | | | | | | | | | | | D30041 extended SCEVPredicateRewriter to improve handling of Phi nodes whose update chain involves casts; PSCEV can now build an AddRecurrence for some forms of such phi nodes, under the proper runtime overflow test. This means that we can identify such phi nodes as an induction, and the loop-vectorizer can now vectorize such inductions, however inefficiently. The vectorizer doesn't know that it can ignore the casts, and so it vectorizes them. This patch records the casts in the InductionDescriptor, so that they could be marked to be ignored for cost calculation (we use VecValuesToIgnore for that) and ignored for vectorization/widening/scalarization (i.e. treated as TriviallyDead). In addition to marking all these casts to be ignored, we also need to make sure that each cast is mapped to the right vector value in the vector loop body (be it a widened, vectorized, or scalarized induction). So whenever an induction phi is mapped to a vector value (during vectorization/widening/ scalarization), we also map the respective cast instruction (if exists) to that vector value. (If the phi-update sequence of an induction involves more than one cast, then the above mapping to vector value is relevant only for the last cast of the sequence as we allow only the "last cast" to be used outside the induction update chain itself). This is the last step in addressing PR30654. llvm-svn: 320672
* [SelectionDAG] When legalizing the result type of CONCAT_VECTORS, take into ↵Craig Topper2017-12-141-3/+8
| | | | | | | | | | account whether the input type also needs to be promoted. If so go ahead and get the promoted input vector to extract from. Previously, we would create a bunch of any_extends of extract_vector_elts with illegal input type that needs to be promoted. The legalization of those extract_vector_elts would then potentially introduce a truncate. So now we have a bunch of any_extends of truncates. By legalizing both parts together we avoid creating these extra nodes. The test changes seem to be because we were previously combining the build_vector with the any_extend before the any_extend got combined with the truncate. llvm-svn: 320669
* MC/AsmPrinter: Reduce code duplication.Matthias Braun2017-12-143-42/+33
| | | | | | | | | | Factor out duplicated code emitting mach-o version-min specifiers. This should be NFC but happens to fix a bug where the code in MCMachoStreamer didn't take the version skew between darwin and macos versions into account. llvm-svn: 320666
* MC: Add support for mach-o build_versionMatthias Braun2017-12-145-81/+219
| | | | | | | | LC_BUILD_VERSION is a new load command superseding the previously used LC_XXX_MIN_VERSION commands. This adds an assembler directive along with encoding/streaming support. llvm-svn: 320661
* Recommit r320461 "[X86] Use regular expressions more aggressively to reduce ↵Craig Topper2017-12-134-1032/+48
| | | | | | | | | | | | | | the number of scheduler entries needed for FMA3 instructions." I've hopefully sidestepped the MSVC issue that caused it to be reverted. We no longer include the Sched enum from X86GenInstrInfo.inc on the X86 target. So hopefully MSVC's preprocessor will skip over it and nothing will notice the 11000 character enum name. Original commit message: When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models. This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do. llvm-svn: 320655
* [EarlyCSE] recognize swapped variants of abs/nabs as equivalentSanjay Patel2017-12-131-9/+12
| | | | | | | | Extends https://reviews.llvm.org/rL320640 Differential Revision: https://reviews.llvm.org/D41136 llvm-svn: 320653
* CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu2017-12-133-11/+19
| | | | | | | | | | | | | | | | | Two issues were found about machine inst scheduler when compiling ProRender with -g for amdgcn target: GCNScheduleDAGMILive::schedule tries to update LiveIntervals for DBG_VALUE, which it should not since DBG_VALUE is not mapped in LiveIntervals. when DBG_VALUE is the last instruction of MBB, ScheduleDAGInstrs::buildSchedGraph and ScheduleDAGMILive::scheduleMI does not move RPTracker properly, which causes assertion. This patch fixes that. Differential Revision: https://reviews.llvm.org/D41132 llvm-svn: 320650
* [CodeView] Teach clang to emit the .debug$H COFF section.Zachary Turner2017-12-136-13/+186
| | | | | | | | | | | | | | | Currently this is an LLVM extension to the COFF spec which is experimental and intended to speed up linking. For now it is behind a hidden cl::opt flag, but in the future we can move it to a "real" cc1 flag and have the driver pass it through whenever it is appropriate. The patch to actually make use of this section in lld will come in a followup. Differential Revision: https://reviews.llvm.org/D40917 llvm-svn: 320649
* Recover some overzealously removed includes.Michael Zolotukhin2017-12-134-0/+4
| | | | llvm-svn: 320648
* Speculative build fix for lld on Linux after Michael's #include removalsHans Wennborg2017-12-131-0/+1
| | | | llvm-svn: 320645
* [WebAssembly] Use bitfield types in wasm YAML representationSam Clegg2017-12-131-0/+22
| | | | | | Differential Revision: https://reviews.llvm.org/D41202 llvm-svn: 320642
* Reverting [JumpThreading] Preservation of DT and LVI across the passBrian M. Rzycki2017-12-135-365/+89
| | | | | | | Stage 2 bootstrap failed: http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/14434 llvm-svn: 320641
* [EarlyCSE] recognize commuted and swapped variants of min/max as equivalent ↵Sanjay Patel2017-12-131-0/+27
| | | | | | | | | | | | | (PR35642) As shown in: https://bugs.llvm.org/show_bug.cgi?id=35642 ...we can have different forms of min/max, so we should recognize those here in EarlyCSE similar to how we already handle binops and compares that can commute. Differential Revision: https://reviews.llvm.org/D41136 llvm-svn: 320640
OpenPOWER on IntegriCloud