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* [X86] Fix typo in comment. NFCCraig Topper2017-10-291-1/+1
| | | | llvm-svn: 316859
* [X86] Use the extended vector register classes in fast isel with AVX512F/VL.Craig Topper2017-10-291-10/+10
| | | | llvm-svn: 316857
* [X86] Add AVX512 support to X86FastISel::X86SelectFPExt and ↵Craig Topper2017-10-291-4/+12
| | | | | | X86FastISel::X86SelectFPTrunc. llvm-svn: 316856
* [X86] Add AVX512 support to X86FastISel::X86MaterializeFPCraig Topper2017-10-291-2/+6
| | | | llvm-svn: 316853
* [X86] Remove invalid code from LowerVSELECT.Craig Topper2017-10-281-4/+0
| | | | | | | | This code attempted to say that v8i16/v16i16 VSELECT is legal if BWI and VLX are enabled, but the only way we could reach this point is if the condition was not a vXi1 type. Which means it really wasn't legal. We don't have any tests that exercise this code. So I'm hoping it wasn't really reachable. llvm-svn: 316851
* [SelectionDAG] Add support for INSERT_SUBVECTOR to computeKnownBitsSimon Pilgrim2017-10-281-0/+34
| | | | llvm-svn: 316847
* [X86][SSE] Combine 128-bit target shuffles to PACKSS/PACKUS.Simon Pilgrim2017-10-281-0/+10
| | | | llvm-svn: 316845
* [X86][SSE] Split off matchVectorShuffleWithPACK. NFCI.Simon Pilgrim2017-10-281-16/+41
| | | | | | Split matchVectorShuffleWithPACK from lowerVectorShuffleWithPACK so that we can reuse it for target shuffle combines llvm-svn: 316844
* [X86] Fix a mistake in the X86ISelDAGToDAG.cpp code for MUL8r/IMUL8r.Craig Topper2017-10-281-1/+1
| | | | | | I think this code is unreachable due to some promotions that occur elsewhere. I'll look into that to be sure, but for now I thought I should at least fix the obvious typo. llvm-svn: 316840
* [X86] Replace some default cases in X86SelectShift with llvm_unreachable.Craig Topper2017-10-281-3/+3
| | | | llvm-svn: 316839
* [SimplifyCFG] use pass options and remove the latesimplifycfg passSanjay Patel2017-10-286-83/+74
| | | | | | | | | | | | | | | | | This is no-functional-change-intended. This is repackaging the functionality of D30333 (defer switch-to-lookup-tables) and D35411 (defer folding unconditional branches) with pass parameters rather than a named "latesimplifycfg" pass. Now that we have individual options to control the functionality, we could decouple when these fire (but that's an independent patch if desired). The next planned step would be to add another option bit to disable the sinking transform mentioned in D38566. This should also make it clear that the new pass manager needs to be updated to limit simplifycfg in the same way as the old pass manager. Differential Revision: https://reviews.llvm.org/D38631 llvm-svn: 316835
* [X86][SSE] Rename truncateVectorCompareWithPACKSS to ↵Simon Pilgrim2017-10-281-12/+11
| | | | | | | | truncateVectorWithPACKSS. NFC. We no longer rely on the vector source being a comparison result, just have sufficient sign bits. llvm-svn: 316834
* [SelectionDAG] Support 'bit preserving' floating points bitcasts on ↵Simon Pilgrim2017-10-281-7/+15
| | | | | | | | | | | | computeKnownBits/ComputeNumSignBits For cases where we know the floating point representations match the bitcasted integer equivalent, allow bitcasting to these types. This is especially useful for the X86 floating point compare results which return all/zero bits but as a floating point type. Differential Revision: https://reviews.llvm.org/D39289 llvm-svn: 316831
* [X86] Remove unneeded MVT::i1 related code from fast isel.Craig Topper2017-10-281-10/+0
| | | | llvm-svn: 316825
* [ConstantFold] Fix a crash when folding a GEP that has vector indexHaicheng Wu2017-10-281-0/+3
| | | | | | | | | | LLVM crashes when factoring out an out-of-bound index into preceding dimension and the preceding dimension uses vector index. Simply bail out now when this case happens. Differential Revision: https://reviews.llvm.org/D38677 llvm-svn: 316824
* [PartialInlineLibCalls] Teach PartialInlineLibCalls to honor nobuiltin, ↵Craig Topper2017-10-281-6/+5
| | | | | | | | | | | | | | | | | | | | | | | properly check the function signature, and check TLI::has Summary: We shouldn't do this transformation if the function is marked nobuitlin. We were only checking that the return type is floating point, we really should be checking the argument types and argument count as well. This can be accomplished by using the other version of getLibFunc that takes the Function and not just the name. We should also be checking TLI::has since sqrtf is a macro on Windows. Fixes PR32559. Reviewers: hfinkel, spatel, davide, efriedma Reviewed By: davide, efriedma Subscribers: efriedma, llvm-commits, eraman Differential Revision: https://reviews.llvm.org/D39381 llvm-svn: 316819
* AMDGPU/GlobalISel: Mark 32-bit G_FADD as legalTom Stellard2017-10-271-0/+2
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D38439 llvm-svn: 316815
* [support] remove tautological comparison in Support/Windows/Path.incBob Haarman2017-10-271-4/+0
| | | | | | | | | | | | | | | | | Summary: The removed code checks that we are able to handle a 64-bit number, but the code we're calling takes two dwords (for a total of 64 bits), so this is always true. Reviewers: zturner, rnk, majnemer, compnerd Reviewed By: zturner Subscribers: amccarth, hiraditya, lebedev.ri, llvm-commits Differential Revision: https://reviews.llvm.org/D39263 llvm-svn: 316814
* Revert "Add support for writing 64-bit symbol tables for archives when ↵Jake Ehrlich2017-10-271-55/+9
| | | | | | | | offsets become too large for 32-bit" This reverts commit r316805. llvm-svn: 316813
* Add support for writing 64-bit symbol tables for archives when offsets ↵Jake Ehrlich2017-10-271-9/+55
| | | | | | | | | | | | | become too large for 32-bit This should fix https://bugs.llvm.org//show_bug.cgi?id=34189 This change makes it so that if writing a K_GNU style archive, you need to output a > 32-bit offset it should output in K_GNU64 style instead. Differential Revision: https://reviews.llvm.org/D36812 llvm-svn: 316805
* [Hexagon] Adjust patterns to reflect instruction selection preferencesKrzysztof Parzyszek2017-10-271-7/+30
| | | | llvm-svn: 316804
* Add a few missing headers for modularization/IWYU/etcDavid Blaikie2017-10-274-1/+5
| | | | | | | Several cases where class definitions are required for DenseMap pointer traits handling. llvm-svn: 316803
* [DAGCombine] Don't combine sext with extload if sextload is not supported ↵Guozhi Wei2017-10-271-1/+5
| | | | | | | | | | | | | | | and extload has multi users In function DAGCombiner::visitSIGN_EXTEND_INREG, sext can be combined with extload even if sextload is not supported by target, then if sext is the only user of extload, there is no big difference, no harm no benefit. if extload has more than one user, the combined sextload may block extload from combining with other zext, causes extra zext instructions generated. As demonstrated by the attached test case. This patch add the constraint that when sextload is not supported by target, sext can only be combined with extload if it is the only user of extload. Differential Revision: https://reviews.llvm.org/D39108 llvm-svn: 316802
* Make 32-bit member offset in Archive::Symbol::getMember 64-bitJake Ehrlich2017-10-271-1/+1
| | | | | | | | | | | | When accessing a member for a symbol with an offset greater than 2^32 - 1 the current Archive::Symbol::getMember implementation will overflow and cause unexpected behavior. This change simply fixes that. In particular if you call "llvm-nm --print-armap" on an archive that has this behavior you'll get an error. Differential Revision: https://reviews.llvm.org/D39379 llvm-svn: 316801
* Handle undefined weak hidden symbols on all architectures.Rafael Espindola2017-10-272-20/+12
| | | | | | | | | | | | | | | | We were handling the non-hidden case in lib/Target/TargetMachine.cpp, but the hidden case was handled in architecture dependent code and only X86_64 and AArch64 were covered. While it is true that some code sequences in some ABIs might be able to produce the correct value at runtime, that doesn't seem to be the common case. I left the AArch64 code in place since it also forces a got access for non-pic code. It is not clear if that is needed, but it is probably better to change that in another commit. llvm-svn: 316799
* Force #define GTEST_LANG_CXX11.Zachary Turner2017-10-271-0/+3
| | | | | | | | | | | | | | | | | | gtest depends on this #define to determine whether it can use various classes like std::tuple, or whether it has to fall back to experimental classes in the std::tr1 namespace. The check in the current version of gtest relies on the value of the `__cplusplus` macro, but MSVC provides a non-conformant value of this macro, making it effectively impossible to detect C++11. In short, LLVM compiled with MSVC has been silently using the tr1 versions of several classes since the beginning of time. This would normally be pretty benign, except that in the latest preview of MSVC they have marked all of the tr1 classes deprecated, so it spews thousands of warnings. llvm-svn: 316798
* [X86] Remove fast-isel code for handling i8 shifts. This is handled by auto ↵Craig Topper2017-10-271-14/+7
| | | | | | generated code. llvm-svn: 316797
* Improve clamp recognition in ValueTracking.Artur Gainullin2017-10-271-12/+26
| | | | | | | | | | | | | | | | Summary: ValueTracking was recognizing not all variations of clamp. Swapping of true value and false value of select was added to fix this problem. The first patch was reverted because it caused miscompile in NVPTX target. Added corresponding test cases. Reviewers: spatel, majnemer, efriedma, reames Subscribers: llvm-commits, jholewinski Differential Revision: https://reviews.llvm.org/D39240 llvm-svn: 316795
* [X86] Teach fastisel to use VLX VMOVNTDQA for v4f64 and 256-bit integers ↵Craig Topper2017-10-271-2/+2
| | | | | | | | when available. This looks to have been missed from r280682. llvm-svn: 316790
* Fix llvm-special-case-list-fuzzer regexp exceptionVlad Tsyrklevich2017-10-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Original oss-fuzz report: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3727#c2 The minimized test case that causes this failure: 5b 5b 5b 3d 47 53 00 5b 3d 5d 5b 5d 0a [[[=GS.[=][]. Note the string "=GS\x00". The failure happens because the code is searching the string against an array of known collated names. "GS\x00" is a hit, but since len takes into account an extra NUL byte, indexing into cp->name[len] goes one byte past it's allocated memory. Fix this to use a strlen(cp->name) comparison to account for NUL bytes in the input. Reviewers: pcc Reviewed By: pcc Subscribers: hctim, kcc Differential Revision: https://reviews.llvm.org/D39380 llvm-svn: 316786
* [Hexagon] Fix an incorrect assertion in HexagonConstExtenders.cppKrzysztof Parzyszek2017-10-271-1/+1
| | | | | | | Making sure that an instruction has fewer operands than required, then attempting to access one out of range is going to fail. llvm-svn: 316785
* ELF: Add support for emitting dynamic relocations in the Android relocation ↵Peter Collingbourne2017-10-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | packing format. The Android relocation packing format is a more compact format for dynamic relocations in executables and DSOs that is based on delta encoding and SLEBs. An overview of the format can be found in the Android source code: https://android.googlesource.com/platform/bionic/+/refs/heads/master/tools/relocation_packer/src/delta_encoder.h This patch implements relocation packing using that format. This implementation uses a more intelligent algorithm for compressing relative relocations than Android's own relocation packer. As a result it can generally create smaller relocation sections than that packer. If I link Chromium for Android targeting ARM32 I get a .rel.dyn of size 174693 bytes, as compared to 371832 bytes with gold and the Android packer. Differential Revision: https://reviews.llvm.org/D39152 llvm-svn: 316775
* [X86][F16C] Fix btver2 AGU pipe schedulingSimon Pilgrim2017-10-271-3/+3
| | | | | | Use the store AGU for stores, and the load AGU needs to be the first pipe for loads llvm-svn: 316771
* [LoopPredication] Handle the case when the guard and the latch IV have ↵Artur Pilipenko2017-10-271-61/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | different offsets This is a follow up change for D37569. Currently the transformation is limited to the case when: * The loop has a single latch with the condition of the form: ++i <pred> latchLimit, where <pred> is u<, u<=, s<, or s<=. * The step of the IV used in the latch condition is 1. * The IV of the latch condition is the same as the post increment IV of the guard condition. * The guard condition is of the form i u< guardLimit. This patch enables the transform in the case when the latch is latchStart + i <pred> latchLimit, where <pred> is u<, u<=, s<, or s<=. And the guard is guardStart + i u< guardLimit Reviewed By: anna Differential Revision: https://reviews.llvm.org/D39097 llvm-svn: 316768
* [CodeGen] Fix -Wunused-private-field warning on lld-x86_64-darwin13.Clement Courbet2017-10-271-2/+0
| | | | llvm-svn: 316765
* [CodeGen][ExpandMemCmp][NFC] Simplify load sequence generation.Clement Courbet2017-10-271-40/+33
| | | | llvm-svn: 316763
* [LLVM-C] Publicly expose getters of MetadataType, TokenTypewhitequark2017-10-271-3/+6
| | | | | | | | | | | Patch by Robert Widmann. Expose getters for MetadataType and TokenType publicly in the C API. Discovered a need for these while trying to wrap the intrinsics API. Differential Revision: https://reviews.llvm.org/D38809 llvm-svn: 316762
* Fix BB after r316756 "[llvm-dwarfdump] - Teach verifier to report broken ↵George Rimar2017-10-271-1/+1
| | | | | | | | | | | DWARF expressions." Bot: http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/6255 Changed format of this message by mistake. llvm-svn: 316757
* [llvm-dwarfdump] - Teach verifier to report broken DWARF expressions.George Rimar2017-10-272-29/+45
| | | | | | | | | | | | | Patch improves next things: * Fixes assert/crash in getOpDesc when giving it a invalid expression op code. * DWARFExpression::print() called DWARFExpression::Operation::getEndOffset() which returned and used uninitialized field EndOffset. Patch fixes that. * Teaches verifier to verify DW_AT_location and error out on broken expressions. Differential revision: https://reviews.llvm.org/D39294 llvm-svn: 316756
* DAG: Fold fma (fneg x), K, y -> fma x, -K, yMatt Arsenault2017-10-271-0/+8
| | | | llvm-svn: 316753
* [GVN][NFC] Refactor loop iteration with foreachMax Kazantsev2017-10-271-6/+6
| | | | llvm-svn: 316748
* Revert rL316568 because of sudden performance drop on ARMMax Kazantsev2017-10-271-2/+8
| | | | llvm-svn: 316739
* Add subclass data to the FoldingSetNode for MemIntrinsicSDNodes.Sean Fertile2017-10-271-0/+2
| | | | | | | | | | | Not having the subclass data on an MemIntrinsicSDNodes means it was possible to try to fold 2 nodes with the same operands but differing MMO flags. This would trip an assertion when trying to refine the alignment between the 2 MachineMemOperands. Differential Revision: https://reviews.llvm.org/D38898 llvm-svn: 316737
* [Transforms] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-10-2712-178/+350
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 316724
* [PDB] Handle an empty globals hash table with no bucketsReid Kleckner2017-10-271-2/+3
| | | | llvm-svn: 316722
* Revert "[CGP] Merge empty case blocks if no extra moves are added."Balaram Makam2017-10-271-36/+11
| | | | | | This reverts commit r316711. The domtree isn't getting updated correctly. llvm-svn: 316721
* [WebAssembly] MC: Don't allow zero sized data segmentsSam Clegg2017-10-271-0/+8
| | | | | | | | | | | This ensures that each segment has a unique address. Without this, consecutive zero sized symbols would end up with the same address and the linker cannot map symbols to unique data segments. Differential Revision: https://reviews.llvm.org/D39107 llvm-svn: 316717
* InstructionSelectorImpl.h: Modularize/remove ODR violations by using a ↵David Blaikie2017-10-263-6/+7
| | | | | | static member function to expose the debug name llvm-svn: 316715
* [CGP] Merge empty case blocks if no extra moves are added.Balaram Makam2017-10-261-11/+36
| | | | | | | | | | | | | | | | Summary: Currently we skip merging when extra moves may be added in the header of switch instead of the case block, if the case block is used as an incoming block of a PHI. If all the incoming values of the PHIs are non-constants and the destination block is dominated by the switch block then extra moves are likely not added by ISel, so there is no need to skip merging in this case. Reviewers: efriedma, junbuml, davidxl, hfinkel, qcolombet Reviewed By: efriedma Subscribers: dberlin, kuhar, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D37343 llvm-svn: 316711
* [SimplifyIndVars] Shorten code by using SCEV helper [NFC]Philip Reames2017-10-261-7/+4
| | | | llvm-svn: 316709
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