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* [CodeView] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-06-2911-46/+127
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 306616
* [InstCombine] Retain TBAA when narrowing memory accessesKeno Fischer2017-06-282-3/+29
| | | | | | | | | | | | Summary: As discussed on the mailing list it is legal to propagate TBAA to loads/stores from/to smaller regions of a larger load tagged with TBAA. Do so for (load->extractvalue)=>(gep->load) and similar foldings. Reviewed By: sanjoy Differential Revision: https://reviews.llvm.org/D31954 llvm-svn: 306615
* Introduce symbol cache to PDB NativeSessionAdrian McCarthy2017-06-282-5/+20
| | | | | | | | | | | | | Instead of creating symbols directly in the findChildren methods of the native symbol implementations, they will rely on the NativeSession to act as a factory for these types. This lets NativeSession cache the NativeRawSymbols in its new symbol cache and makes that cache the source of unique IDs for the symbols. Right now, this affects only NativeCompilandSymbols. There's no external change yet, so I think the existing tests are still sufficient. Coming soon are patches to extend this to built-in types and enums. llvm-svn: 306610
* AMDGPU: Remove SITypeRewriterMatt Arsenault2017-06-284-159/+0
| | | | | | | This was an old workaround for using v16i8 in some old intrinsics for resource descriptors. llvm-svn: 306603
* Fix a typo.Eric Christopher2017-06-281-1/+1
| | | | llvm-svn: 306599
* Fold fneg and fabs like multiplicationsStanislav Mekhanoshin2017-06-281-0/+46
| | | | | | | | | | | Given no NaNs and no signed zeroes it folds: (fmul X, (select (fcmp X > 0.0), -1.0, 1.0)) -> (fneg (fabs X)) (fmul X, (select (fcmp X > 0.0), 1.0, -1.0)) -> (fabs X) Differential Revision: https://reviews.llvm.org/D34579 llvm-svn: 306592
* [AArch64] Make assert messages uniform and general [NFC]Mandeep Singh Grang2017-06-284-8/+5
| | | | | | | | | | | | | | Summary: Make assert messages related to Darwin, ELF and COFF uniform. Reviewers: rnk, ruiu, compnerd, t.p.northover Reviewed By: t.p.northover Subscribers: t.p.northover, aemerson, rengolin, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D34730 llvm-svn: 306589
* [AArch64][Falkor] Attempt to fix Windows buildbotsGeoff Berry2017-06-281-1/+1
| | | | llvm-svn: 306588
* Reuse existing variables. NFC.Rafael Espindola2017-06-281-11/+9
| | | | llvm-svn: 306586
* [AArch64][Falkor] Try to avoid exhausting HW prefetcher resources when ↵Geoff Berry2017-06-281-0/+59
| | | | | | | | | | | | unrolling. Reviewers: t.p.northover, mcrosier Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34533 llvm-svn: 306584
* Reuse existing variable. NFC.Rafael Espindola2017-06-281-2/+2
| | | | llvm-svn: 306582
* [LV] Fix PR33613 - retain order of insertelement per partAyal Zaks2017-06-281-6/+7
| | | | | | | | | | | | r306381 caused PR33613, by reversing the order in which insertelements were generated per unroll part. This patch fixes PR33613 by retraining this order, placing each set of insertelements per part immediately after the last scalar being packed for this part. Includes a test case derived from PR33613. Reference: https://bugs.llvm.org/show_bug.cgi?id=33613 Differential Revision: https://reviews.llvm.org/D34760 llvm-svn: 306575
* Fix PR33625.Rafael Espindola2017-06-281-1/+1
| | | | | | We were failing to convert this expression to pcrel. llvm-svn: 306573
* Don't repeat name in comment and format. NFC.Rafael Espindola2017-06-281-19/+15
| | | | llvm-svn: 306568
* [LoopUnroll] Fix bug in computeUnrollCount causing it to not honor MaxCountGeoff Berry2017-06-281-0/+2
| | | | | | | | | | Reviewers: sanjoy, anna, reames, apilipenko, igor-laevsky, mkuper Subscribers: mcrosier, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D34532 llvm-svn: 306564
* [InstCombine] use local variable to reduce code; NFCISanjay Patel2017-06-281-18/+14
| | | | llvm-svn: 306560
* Rangify loops, formatting changes, use bool instead of unsigned, NFCKrzysztof Parzyszek2017-06-281-18/+16
| | | | llvm-svn: 306557
* Don't repeat names and reformat. NFC.Rafael Espindola2017-06-281-46/+37
| | | | llvm-svn: 306556
* [LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI.Geoff Berry2017-06-2814-31/+37
| | | | | | | | | | Reviewers: sanjoy, anna, reames, apilipenko, igor-laevsky, mkuper Subscribers: jholewinski, arsenm, mzolotukhin, nemanjai, nhaehnle, javed.absar, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D34531 llvm-svn: 306554
* Missed a check for UndefVI in r306466Krzysztof Parzyszek2017-06-281-1/+1
| | | | llvm-svn: 306553
* [AArch64] AArch64CondBrTuningPass generates wrong branch instructionsAlexandros Lamprineas2017-06-281-3/+3
| | | | | | | | | | | Some conditional branch instructions generated by this pass are checking the wrong condition code. The instructions TBZ and TBNZ are transformed into B.GE and B.LT instead of B.PL and B.MI respectively. They should only be checking the Negative bit. Differential Revision: https://reviews.llvm.org/D34743 llvm-svn: 306550
* Don't repeat name in comments. 80 columns. NFC.Rafael Espindola2017-06-281-22/+16
| | | | llvm-svn: 306548
* [ARM] Improve if-conversion for M-class CPUs without branch predictorsJohn Brawn2017-06-285-14/+85
| | | | | | | | | | | | | The current heuristic in isProfitableToIfCvt assumes we have a branch predictor, and so gives the wrong answer in some cases when we don't. This patch adds a subtarget feature to indicate that a subtarget has no branch predictor, and changes the heuristic in isProfitableToiIfCvt when it's present. This gives a slight overall improvement in a set of embedded benchmarks on Cortex-M4 and Cortex-M33. Differential Revision: https://reviews.llvm.org/D34398 llvm-svn: 306547
* Create inliner params based on size and opt levels.Easwaran Raman2017-06-281-3/+11
| | | | | | Differential revision: https://reviews.llvm.org/D34309 llvm-svn: 306542
* Add zero-length check to memcpy/memset load store loop expansionTeresa Johnson2017-06-281-5/+12
| | | | | | | | | | | | | | | | Summary: I was testing using this expansion logic in other cases besides NVPTX, and found some runtime failures due to the lack of a check for a zero length memcpy/memset before the loop. There is already such a check in the memmove expansion code though. Reviewers: hfinkel Subscribers: jholewinski, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D34707 llvm-svn: 306541
* Revert r306528Nikolai Bozhenov2017-06-281-0/+9
| | | | llvm-svn: 306536
* [GlobalISel][X86] Support bitwise operations : G_AND, G_OR, G_XORIgor Breger2017-06-281-2/+2
| | | | | | | | | | | | | | Summary: Support G_AND, G_OR, G_XOR for i8/i16/i32/i64. Selection done via TableGen'erated code. Reviewers: zvi, guyblank, aymanmus, m_zuckerman Reviewed By: aymanmus Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34605 llvm-svn: 306533
* Reverting commit 306414 on behalf of @gadi.haberMichael Zuckerman2017-06-282-5225/+1634
| | | | llvm-svn: 306532
* [X86] Correct dwarf unwind information in function epiloguePetar Jovanovic2017-06-2813-22/+716
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CFI instructions that set appropriate cfa offset and cfa register are now inserted in emitEpilogue() in X86FrameLowering. Majority of the changes in this patch: 1. Ensure that CFI instructions do not affect code generation. 2. Enable maintaining correct information about cfa offset and cfa register in a function when basic blocks are reordered, merged, split, duplicated. These changes are target independent and described below. Changed CFI instructions so that they: 1. are duplicable 2. are not counted as instructions when tail duplicating or tail merging 3. can be compared as equal Add information to each MachineBasicBlock about cfa offset and cfa register that are valid at its entry and exit (incoming and outgoing CFI info). Add support for updating this information when basic blocks are merged, split, duplicated, created. Add a verification pass (CFIInfoVerifier) that checks that outgoing cfa offset and register of predecessor blocks match incoming values of their successors. Incoming and outgoing CFI information is used by a late pass (CFIInstrInserter) that corrects CFA calculation rule for a basic block if needed. That means that additional CFI instructions get inserted at basic block beginning to correct the rule for calculating CFA. Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D18046 llvm-svn: 306529
* [ValueTracking] Enabling existing ValueTracking patch by default.Nikolai Bozhenov2017-06-281-9/+0
| | | | | | | | | | | | | | | The original patch was an improvement to IR ValueTracking on non-negative integers. It has been checked in to trunk (D18777, r284022). But was disabled by default due to performance regressions. Perf impact has improved. The patch would be enabled by default. Reviewers: reames Differential Revision: https://reviews.llvm.org/D34101 Patch by: Olga Chupina <olga.chupina@intel.com> llvm-svn: 306528
* [InstCombine] Canonicalize clamp of float types to minmax in fast mode.Nikolai Bozhenov2017-06-282-4/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit allows matchSelectPattern to recognize clamp of float arguments in the presence of FMF the same way as already done for integers. This case is a little different though. With integers, given the min/max pattern is recognized, DAGBuilder starts selecting MIN/MAX "automatically". That is not the case for float, because for them only full FMINNAN/FMINNUM/FMAXNAN/FMAXNUM ISD nodes exist and they do care about NaNs. On the other hand, some backends (e.g. X86) have only FMIN/FMAX nodes that do not care about NaNS and the former NAN/NUM nodes are illegal thus selection is not happening. So I decided to do such kind of transformation in IR (InstCombiner) instead of complicating the logic in the backend. Reviewers: spatel, jmolloy, majnemer, efriedma, craig.topper Reviewed By: efriedma Subscribers: hiraditya, javed.absar, n.bozhenov, llvm-commits Patch by Andrei Elovikov <andrei.elovikov@intel.com> Differential Revision: https://reviews.llvm.org/D33186 llvm-svn: 306525
* Recommit "[ELF] - Add ability for DWARFContextInMemory to exit early when ↵George Rimar2017-06-281-9/+21
| | | | | | | | | | | | | | | | | | | | | any error happen." With fix in include folder character case: #include "llvm/Codegen/AsmPrinter.h" -> #include "llvm/CodeGen/AsmPrinter.h" Original commit message: Change introduces error reporting policy for DWARFContextInMemory. New callback provided by client is able to handle error on it's side and return Halt or Continue. That allows to either keep current behavior when parser prints all errors but continues parsing object or implement something very different, like stop parsing on a first error and report an error in a client style. Differential revision: https://reviews.llvm.org/D34328 llvm-svn: 306517
* [ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).Kristof Beyls2017-06-281-1/+1
| | | | | | | | | | | | | | | | The benchmarking summarized in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed this is beneficial for a wide range of cores. As is to be expected, quite a few small adaptations are needed to the regressions tests, as the difference in scheduling results in: - Quite a few small instruction schedule differences. - A few changes in register allocation decisions caused by different instruction schedules. - A few changes in IfConversion decisions, due to a difference in instruction schedule and/or the estimated cost of a branch mispredict. llvm-svn: 306514
* Revert r306512 "[ELF] - Add ability for DWARFContextInMemory to exit early ↵George Rimar2017-06-281-21/+9
| | | | | | | | | | | | | | | | | when any error happen." It broke BB: [13/106] 13 0.022 Generating VCSRevision.h [25/106] 24 1.209 Building CXX object unittests/DebugInfo/DWARF/CMakeFiles/DebugInfoDWARFTests.dir/DWARFDebugInfoTest.cpp.o FAILED: unittests/DebugInfo/DWARF/CMakeFiles/DebugInfoDWARFTests.dir/DWARFDebugInfoTest.cpp.o /home/bb/bin/g++ -DGTEST_HAS_RTTI=0 -DLLVM_BUILD_GLOBAL_ISEL -D_DEBUG -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -Iunittests/DebugInfo/DWARF -I../llvm-project/llvm/unittests/DebugInfo/DWARF -Iinclude -I../llvm-project/llvm/include -I../llvm-project/llvm/utils/unittest/googletest/include -I../llvm-project/llvm/utils/unittest/googlemock/include -fPIC -fvisibility-inlines-hidden -m32 -std=c++11 -Wall -W -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -pedantic -Wno-long-long -Wno-maybe-uninitialized -Wdelete-non-virtual-dtor -Wno-comment -ffunction-sections -fdata-sections -O3 -UNDEBUG -Wno-variadic-macros -fno-exceptions -fno-rtti -MD -MT unittests/DebugInfo/DWARF/CMakeFiles/DebugInfoDWARFTests.dir/DWARFDebugInfoTest.cpp.o -MF unittests/DebugInfo/DWARF/CMakeFiles/DebugInfoDWARFTests.dir/DWARFDebugInfoTest.cpp.o.d -o unittests/DebugInfo/DWARF/CMakeFiles/DebugInfoDWARFTests.dir/DWARFDebugInfoTest.cpp.o -c ../llvm-project/llvm/unittests/DebugInfo/DWARF/DWARFDebugInfoTest.cpp ../llvm-project/llvm/unittests/DebugInfo/DWARF/DWARFDebugInfoTest.cpp:18:37: fatal error: llvm/Codegen/AsmPrinter.h: No such file or directory #include "llvm/Codegen/AsmPrinter.h" ^ compilation terminated. llvm-svn: 306513
* [ELF] - Add ability for DWARFContextInMemory to exit early when any error ↵George Rimar2017-06-281-9/+21
| | | | | | | | | | | | | | | | happen. Change introduces error reporting policy for DWARFContextInMemory. New callback provided by client is able to handle error on it's side and return Halt or Continue. That allows to either keep current behavior when parser prints all errors but continues parsing object or implement something very different, like stop parsing on a first error and report an error in a client style. Differential revision: https://reviews.llvm.org/D34328 llvm-svn: 306512
* [IRCE][NFC] Better get SCEV for 1 in calculateSubRangesMax Kazantsev2017-06-281-3/+3
| | | | | | | | | A slightly more efficient way to get constant, we avoid resolving in getSCEV and excessive invocations, and we don't create a ConstantInt if 'true' branch is taken. Differential Revision: https://reviews.llvm.org/D34672 llvm-svn: 306503
* Revert "[DAG] Fold FrameIndex offset into BaseIndexOffset analysis. NFCI."Nirav Dave2017-06-282-24/+27
| | | | | | This reverts commit r306498 which appears to cause a compilrt-rt test failures llvm-svn: 306501
* [AMDGPU] Add pattern for v_alignbit_b32 with immediateStanislav Mekhanoshin2017-06-282-3/+6
| | | | | | | | If immediate in shift is less than 32 we can use alignbit too. Differential Revision: https://reviews.llvm.org/D34729 llvm-svn: 306500
* Allow to truncate left shift with non-constant shift amountStanislav Mekhanoshin2017-06-281-10/+12
| | | | | | | | | | | That is pretty common for clang to produce code like (shl %x, (and %amt, 31)). In this situation we can still perform trunc (shl) into shl (trunc) conversion given the known value range of shift amount. Differential Revision: https://reviews.llvm.org/D34723 llvm-svn: 306499
* [DAG] Fold FrameIndex offset into BaseIndexOffset analysis. NFCI.Nirav Dave2017-06-282-27/+24
| | | | | | | Pull FrameIndex comparision reasoning from DAGCombiner::isAlias to general BaseIndexOffset. llvm-svn: 306498
* Inlining: Don't re-map simplified cloned instructions.Kyle Butt2017-06-281-4/+5
| | | | | | | | | | | | | When simplifying an instruction that has been re-mapped, it should never simplify to an instruction in the original function. In the edge case where we are inlining a function into itself, the existing code led to incorrect behavior. Replace the incorrect code with an assert verifying that we never expect simplification to produce an instruction in the old function, unless the functions are the same. Differential Revision: https://reviews.llvm.org/D33850 llvm-svn: 306495
* Add missing library dependency.Peter Collingbourne2017-06-281-1/+1
| | | | llvm-svn: 306491
* [COFF, ARM64] Add support for Windows ARM64 COFF formatMandeep Singh Grang2017-06-2715-5/+241
| | | | | | | | | | | | | | | | Summary: This is the llvm part of the initial implementation to support Windows ARM64 COFF format. I will gradually add more functionality in subsequent patches. Reviewers: ruiu, rnk, t.p.northover, compnerd Reviewed By: ruiu, compnerd Subscribers: aemerson, mgorny, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D34705 llvm-svn: 306490
* Object: Teach irsymtab::read() to try to use the irsymtab that we wrote to disk.Peter Collingbourne2017-06-272-7/+55
| | | | | | | | Fixes PR27551. Differential Revision: https://reviews.llvm.org/D33974 llvm-svn: 306488
* Bitcode: Write the irsymtab to disk.Peter Collingbourne2017-06-273-0/+47
| | | | | | Differential Revision: https://reviews.llvm.org/D33973 llvm-svn: 306487
* Object: Add version and producer fields to the irsymtab header. NFCI.Peter Collingbourne2017-06-271-0/+18
| | | | | | | | | These will be necessary in order to handle upgrades from old bitcode files. Differential Revision: https://reviews.llvm.org/D33972 llvm-svn: 306486
* [CGP] add specialization for memcmp expansion with only one basic blockSanjay Patel2017-06-271-1/+41
| | | | llvm-svn: 306485
* [NewPM/Inliner] Reduce threshold for cold callsites in the non-PGO caseEaswaran Raman2017-06-271-1/+30
| | | | | | Differential Revision: https://reviews.llvm.org/D34312 llvm-svn: 306484
* GlobalISel: add some more sanity-checking to MachineInstrBuilder. NFC.Tim Northover2017-06-271-1/+15
| | | | llvm-svn: 306481
* [AArch64] Inline callee if its target-features are a subset of the callerFlorian Hahn2017-06-272-0/+17
| | | | | | | | | | | | | | | | | | | Summary: Similar to X86, it should be safe to inline callees if their target-features are a subset of the caller. This change matches GCC's inlining behavior with respect to attributes [1]. [1] https://gcc.gnu.org/onlinedocs/gcc/AArch64-Function-Attributes.html#AArch64-Function-Attributes Reviewers: kristof.beyls, javed.absar, rengolin, t.p.northover Reviewed By: t.p.northover Subscribers: aemerson, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D34698 llvm-svn: 306478
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