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* [MS Demangler] Properly demangle templated operators.Zachary Turner2018-08-011-31/+43
| | | | | | | | | | | | | | | | | | After we detected the presence of a template via ?$ we would proceed by only demangling a simple unqualified name. This means we would fail on templated operators (and perhaps other yet-to-be-determined things) This was discovered while doing some refactoring to store richer semantic information about the demangled types to pave the way for overhauling the way we handle backreferences. (Specifically, we need to defer recording or resolving back-references until a symbol has been completely demangled, because we need to use information that only occurs later in the mangled string to decide whether a back-reference should be recorded.) Differential Revision: https://reviews.llvm.org/D50145 llvm-svn: 338608
* [MS Demangler] Don't crash as often when demangling.Zachary Turner2018-08-011-10/+28
| | | | | | | We crash a lot on unrecognized inputs. This adds some error handling so we early out when we get unrecognized names. llvm-svn: 338607
* [NFC] small addendum to r334242, FMF propagationMichael Berg2018-08-011-1/+1
| | | | llvm-svn: 338604
* [X86] FastISel fall back on !absolute_symbol GVsVlad Tsyrklevich2018-08-011-0/+4
| | | | | | | | | | | | | | | | | | | Summary: D25878, which added support for !absolute_symbol for normal X86 ISel, did not add support for materializing references to absolute symbols for X86 FastISel. This causes build failures because FastISel generates PC-relative relocations for absolute symbols. Fall back to normal ISel for references to !absolute_symbol GVs. Fix for PR38200. Reviewers: pcc, craig.topper Reviewed By: pcc Subscribers: hiraditya, llvm-commits, kcc Differential Revision: https://reviews.llvm.org/D50116 llvm-svn: 338599
* [X86] Assign from a brace initializer to match style guide. NFCI.Simon Pilgrim2018-08-011-1/+1
| | | | llvm-svn: 338598
* [SelectionDAG] fix bug in translating funnel shift with non-power-of-2 typeSanjay Patel2018-08-011-31/+39
| | | | | | | | | | | | | | | | | | The bug is visible in the constant-folded x86 tests. We can't use the negated shift amount when the type is not power-of-2: https://rise4fun.com/Alive/US1r ...so in that case, use the regular lowering that includes a select to guard against a shift-by-bitwidth. This path is improved by only calculating the modulo shift amount once now. Also, improve the rotate (with power-of-2 size) lowering to use a negate rather than subtract from bitwidth. This improves the codegen whether we have a rotate instruction or not (although we can still see that we're not matching to a legal rotate in all cases). llvm-svn: 338592
* [SelectionDAG] Make binop reduction matcher available to all targetsSimon Pilgrim2018-08-012-65/+64
| | | | | | | | There is nothing x86-specific about this code, so it'd be nice to make this available for other targets to use in the future (and get it out of X86ISelLowering!). Differential Revision: https://reviews.llvm.org/D50083 llvm-svn: 338586
* [NFC][FunctionAttrs] Remove duplication in old/new PM pipelineJohannes Doerfert2018-08-011-33/+29
| | | | | | | | This patch just extract code into a separate function to remove some duplication between the old and new pass manager pipeline. Due to the different CGSCC iterators used, not all code duplication was eliminated. llvm-svn: 338585
* AMDGPU: Allow fp32-denormals feature for r600 targetsJan Vesely2018-08-012-9/+9
| | | | | | | | This was accidentally removed in r335942. Differential Revision: https://reviews.llvm.org/D49934 llvm-svn: 338569
* [FPEnv] Widen illegal width StrictFP vector operations as neededCameron McInally2018-08-012-58/+205
| | | | | | Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
* [AArch64] Fix FCCMP with FP16 operandsBryan Chan2018-08-011-1/+3
| | | | | | | | | | | | | | Summary: This patch adds support for FCCMP instruction with FP16 operands, avoiding an assertion during instruction selection. Reviewers: olista01, SjoerdMeijer, t.p.northover, javed.absar Reviewed By: SjoerdMeijer Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D50115 llvm-svn: 338554
* [X86] Use isNullConstant helper. NFCI.Simon Pilgrim2018-08-011-2/+1
| | | | llvm-svn: 338530
* Fix "not all control paths return a value" MSVC warning.Simon Pilgrim2018-08-011-0/+1
| | | | llvm-svn: 338529
* [MC] Report fatal error for DWARF types for non-ELF object filesJonas Devlieghere2018-08-012-3/+15
| | | | | | | | | | | | | | Getting the DWARF types section is only implemented for ELF object files. We already disabled emitting debug types in clang (r337717), but now we also report an fatal error (rather than crashing) when trying to obtain this section in MC. Additionally we ignore the generate debug types flag for unsupported target triples. See PR38190 for more information. Differential revision: https://reviews.llvm.org/D50057 llvm-svn: 338527
* [AMDGPU] Optimize _L image intrinsic to _LZ when lod is zeroRyan Taylor2018-08-014-2/+53
| | | | | | | | | | | | | | | Summary: Add _L to _LZ image intrinsic table mapping to table gen. In ISelLowering check if image intrinsic has lod and if it's equal to zero, if so remove lod and change opcode to equivalent mapped _LZ. Change-Id: Ie24cd7e788e2195d846c7bd256151178cbb9ec71 Subscribers: arsenm, mehdi_amini, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, steven_wu, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D49483 llvm-svn: 338523
* [SystemZ, TableGen] Fix shift count handlingUlrich Weigand2018-08-015-103/+35
| | | | | | | | | | | | | | | | | | | | | | | | | The DAG combiner logic to simplify AND masks in shift counts is invalid. While it is true that the SystemZ shift instructions ignore all but the low 6 bits of the shift count, it is still invalid to simplify the AND masks while the DAG still uses the standard shift operators (which are *not* defined to match the SystemZ instruction behavior). Instead, this patch performs equivalent operations during instruction selection. For completely removing the AND, this now happens via additional DAG match patterns implemented by a multi-alternative PatFrags. For simplifying a 32-bit AND to a 16-bit AND, the existing DAG patterns were already mostly OK, they just needed an output XForm to actually truncate the immediate value. Unfortunately, the latter change also exposed a bug in TableGen: it seems XForms are currently only handled correctly for direct operands of the outermost operation node. This patch also fixes that bug by simply recurring through the whole pattern. This should be NFC for all other targets. Differential Revision: https://reviews.llvm.org/D50096 llvm-svn: 338521
* [X86] Use isNullConstant helper. NFCI.Simon Pilgrim2018-08-011-2/+1
| | | | llvm-svn: 338516
* [X86] Improved sched models for X86 BT*rr instructions.Andrew V. Tischenko2018-08-0111-48/+18
| | | | | | Differential Revision: https://reviews.llvm.org/D49243 llvm-svn: 338507
* [MIPS GlobalISel] Select global addressPetar Jovanovic2018-08-013-0/+31
| | | | | | | | | | Select G_GLOBAL_VALUE for position dependent code. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D49803 llvm-svn: 338499
* Revert "Enrich inline messages", tests failDavid Bolvansky2018-08-015-152/+111
| | | | llvm-svn: 338496
* Enrich inline messagesDavid Bolvansky2018-08-015-111/+152
| | | | | | | | | | | | | | | | | | | | | | Summary: This patch improves Inliner to provide causes/reasons for negative inline decisions. 1. It adds one new message field to InlineCost to report causes for Always and Never instances. All Never and Always instantiations must provide a simple message. 2. Several functions that used to return the inlining results as boolean are changed to return InlineResult which carries the cause for negative decision. 3. Changed remark priniting and debug output messages to provide the additional messages and related inline cost. 4. Adjusted tests for changed printing. Patch by: yrouban (Yevgeny Rouban) Reviewers: craig.topper, sammccall, sgraenitz, NutshellySima, shchenz, chandlerc, apilipenko, javed.absar, tejohnson, dblaikie, sanjoy, eraman, xbolva00 Reviewed By: tejohnson, xbolva00 Subscribers: xbolva00, llvm-commits, arsenm, mehdi_amini, eraman, haicheng, steven_wu, dexonsmith Differential Revision: https://reviews.llvm.org/D49412 llvm-svn: 338494
* [AArch64] Disallow the MachO specific .loh directive for windowsMartin Storsjo2018-08-011-6/+6
| | | | | | | | Also add a test for it being unsupported for linux. Differential Revision: https://reviews.llvm.org/D49929 llvm-svn: 338493
* [X86] When looking for (CMOV C-1, (ADD (CTTZ X), C), (X != 0)) -> (ADD (CMOV ↵Craig Topper2018-08-011-27/+26
| | | | | | | | | | (CTTZ X), -1, (X != 0)), C), make sure we really have a compare with 0. It's not strictly required by the transform of the cmov and the add, but it makes sure we restrict it to the cases we know we want to match. While there canonicalize the operand order of the cmov to simplify the matching and emitting code. llvm-svn: 338492
* [DWARF] Basic support for producing DWARFv5 .debug_addr sectionVictor Leschuk2018-08-014-2/+31
| | | | | | | | | | | | | | This revision implements support for generating DWARFv5 .debug_addr section. The implementation is pretty straight-forward: we just check the dwarf version and emit section header if needed. Reviewers: aprantl, dblaikie, probinson Reviewed by: dblaikie Differential Revision: https://reviews.llvm.org/D50005 llvm-svn: 338487
* [InstSimplify] fold extracting from std::pair (1/2)Hiroshi Inoue2018-08-011-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch intends to enable jump threading when a method whose return type is std::pair<int, bool> or std::pair<bool, int> is inlined. For example, jump threading does not happen for the if statement in func. std::pair<int, bool> callee(int v) { int a = dummy(v); if (a) return std::make_pair(dummy(v), true); else return std::make_pair(v, v < 0); } int func(int v) { std::pair<int, bool> rc = callee(v); if (rc.second) { // do something } SROA executed before the method inlining replaces std::pair by i64 without splitting in both callee and func since at this point no access to the individual fields is seen to SROA. After inlining, jump threading fails to identify that the incoming value is a constant due to additional instructions (like or, and, trunc). This series of patch add patterns in InstructionSimplify to fold extraction of members of std::pair. To help jump threading, actually we need to optimize the code sequence spanning multiple BBs. These patches does not handle phi by itself, but these additional patterns help NewGVN pass, which calls instsimplify to check opportunities for simplifying instructions over phi, apply phi-of-ops optimization to result in successful jump threading. SimplifyDemandedBits in InstCombine, can do more general optimization but this patch aims to provide opportunities for other optimizers by supporting a simple but common case in InstSimplify. This first patch in the series handles code sequences that merges two values using shl and or and then extracts one value using lshr. Differential Revision: https://reviews.llvm.org/D48828 llvm-svn: 338485
* [DebugInfo] Fix build failed in clang-x86_64-linux-selfhost-modules.Hsiangkai Wang2018-08-011-1/+7
| | | | | | Only generate symbol difference expression if needed. llvm-svn: 338484
* [x86] Fix a really subtle miscompile due to a somewhat glaring bug inChandler Carruth2018-08-011-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EFLAGS copy lowering. If you have a branch of LLVM, you may want to cherrypick this. It is extremely unlikely to hit this case empirically, but it will likely manifest as an "impossible" branch being taken somewhere, and will be ... very hard to debug. Hitting this requires complex conditions living across complex control flow combined with some interesting memory (non-stack) initialized with the results of a comparison. Also, because you have to arrange for an EFLAGS copy to be in *just* the right place, almost anything you do to the code will hide the bug. I was unable to reduce anything remotely resembling a "good" test case from the place where I hit it, and so instead I have constructed synthetic MIR testing that directly exercises the bug in question (as well as the good behavior for completeness). The issue is that we would mistakenly assume any SETcc with a valid condition and an initial operand that was a register and a virtual register at that to be a register *defining* SETcc... It isn't though.... This would in turn cause us to test some other bizarre register, typically the base pointer of some memory. Now, testing this register and using that to branch on doesn't make any sense. It even fails the machine verifier (if you are running it) due to the wrong register class. But it will make it through LLVM, assemble, and it *looks* fine... But wow do you get a very unsual and surprising branch taken in your actual code. The fix is to actually check what kind of SETcc instruction we're dealing with. Because there are a bunch of them, I just test the may-store bit in the instruction. I've also added an assert for sanity that ensure we are, in fact, *defining* the register operand. =D llvm-svn: 338481
* [DebugInfo] Generate fixups as emitting DWARF .debug_line.Hsiangkai Wang2018-08-012-6/+81
| | | | | | | | | | | | | | | | It is necessary to generate fixups in .debug_line as relaxation is enabled due to the address delta may be changed after relaxation. DWARF will record the mappings of lines and addresses in .debug_line section. It will encode the information using special opcodes, standard opcodes and extended opcodes in Line Number Program. I use DW_LNS_fixed_advance_pc to encode fixed length address delta and DW_LNE_set_address to encode absolute address to make it possible to generate fixups in .debug_line section. Differential Revision: https://reviews.llvm.org/D46850 llvm-svn: 338477
* [GlobalISel][IRTranslator] Use RPO traversal when visiting blocks to translate.Amara Emerson2018-08-011-5/+8
| | | | | | | | | | | | Previously we were just visiting the blocks in the function in IR order, which is rather arbitrary. Therefore we wouldn't always visit defs before uses, but the translation code relies on this assumption in some places. Only codegen change seen in tests is an elision of a redundant copy. Fixes PR38396 llvm-svn: 338476
* AMDGPU: Add clamp bit to dot intrinsicsKonstantin Zhuravlyov2018-08-013-12/+33
| | | | | | Differential Revision: https://reviews.llvm.org/D49874 llvm-svn: 338470
* Simplify selectELFSectionForGlobal by pulling out the entry sizeEric Christopher2018-08-011-22/+27
| | | | | | determination for mergeable sections into a small static function. llvm-svn: 338469
* Tidy up logic around unique section name creation and remove aEric Christopher2018-08-011-9/+9
| | | | | | mostly unused variable. llvm-svn: 338468
* [MachineOutliner] Clean up subtarget handling.Eli Friedman2018-08-011-23/+22
| | | | | | | | | | | | | | Call shouldOutlineFromFunctionByDefault, isFunctionSafeToOutlineFrom, getOutliningType, and getMachineOutlinerMBBFlags using the correct TargetInstrInfo. And don't create a MachineFunction for a function declaration. The call to getOutliningCandidateInfo is still a little weird, but at least the weirdness is explicitly called out. Differential Revision: https://reviews.llvm.org/D49880 llvm-svn: 338465
* Revert r338354 "[ARM] Revert r337821"Reid Kleckner2018-07-311-1/+1
| | | | | | | | | | | | | | | | | Disable ARMCodeGenPrepare by default again. It is causing verifier failues in V8 that look like: Duplicate integer as switch case switch i32 %trunc, label %if.end13 [ i32 0, label %cleanup36 i32 0, label %if.then8 ], !dbg !4981 i32 0 fatal error: error in backend: Broken function found, compilation aborted! I will continue reducing the test case and send it along. llvm-svn: 338452
* [DWARF] Support for .debug_addr (consumer)Victor Leschuk2018-07-313-10/+252
| | | | | | | This patch implements basic support for parsing and dumping DWARFv5 .debug_addr section. llvm-svn: 338447
* [SLC] Refactor the simplication of pow() (NFC)Evandro Menezes2018-07-311-20/+16
| | | | | | Reword comments and minor code reformatting. llvm-svn: 338446
* Revert r338431: "Add DebugCounters to DivRemPairs"George Burgess IV2018-07-311-6/+0
| | | | | | | This reverts r338431; the test it added is making buildbots unhappy. Locally, I can repro the failure on reverse-iteration builds. llvm-svn: 338442
* [DWARF] Do not create a .debug_ranges section when no ranges are needed.Wolfgang Pieb2018-07-311-1/+1
| | | | | | | | Reviewers: aprantl Differential Revision: https://reviews.llvm.org/D50089 llvm-svn: 338437
* Add DebugCounters to DivRemPairsGeorge Burgess IV2018-07-311-0/+6
| | | | | | | | | | For people who don't use DebugCounters, NFCI. Patch by Zhizhou Yang! Differential Revision: https://reviews.llvm.org/D50033 llvm-svn: 338431
* [SystemZ] Fix bad assert composition.Jonas Paulsson2018-07-311-1/+1
| | | | | | Use '&&' before the string instead of '||' llvm-svn: 338429
* DAG: Correct pointer type used for stack slotMatt Arsenault2018-07-311-1/+2
| | | | | | | | | | Correct the address space for the inserted argument stack slot. AMDGPU seems to not do anything with this information, so I don't think this was breaking anything. llvm-svn: 338428
* AMDGPU: Break 64-bit arguments into 32-bit piecesMatt Arsenault2018-07-311-3/+16
| | | | llvm-svn: 338421
* AMDGPU: Split wide vectors of i16/f16 into 32-bit regs on callsMatt Arsenault2018-07-311-2/+24
| | | | | | | This improves code for the same reasons as scalarizing 32-bit element vectors. llvm-svn: 338418
* [CodeView] Minimal support for S_UNAMESPACE recordsAlexandre Ganea2018-07-315-1/+23
| | | | | | Differential Revision: https://reviews.llvm.org/D50007 llvm-svn: 338417
* AMDGPU: Scalarize vector argument types to callsMatt Arsenault2018-07-311-31/+15
| | | | | | | | | | | | | | | | | When lowering calling conventions, prefer to decompose vectors into the constitute register types. This avoids artifical constraints to satisfy a wide super-register. This improves code quality because now optimizations don't need to deal with the super-register constraint. For example the immediate folding code doesn't deal with 4 component reg_sequences, so by breaking the register down earlier the existing immediate folding code is able to work. This also avoids the need for the shader input processing code to manually split vector types. llvm-svn: 338416
* [X86] WriteBSWAP sched classes are reg-reg only.Simon Pilgrim2018-07-3110-20/+20
| | | | | | | Don't declare them as X86SchedWritePair when the folded class will never be used. Note: MOVBE (load/store endian conversion) instructions tend to have a very different behaviour to BSWAP. llvm-svn: 338412
* Revert "[DebugInfo] Generate DWARF debug information for labels."Vlad Tsyrklevich2018-07-3116-406/+149
| | | | | | | This reverts commits r338390 and r338398, they were causing LSan failures on the ASan bot. llvm-svn: 338408
* [X86][SSE] Use ISD::MULHU for constant/non-zero ISD::SRL lowering (PR38151)Simon Pilgrim2018-07-311-0/+18
| | | | | | | | | | As was done for vector rotations, we can efficiently use ISD::MULHU for vXi8/vXi16 ISD::SRL lowering. Shift-by-zero cases are still problematic (mainly on v32i8 due to extra AND/ANDN/OR or VPBLENDVB blend masks but v8i16/v16i16 aren't great either if PBLENDW fails) so I've limited this first patch to known non-zero cases if we can't easily use PBLENDW. Differential Revision: https://reviews.llvm.org/D49562 llvm-svn: 338407
* Make ICF log output order deterministic.Rui Ueyama2018-07-311-0/+4
| | | | | | | | | | This patch does the same thing as r338153 for COFF. Note that this patch affects only the order of log messages. The output file is already deterministic. Differential Revision: https://reviews.llvm.org/D50023 llvm-svn: 338406
* Resubmit r338340 "[MS Demangler] Better demangling of template arguments."Zachary Turner2018-07-311-45/+87
| | | | | | This broke the build with GCC, but has since been fixed. llvm-svn: 338403
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