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* Remove redundant includes from lib/Target/*.cpp.Michael Zolotukhin2017-12-133-5/+0
| | | | llvm-svn: 320633
* Remove redundant includes from various places.Michael Zolotukhin2017-12-134-7/+0
| | | | llvm-svn: 320629
* Remove redundant includes from lib/Transforms.Michael Zolotukhin2017-12-1331-48/+0
| | | | llvm-svn: 320628
* Remove redundant includes from lib/Support.Michael Zolotukhin2017-12-136-6/+0
| | | | llvm-svn: 320627
* Remove redundant includes from lib/ProfileData.Michael Zolotukhin2017-12-132-9/+0
| | | | llvm-svn: 320626
* Remove redundant includes from lib/Object.Michael Zolotukhin2017-12-133-13/+0
| | | | llvm-svn: 320625
* Remove redundant includes from lib/MC.Michael Zolotukhin2017-12-1310-19/+0
| | | | llvm-svn: 320624
* Remove redundant includes from lib/LTO.Michael Zolotukhin2017-12-133-9/+0
| | | | llvm-svn: 320623
* Remove redundant includes from lib/IR.Michael Zolotukhin2017-12-139-12/+0
| | | | llvm-svn: 320622
* Remove redundant includes from lib/ExecutionEngine.Michael Zolotukhin2017-12-133-4/+0
| | | | llvm-svn: 320621
* Remove redundant includes from lib/DebugInfo.Michael Zolotukhin2017-12-1324-33/+0
| | | | llvm-svn: 320620
* Remove redundant includes from lib/CodeGen.Michael Zolotukhin2017-12-1332-56/+0
| | | | llvm-svn: 320619
* Remove redundant includes from lib/Bitcode.Michael Zolotukhin2017-12-132-5/+0
| | | | llvm-svn: 320618
* Remove redundant includes from lib/Analysis.Michael Zolotukhin2017-12-1312-14/+0
| | | | llvm-svn: 320617
* AMDGPU: Partially fix disassembly of MIMG instructionsMatt Arsenault2017-12-138-78/+128
| | | | | | | | | | | | | | | | | | | | | Stores failed to decode at all since they didn't have a DecoderNamespace set. Loads worked, but did not change the register width displayed to match the numbmer of enabled channels. The number of printed registers for vaddr is still wrong, but I don't think that's encoded in the instruction so there's not much we can do about that. Image atomics are still broken. MIMG is the same encoding for SI/VI, but the image atomic classes are split up into encoding specific versions unlike every other MIMG instruction. They have isAsmParserOnly set on them for some reason. dmask is also special for these, so we probably should not have it as an explicit operand as it is now. llvm-svn: 320614
* [JumpThreading] Preservation of DT and LVI across the passBrian M. Rzycki2017-12-135-89/+365
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: See D37528 for a previous (non-deferred) version of this patch and its description. Preserves dominance in a deferred manner using a new class DeferredDominance. This reduces the performance impact of updating the DominatorTree at every edge insertion and deletion. A user may call DDT->flush() within JumpThreading for an up-to-date DT. This patch currently has one flush() at the end of runImpl() to ensure DT is preserved across the pass. LVI is also preserved to help subsequent passes such as CorrelatedValuePropagation. LVI is simpler to maintain and is done immediately (not deferred). The code to perfom the preversation was minimally altered and was simply marked as preserved for the PassManager to be informed. This extends the analysis available to JumpThreading for future enhancements. One example is loop boundary threading. Reviewers: dberlin, kuhar, sebpop Reviewed By: kuhar, sebpop Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40146 llvm-svn: 320612
* [GVNHoist] Fix: PR35222 gvn-hoist incorrectly erases loadAditya Kumar2017-12-131-2/+2
| | | | | | | | | | | | | | w.r.t. the paper "A Practical Improvement to the Partial Redundancy Elimination in SSA Form" (https://sites.google.com/site/jongsoopark/home/ssapre.pdf) Proper dominance check was missing here, so having a loopinfo should not be required. Committing this diff as this fixes the bug, if there are further concerns, I'll be happy to work on them. Differential Revision: https://reviews.llvm.org/D39781 llvm-svn: 320607
* Ignore metainstructions during the shrink wrap analysisAdrian Prantl2017-12-131-0/+4
| | | | | | | | | | Shrink wrapping should ignore DBG_VALUEs referring to frame indices, since the presence of debug information must not affect code generation. Differential Revision: https://reviews.llvm.org/D41187 llvm-svn: 320606
* Fix link failure on one build bot introduced by r320584.Nemanja Ivanovic2017-12-131-1/+3
| | | | llvm-svn: 320589
* Reverted r320229. It broke tests on builder ↵Galina Kistanova2017-12-131-118/+4
| | | | | | llvm-clang-x86_64-expensive-checks-win. llvm-svn: 320588
* [PowerPC] MachineSSA pass to reduce the number of CR-logical operationsNemanja Ivanovic2017-12-135-0/+740
| | | | | | | | | | | | | | The initial implementation of an MI SSA pass to reduce cr-logical operations. Currently, the only operations handled by the pass are binary operations where both CR-inputs come from the same block and the single use is a conditional branch (also in the same block). Committing this off by default to allow for a period of field testing. Will enable it by default in a follow-up patch soon. Differential Revision: https://reviews.llvm.org/D30431 llvm-svn: 320584
* [X86] Add RDMSR/WRMSR, RDPMC + RDTSC/RDTSCP schedule testsSimon Pilgrim2017-12-133-1/+4
| | | | | | Add missing RDTSCP itinerary llvm-svn: 320581
* [RISCV] Define sfence.vma InstAliases to match the GNU RISC-V toolsAlex Bradbury2017-12-131-0/+3
| | | | | | | | Unfortunately these aren't defined explicitly in the privileged spec, but the GNU assembler does accept `sfence.vma` and `sfence.vma rs` as well as the usual `sfence.vma rs, rt`. llvm-svn: 320575
* [FuzzMutate] Only generate loads and stores to the first class sized typesIgor Laevsky2017-12-131-1/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D41109 llvm-svn: 320573
* [FuzzMutate] Correctly split landingpad blocksIgor Laevsky2017-12-131-2/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D41112 llvm-svn: 320571
* [X86][SSE] MOVMSK only uses the sign bit from each vector elementSimon Pilgrim2017-12-131-0/+22
| | | | | | | | | | Pass the input vector through SimplifyDemandedBits as we only need the sign bit from each vector element of MOVMSK We'd probably get more hits if SimplifyDemandedBits was better at handling vectors... Differential Revision: https://reviews.llvm.org/D41119 llvm-svn: 320570
* [RISCV] Implement floating point assembler pseudo instructionsAlex Bradbury2017-12-132-0/+46
| | | | | | | | | | | | | | | Adds the assembler aliases for the floating point instructions which can be mapped to a single canonical instruction. The missing pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other things, like for example PCREL_LO, have to be implemented first. This patch builds upon D40902. Differential Revision: https://reviews.llvm.org/D41071 Patch by Mario Werner. llvm-svn: 320569
* Reintroduce r320049, r320014 and r319894.Igor Laevsky2017-12-132-0/+32
| | | | | | OpenGL issues should be fixed by now. llvm-svn: 320568
* [DAG] Promote ADDCARRY / SUBCARRYRoger Ferrer Ibanez2017-12-131-1/+24
| | | | | | | | Add missing case that was not implemented yet. Differential Revision: https://reviews.llvm.org/D38942 llvm-svn: 320567
* [CodeGen] Print jump-table index operands as %jump-table.0 in both MIR and ↵Francis Visoiu Mistrih2017-12-133-6/+9
| | | | | | | | | | debug output Work towards the unification of MIR and debug output by printing `%jump-table.0` instead of `<jt#0>`. Only debug syntax is affected. llvm-svn: 320566
* [CodeGen] Print target index operands as target-index(target-specific) + 8 ↵Francis Visoiu Mistrih2017-12-132-28/+24
| | | | | | | | | | in both MIR and debug output Work towards the unification of MIR and debug output by printing `target-index(target-specific) + 8` instead of `<ti#0+8>` and `target-index(target-specific) + 8` instead of `<ti#0-8>`. Only debug syntax is affected. llvm-svn: 320565
* [CodeGen] Print constant pool index operands as %const.0 + 8 in both MIR and ↵Francis Visoiu Mistrih2017-12-132-9/+14
| | | | | | | | | | | | | | debug output Work towards the unification of MIR and debug output by printing `%const.0 + 8` instead of `<cp#0+8>` and `%const.0 - 8` instead of `<cp#0-8>`. Only debug syntax is affected. Differential Revision: https://reviews.llvm.org/D41116 llvm-svn: 320564
* [mips] Provide additional DSP bitconvert patternsStefan Maksimovic2017-12-131-0/+4
| | | | | | | | | Previously, v2i16 -> f32 bitcast could not be matched. Add patterns to support matching this and similar types of bitcasts. Differential revision: https://reviews.llvm.org/D40959 llvm-svn: 320562
* [RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming ↵Alex Bradbury2017-12-132-98/+100
| | | | | | | | | | | | | | convention When an instruction mnemonic contains a '.', we usually name the instruction with a _ in that place. e.g. fadd.s -> FADD_S. This patch updates RISCVInstrInfoC.td to do the same, e.g. c.nop -> C_NOP. Also includes some minor formatting changes in RISCVInstrInfoC.td to better align it with the formatting conventions in the rest of the backend. llvm-svn: 320560
* [RISCV][NFC] Put isSImm6 and simm6 td definition in correct sorted positionAlex Bradbury2017-12-132-22/+22
| | | | | | | We sort these helper functions and td definitions by bit width. simm6 was previously out-of-order with respect to the others. llvm-svn: 320559
* [RISCV] MC layer support for the remaining RVC instructionsAlex Bradbury2017-12-135-20/+390
| | | | | | | | Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
* Revert "[CGP] Enable select in complex addr mode"Serguei Katkov2017-12-131-1/+1
| | | | | | | | Causes: Assertion `ScaledReg == nullptr' failed. This actually a revert of rL320551. llvm-svn: 320553
* [Targets] Don't automatically include the scheduler class enum from ↵Craig Topper2017-12-133-0/+4
| | | | | | | | | | *GenInstrInfo.inc with GET_INSTRINFO_ENUM. Make targets request is separately. Most of the targets don't need the scheduler class enum. I have an X86 scheduler model change that causes some names in the enum to become about 18000 characters long. This is because using instregex in scheduler models causes the scheduler class to get named with every instruction that matches the regex concatenated together. MSVC has a limit of 4096 characters for an identifier name. Rather than trying to come up with way to reduce the name length, I'm just going to sidestep the problem by not including the enum in X86. llvm-svn: 320552
* [CGP] Enable select in complex addr modeSerguei Katkov2017-12-131-1/+1
| | | | | | | | | | | Enable select instruction handling in complex addr modes. Reviewers: john.brawn, reames, aaboud Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40634 llvm-svn: 320551
* [NFC] Refactor SafepointIRVerifierSerguei Katkov2017-12-131-236/+317
| | | | | | | | | | | | | | Now two classes are responsible for verification: one of them can track GC pointers and know whether a pointer is relocated or not and another based on that information can verify uses of GC pointers. Patch Author: Daniil Suchkov Reviewers: mkazantsev, anna, apilipenko Reviewed By: mkazantsev Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40885 llvm-svn: 320549
* [SLP] Vectorize jumbled memory loads.Mohammad Shahid2017-12-132-83/+266
| | | | | | | | | | | | | | | | | | | | | | Summary: This patch tries to vectorize loads of consecutive memory accesses, accessed in non-consecutive or jumbled way. An earlier attempt was made with patch D26905 which was reverted back due to some basic issue with representing the 'use mask' of jumbled accesses. This patch fixes the mask representation by recording the 'use mask' in the usertree entry. Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df Reviewers: mkuper, loladiro, Ayal, zvi, danielcdh Reviewed By: Ayal Subscribers: mgrang, dcaballe, hans, mzolotukhin Differential Revision: https://reviews.llvm.org/D36130 llvm-svn: 320548
* [CallSiteSplitting] Refactor creating callsites.Florian Hahn2017-12-131-115/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change makes the call site creation more general if any of the arguments is predicated on a condition in the call site's predecessors. If we find a callsite, that potentially can be split, we collect the set of conditions for the call site's predecessors (currently only 2 predecessors are allowed). To do that, we traverse each predecessor's predecessors as long as it only has single predecessors and record the condition, if it is relevant to the call site. For each condition, we also check if the condition is taken or not. In case it is not taken, we record the inverse predicate. We use the recorded conditions to create the new call sites and split the basic block. This has 2 benefits: (1) it is slightly easier to see what is going on (IMO) and (2) we can easily extend it to handle more complex control flow. Reviewers: davidxl, junbuml Reviewed By: junbuml Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40728 llvm-svn: 320547
* Rename LiveIntervalAnalysis.h to LiveIntervals.hMatthias Braun2017-12-1353-53/+55
| | | | | | | | | | Headers/Implementation files should be named after the class they declare/define. Also eliminated an `#include "llvm/CodeGen/LiveIntervalAnalysis.h"` in favor of `class LiveIntarvals;` llvm-svn: 320546
* Remove unnecessary includes; NFCMatthias Braun2017-12-131-0/+2
| | | | llvm-svn: 320545
* [hwasan] Inline instrumentation & fixed shadow.Evgeniy Stepanov2017-12-131-3/+48
| | | | | | | | | | | | Summary: This brings CPU overhead on bzip2 down from 5.5x to 2x. Reviewers: kcc, alekseyshl Subscribers: kubamracek, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D41137 llvm-svn: 320538
* reverting out -r320532 because a warning is breaking the lld buildMichael Trent2017-12-131-23/+1
| | | | llvm-svn: 320534
* Updated llvm-objdump to display local relocations in Mach-O binariesMichael Trent2017-12-121-1/+23
| | | | | | | | | | | | | | | | | | Summary: llvm-objdump's Mach-O parser was updated in r306037 to display external relocations for MH_KEXT_BUNDLE file types. This change extends the Macho-O parser to display local relocations for MH_PRELOAD files. When used with the -macho option relocations will be displayed in a historical format. rdar://35778019 Reviewers: enderby Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41061 llvm-svn: 320532
* [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev2017-12-121-4/+20
| | | | | | | | | | | | | | | | | Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320525
* [Hexagon] Better detection of identity and undef masks in shufflesKrzysztof Parzyszek2017-12-121-3/+17
| | | | llvm-svn: 320523
* [Hexagon] Fix wrong order of operands for vmuxKrzysztof Parzyszek2017-12-121-1/+1
| | | | | | | | | | | | Shuffle generation uses vmux to collapse vectors resulting from two individual shuffles into one. The indexes of the elements selected from the first operand were indicated by 0xFF in the constant vector used in the compare instruction, but the compare (veqb) set the bits corresponding to the 0x00 elements, thus inverting the selection. Reverse the order of operands to vmux to get the correct output. llvm-svn: 320516
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