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* [Hexagon] Factor out some common code in HexagonEarlyIfConv.cpp, NFCKrzysztof Parzyszek2017-04-031-12/+10
| | | | llvm-svn: 299367
* Revert r299337 "[InstCombine] Remove redundant combine from visitAnd"Craig Topper2017-04-032-0/+89
| | | | | | | | One of the tsan bots started failing at this commit. I don't see anything obviously wrong with the commit so trying this to see if it recovers. Failing log: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/6792 llvm-svn: 299366
* [InstCombine] fix formatting for foldLogOpOfMaskedICmps and related bits; NFCISanjay Patel2017-04-031-145/+158
| | | | | | | | | | | | 1. Improve enum, function, and variable names. 2. Improve comments. 3. Fix variable capitalization. 4. Run clang-format. As an existing code comment suggests, this should work with vector types / splat constants too, so making this look right first will reduce the diffs needed for that change. llvm-svn: 299365
* [APInt] Move isMask and isShiftedMask out of APIntOps and into the APInt ↵Craig Topper2017-04-036-9/+9
| | | | | | | | | | class. Implement them without memory allocation for multiword This moves the isMask and isShiftedMask functions to be class methods. They now use the MathExtras.h function for single word size and leading/trailing zeros/ones or countPopulation for the multiword size. The previous implementation made multiple temorary memory allocations to do the bitwise arithmetic operations to match the MathExtras.h implementation. Differential Revision: https://reviews.llvm.org/D31565 llvm-svn: 299362
* [DAGCombiner] Check limits before accessing array element (PR32502)Simon Pilgrim2017-04-031-1/+1
| | | | llvm-svn: 299361
* ARMAsmParser: clean up of isImmediate functionsSjoerd Meijer2017-04-035-238/+139
| | | | | | | | | | | | | | | | | - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
* [InstCombine] Make foldOpWithConstantIntoOperand take a BinaryOperator ↵Craig Topper2017-04-032-2/+2
| | | | | | | | instead of a generic Instruction. It blindly assumes there are two operands so make it explicit. llvm-svn: 299351
* [InstCombine] Remove a And transform that should be handled by ↵Craig Topper2017-04-031-7/+0
| | | | | | SimplifyDemandedInstructionBits. NFCI llvm-svn: 299349
* [APInt] Make use of whichWord and maskBit to simplify some code. NFCCraig Topper2017-04-021-5/+3
| | | | llvm-svn: 299342
* [APInt] Add a public typedef for the internal type of APInt use it instead ↵Craig Topper2017-04-022-81/+85
| | | | | | | | | | | | | | | | of integerPart. Make APINT_BITS_PER_WORD and APINT_WORD_SIZE public. This patch is one step to attempt to unify the main APInt interface and the tc functions used by APFloat. This patch adds a WordType to APInt and uses that in all the tc functions. I've added temporary typedefs to APFloat to alias it to integerPart to keep the patch size down. I'll work on removing that in a future patch. In future patches I hope to reuse the tc functions to implement some of the main APInt functionality. I may remove APINT_ from BITS_PER_WORD and WORD_SIZE constants so that we don't have the repetitive APInt::APINT_ externally. Differential Revision: https://reviews.llvm.org/D31523 llvm-svn: 299341
* [InstCombine] Make InstCombiner::OptAndOp take a BinaryOperator instead of ↵Craig Topper2017-04-022-4/+4
| | | | | | | | | | an Instruction. The callers have already performed the necessary cast before calling. This allows us to remove a comment that says the instruction must be a BinaryOperator and make it explicit in the argument type. Had to add a default case to the switch because BinaryOperator::getOpcode() returns a BinaryOps enum. llvm-svn: 299339
* [X86][MMX] Improve support for folding fptosi from XMM to MMXSimon Pilgrim2017-04-021-0/+10
| | | | llvm-svn: 299338
* [InstCombine] Remove redundant combine from visitAndCraig Topper2017-04-022-89/+0
| | | | | | | | | | As far as I can tell this combine is fully handled by SimplifyDemandedInstructionBits. I was only looking at this because it is the only user of APIntOps::isShiftedMask which is itself broken. As demonstrated by r299187. I was going to fix isShiftedMask and needed to make sure we had coverage for the new cases it would expose to this combine. But looks like we can nuke it instead. Differential Revision: https://reviews.llvm.org/D31543 llvm-svn: 299337
* [X86][MMX] Simplify tablegen patterns by always combining MOVDQ2Q from v2i64Simon Pilgrim2017-04-021-1/+2
| | | | llvm-svn: 299336
* [X86][MMX] Added support for subvector extraction to MMX registerSimon Pilgrim2017-04-021-2/+4
| | | | llvm-svn: 299335
* NewGVN: Handle coercion of constant stores, loads, memory insts.Daniel Berlin2017-04-021-1/+93
| | | | | | | | | | | | | | | | | Summary: Depends on D30928. This adds support for coercion of stores and memory instructions that do not require insertion to process. Another few tests down. I added the relevant tests from rle.ll Reviewers: davide Subscribers: llvm-commits, Prazek Differential Revision: https://reviews.llvm.org/D30929 llvm-svn: 299330
* [BypassSlowDivision] Do not bypass division of hash-like valuesNikolai Bozhenov2017-04-021-12/+81
| | | | | | | | | | | | | | | | | Disable bypassing if one of the operands looks like a hash value. Slow division often occurs in hashtable implementations and fast division is never taken there because a hash value is extremely unlikely to have enough upper bits set to zero. A value is considered to be hash-like if it is produced by 1) XOR operation 2) Multiplication by a constant wider than the shorter type 3) PHI node with all incoming values being hash-like Differential Revision: https://reviews.llvm.org/D28200 llvm-svn: 299329
* [X86] Use tcAdd/tcSubtract to implement the slow case of operator+=/operator-=.Craig Topper2017-04-021-33/+3
| | | | llvm-svn: 299326
* [APInt] Combine declaration and initialization. NFCCraig Topper2017-04-021-6/+2
| | | | llvm-svn: 299325
* [APInt] Simplify some code by using operator+=(uint64_t) instead of doing a ↵Craig Topper2017-04-021-7/+2
| | | | | | more complex assignment into a temporary APInt just to use the APInt operator+=. llvm-svn: 299324
* [APInt] Fix typo in comment. NFCCraig Topper2017-04-021-1/+1
| | | | llvm-svn: 299323
* MemorySSA: Add support for caching clobbering access in storesDaniel Berlin2017-04-022-9/+9
| | | | | | | | | | | | | | | | Summary: This enables us to cache the clobbering access for stores, despite the fact that we can't rewrite the use-def chains themselves. Early testing shows that, after this change, for larger testcases, it will be a significant net positive (memory and time) to remove the walker caching. Reviewers: george.burgess.iv, davide Subscribers: Prazek, llvm-commits Differential Revision: https://reviews.llvm.org/D31567 llvm-svn: 299322
* [APInt] Use conditional operator to simplify some code. NFCCraig Topper2017-04-011-4/+1
| | | | llvm-svn: 299320
* [APInt] Implement flipAllBitsSlowCase with tcComplement. NFCICraig Topper2017-04-011-2/+1
| | | | llvm-svn: 299319
* [APInt] Fix indentation. NFCCraig Topper2017-04-011-8/+8
| | | | llvm-svn: 299318
* [APInt] Implement AndAssignSlowCase using tcAnd. Do the same for Or and Xor. ↵Craig Topper2017-04-011-9/+3
| | | | | | NFCI llvm-svn: 299317
* [APInt] Allow GreatestCommonDivisor to take rvalue inputs efficiently. Use ↵Craig Topper2017-04-011-6/+4
| | | | | | | | | | | | | | | | | | | moves instead of copies in the loop. Summary: GreatestComonDivisor currently makes a copy of both its inputs. Then in the loop we do one move and two copies, plus any allocation the urem call does. This patch changes it to take its inputs by value so that we can do a move of any rvalue inputs instead of copying. Then in the loop we do 3 move assignments and no copies. This way the only possible allocations we have in the loop is from the urem call. Reviewers: dblaikie, RKSimon, hans Reviewed By: dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31572 llvm-svn: 299314
* [WASM] Remove other comparison of unsigned expression >= 0.Davide Italiano2017-04-011-3/+3
| | | | | | This should finally fix the GCC 7 build with -Werror. llvm-svn: 299313
* [WASM] Remove a set but never used variable.Davide Italiano2017-04-011-4/+1
| | | | llvm-svn: 299312
* [WASM] Remove an assertion that can never fire.Davide Italiano2017-04-011-2/+2
| | | | | | uint* is by definition always >=0. llvm-svn: 299311
* [AMDGPU] Garbage collect now unused dead code. NFCI.Davide Italiano2017-04-011-10/+0
| | | | llvm-svn: 299310
* [InstSimplify] add constant folding for fdiv/fremSanjay Patel2017-04-011-70/+49
| | | | | | Also, add a helper function so we don't have to repeat this code for each binop. llvm-svn: 299309
* fix formatting; NFCSanjay Patel2017-04-011-34/+35
| | | | llvm-svn: 299307
* [DAGCombiner] enable vector transforms for any/all {sign} bits set/clearSanjay Patel2017-04-011-13/+17
| | | | | | | | The code already allowed vector types in via "isInteger" (which might want a more specific name), so use splat-friendly constant predicates to match those types. llvm-svn: 299304
* NewGVN: Don't try to kill off the stored value of stores whenDaniel Berlin2017-04-011-9/+22
| | | | | | | | | | | | | processing the congruence class of the store. Because we use the stored value of a store as the def, it isn't dead just because it appears as a def when it comes from a store. Note: I have not hit any cases with the memory code as it is where this breaks anything, just because of what memory congruences we actually allow. In a followup that improves memory congruence, this bug actually breaks real stuff (but the verifier catches it). llvm-svn: 299300
* NewGVN: Clean up GVNExpression memory hierarchy, restructure hash ↵Daniel Berlin2017-04-011-16/+8
| | | | | | computation a bit so we don't have to redefine it for loads, stores, and calls llvm-svn: 299299
* NewGVN: Use def_chain iterator in singleReachablePhiPath instead of recursionDaniel Berlin2017-04-011-20/+24
| | | | llvm-svn: 299298
* Move def_chain iterator to MemorySSA.h so it can be reusedDaniel Berlin2017-04-011-36/+0
| | | | llvm-svn: 299297
* MemorySSA: Push const correctness further.Daniel Berlin2017-04-011-8/+10
| | | | llvm-svn: 299295
* MemorySSA: Kill the WalkTargetCache now that we have getBlockDefs.Daniel Berlin2017-04-011-39/+6
| | | | llvm-svn: 299294
* [APInt] Remove the mul/urem/srem/udiv/sdiv functions from the APIntOps ↵Craig Topper2017-04-012-2/+2
| | | | | | namespace. Replace the few usages with calls to the class methods. NFC llvm-svn: 299292
* [DAGCombiner] Fix fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, ↵Craig Topper2017-04-011-1/+1
| | | | | | | | | | B, Mask) to explicitly ensure that only one of the inputs of each shuffle is a zero vector. This can only happen when we have a mix of zero and undef elements and the two vectors have a different arrangement of zeros/undefs. The shuffle should eventually be constant folded to all zeros. Fixes PR32484. llvm-svn: 299291
* Revert "Feature generic option to setup start/stop-after/before"Quentin Colombet2017-04-011-61/+0
| | | | | | | | This reverts commit r299282. Didn't intend to commit this :( llvm-svn: 299288
* Revert "Localizer fun"Quentin Colombet2017-04-013-122/+0
| | | | | | | | This reverts commit r299283. Didn't intend to commit this :( llvm-svn: 299287
* Revert "Instrument SDISel C++ patterns"Quentin Colombet2017-04-013-369/+356
| | | | | | | | This reverts commit r299284. Didn't intend to commit this :( llvm-svn: 299286
* [RegBankSelect] Support REG_SEQUENCE for generic mappingQuentin Colombet2017-04-011-8/+18
| | | | | | | | | | | | | | | | REG_SEQUENCE falls into the same category as COPY for operands mapping: - They don't have MCInstrDesc with register constraints - The input variable could use whatever register classes - It is possible to have register class already assigned to the operands In particular, given REG_SEQUENCE are always target specific because of the subreg indices. Those indices must apply to the register class of the definition of the REG_SEQUENCE and therefore, the target must set a register class to that definition. As a result, the generic code can always use that register class to derive a valid mapping for a REG_SEQUENCE. llvm-svn: 299285
* Instrument SDISel C++ patternsQuentin Colombet2017-04-013-356/+369
| | | | llvm-svn: 299284
* Localizer funQuentin Colombet2017-04-013-0/+122
| | | | | | WIP llvm-svn: 299283
* Feature generic option to setup start/stop-after/beforeQuentin Colombet2017-04-011-0/+61
| | | | | | | | | | | | | This patch refactors the code used in llc such that all the users of the addPassesToEmitFile API have access to a homogeneous way of handling start/stop-after/before options right out of the box. Previously each user would have needed to duplicate this logic and set up its own options. NFC llvm-svn: 299282
* Reduce the number of times we query the subtarget for the same information.Eric Christopher2017-03-311-5/+4
| | | | llvm-svn: 299278
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