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* GlobalISel: Fix widenScalar for pointer typed G_MERGE_VALUESMatt Arsenault2019-07-031-1/+1
| | | | llvm-svn: 365093
* [Bitcode] Move Bitstream to a separate libraryFrancis Visoiu Mistrih2019-07-0312-7/+61
| | | | | | | | | | | | | | | | | | | | | | | | | This moves Bitcode/Bitstream*, Bitcode/BitCodes.h to Bitstream/. This is needed to avoid a circular dependency when using the bitstream code for parsing optimization remarks. Since Bitcode uses Core for the IR part: libLLVMRemarks -> Bitcode -> Core and Core uses libLLVMRemarks to generate remarks (see IR/RemarkStreamer.cpp): Core -> libLLVMRemarks we need to separate the Bitstream and Bitcode part. For clang-doc, it seems that it doesn't need the whole bitcode layer, so I updated the CMake to only use the bitstream part. Differential Revision: https://reviews.llvm.org/D63899 llvm-svn: 365091
* Revert "[AMDGPU] Kernel arg metadata: added support for "__hip_texture" type."Matt Arsenault2019-07-031-10/+0
| | | | | | | | This reverts commit r365073. This is crashing, and is improperly relying on IR type names. llvm-svn: 365087
* Teach ValueTracking that aarch64.irg result aliases its input.Evgeniy Stepanov2019-07-031-1/+2
| | | | | | | | | | | | Reviewers: javed.absar, olista01 Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64103 llvm-svn: 365079
* [LFTR] Use SCEVExpander for the pointer limit case instead of manual IR genPhilip Reames2019-07-031-10/+5
| | | | | | As noted in the test change, this is not trivially NFC, but all of the changes in output are cases where the SCEVExpander form is more canonical/optimal than the hand generation. llvm-svn: 365075
* [AMDGPU] Kernel arg metadata: added support for "__hip_texture" type.Konstantin Pyzhov2019-07-031-0/+10
| | | | | | | | | Summary: Hip texture type is equivalent to OpenCL image. So, we need to set the Image type for kernel arguments with __hip_texture type. Differential revision: https://reviews.llvm.org/D63850 llvm-svn: 365073
* [LFTR] Remove a stray variable shadow *of the same value* [NFC]Philip Reames2019-07-031-1/+0
| | | | llvm-svn: 365072
* [LFTR] Style and comment changes to clarify the narrow vs wide bitwidth ↵Philip Reames2019-07-031-17/+18
| | | | | | evaluation behavior [NFC] llvm-svn: 365071
* [LFTR] Sink the decision not use truncate scheme for constants into ↵Philip Reames2019-07-031-46/+43
| | | | | | | | genLoopLimit [NFC] We might as well just evaluate the constants using SCEV, and having the cases grouped makes the logic slightly easier to read anyway. llvm-svn: 365070
* Fix precedence in assert from r364961Jessica Paquette2019-07-031-1/+2
| | | | | | | | Precedence was wrong in an assert added in r364961. Add braces around the assertion condition to make it right. See: https://reviews.llvm.org/D64084 llvm-svn: 365069
* [LFTR] Remove falsely generalized (dead) code [NFC]Philip Reames2019-07-031-5/+2
| | | | llvm-svn: 365067
* [LFTR] Hoist extend expressions outside of loops w/o waiting for LICMPhilip Reames2019-07-031-1/+4
| | | | | | | | The motivation for this is two fold: 1) Make the output (and thus tests) a bit more readable to a human trying to understand the result of the transform 2) Reduce spurious diffs in a potential future change to restructure all of this logic to use SCEVExpander (which hoists by default) llvm-svn: 365066
* [GlobalISel][AArch64] Use getConstantVRegValWithLookThrough for selectArithImmedJessica Paquette2019-07-031-6/+4
| | | | | | | | | | | Instead of just stopping to see if we have a G_CONSTANT, instead, look through G_TRUNCs, G_SEXTs, and G_ZEXTs. This gives an average ~1.3% code size improvement on CINT2000 at -O3. Differential Revision: https://reviews.llvm.org/D64108 llvm-svn: 365063
* [X86] Avoid SFB - Skip meta instructionsRobert Lougher2019-07-031-4/+4
| | | | | | | | | | | This patch generalizes the fix in D61680 to ignore all meta instructions, not just debug info. Patch by Chris Dawson. Differential Revision: https://reviews.llvm.org/D62605 llvm-svn: 365061
* [CodeGen] Make branch funnels pass the machine verifierFrancis Visoiu Mistrih2019-07-032-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We previously marked all the tests with branch funnels as `-verify-machineinstrs=0`. This is an attempt to fix it. 1) `ICALL_BRANCH_FUNNEL` has no defs. Mark it as `let OutOperandList = (outs)` 2) After that we hit an assert: ``` Assertion failed: (Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && "Chain and glue operands should occur at end of operand list!"), function AddOperand, file /Users/francisvm/llvm/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp, line 461. ``` The chain operand was added at the beginning of the operand list. Move that to the end. 3) After that we hit another verifier issue in the pseudo expansion where the registers used in the cmps and jmps are not added to the livein lists. Add the `EFLAGS` to all the new MBBs that we create. PR39436 Differential Review: https://reviews.llvm.org/D54155 llvm-svn: 365058
* [X86] ComputeNumSignBitsForTargetNode - add target shuffle support.Simon Pilgrim2019-07-031-1/+50
| | | | llvm-svn: 365057
* Use getAllOnesConstants instead of -1 in DAGCombiner. NFCAmaury Sechet2019-07-031-1/+1
| | | | llvm-svn: 365054
* [SCEV] Preserve flags on add/muls in getSCEVATScopePhilip Reames2019-07-031-2/+2
| | | | | | | | We haven't changed the set of users, just specialized an operand for those users. Given that, the previous wrap flags must still be correct. Sorry for the lack of test case. Noticed this while working on something else, and haven't figured out to exercise this standalone. llvm-svn: 365053
* [DAGCombine] More diamong carry pattern optimization.Amaury Sechet2019-07-031-27/+92
| | | | | | | | | | | | | | | Summary: This diff improve the capability of DAGCOmbine to generate linear carries propagation in presence of a diamond pattern. It is now able to match a large variety of different patterns rather than some hardcoded one. Arguably, the codegen in test cases is not better, but this is to be expected. The goal of this transformation is more about canonicalisation than actual optimisation. Reviewers: hfinkel, RKSimon, craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D57302 llvm-svn: 365051
* [X86][AVX] combineX86ShufflesRecursively - peek through extract_subvectorSimon Pilgrim2019-07-031-20/+25
| | | | | | If we have more then 2 shuffle ops to combine, try to use combineX86ShuffleChainWithExtract to see if some are from the same super vector. llvm-svn: 365050
* [ARM] Fix for NDEBUG buildsSam Parker2019-07-031-4/+3
| | | | | | | | Fix unused variable warning as well as a nonsense assert. Differential Revision: https://reviews.llvm.org/D63816 llvm-svn: 365046
* [X86][AVX] Combine vpermi(bitcast(x)) -> bitcast(vpermi(x))Simon Pilgrim2019-07-031-0/+16
| | | | | | | | | | iff the number of elements doesn't change. This gets around an issue with combineX86ShuffleChain not being able to hint which domain is preferred for shuffles that can be done with either. Fixes regression introduced in rL365041 llvm-svn: 365044
* [SelectionDAG] Propagate alias metadata to target intrinsic nodesJames Molloy2019-07-032-6/+8
| | | | | | | | When a target intrinsic has been determined to touch memory, we construct a MachineMemOperand during SDAG construction. In this case, we should propagate AAMDNodes metadata to the MachineMemOperand where available. Differential revision: https://reviews.llvm.org/D64131 llvm-svn: 365043
* [X86][AVX] combineX86ShuffleChainWithExtract - add number of non-zero ↵Simon Pilgrim2019-07-031-0/+3
| | | | | | | | | | extract_subvectors to the combine depth This better accounts for the cost/benefit of removing extract_subvectors from the shuffle and will be more useful in future patches. The vpermq predicate regression will be fixed shortly. llvm-svn: 365041
* [ThinLTO] Optimize writeonly globals outEugene Leviant2019-07-039-143/+295
| | | | | | Differential revision: https://reviews.llvm.org/D63444 llvm-svn: 365040
* [mips] Mark general scheduling model as completeSimon Atanasyan2019-07-031-2/+2
| | | | llvm-svn: 365034
* [mips] Add missing atomic instructions to general scheduling definitionsSimon Atanasyan2019-07-031-0/+16
| | | | llvm-svn: 365033
* [mips] Add missing microMIPS instructions to general scheduling definitionsSimon Atanasyan2019-07-031-12/+25
| | | | llvm-svn: 365032
* [X86][SSE] lowerUINT_TO_FP_v2i32 - explicitly cast half word to doubleSimon Pilgrim2019-07-031-1/+1
| | | | | | Fixes MSVC analyzer extension->double warning. llvm-svn: 365027
* [X86][SSE] LowerINSERT_VECTOR_ELT - ensure insertion index correctness. NFCI.Simon Pilgrim2019-07-031-1/+2
| | | | | | Assert that the insertion index is in range and use uint64_t for the index to fix MSVC/cppcheck truncation warning. llvm-svn: 365025
* [X86][SSE] LowerScalarImmediateShift - ensure shift amount correctness. NFCI.Simon Pilgrim2019-07-031-2/+4
| | | | | | Assert that the shift amount is in range and create vXi8 shift masks in a way that doesn't cause MSVC/cppcheck shift result is truncated then extended warnings. llvm-svn: 365024
* [mips] Add SIGRIE,GINVI,GINVT to general scheduling definitionsSimon Atanasyan2019-07-031-2/+5
| | | | llvm-svn: 365023
* [mips] Add missing mips16 instructions to general scheduling definitionsSimon Atanasyan2019-07-032-5/+6
| | | | llvm-svn: 365022
* [mips] Add missing MSA and ASE instructions to general scheduling definitionsSimon Atanasyan2019-07-031-0/+33
| | | | llvm-svn: 365021
* [mips] Replace some itineraries by instructions in the general scheduling ↵Simon Atanasyan2019-07-031-187/+668
| | | | | | definitions llvm-svn: 365020
* Fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-07-031-1/+1
| | | | | | Both MSVC and cppcheck don't like the fact that the variables are initialized via references. llvm-svn: 365018
* [X86] LowerFunnelShift - use modulo constant shift amount.Simon Pilgrim2019-07-031-1/+1
| | | | | | This avoids the use of getZExtValue and uses the modulo shift amount which is whats expected for funnel shifts anyhow. llvm-svn: 365016
* [ARM] Thumb2: favor R4-R7 over R12/LR in allocation order when opt for minsizeOliver Stannard2019-07-034-7/+58
| | | | | | | | | | | | | | | | | | | | For Thumb2, we prefer low regs (costPerUse = 0) to allow narrow encoding. However, current allocation order is like: R0-R3, R12, LR, R4-R11 As a result, a lot of instructs that use R12/LR will be wide instrs. This patch changes the allocation order to: R0-R7, R12, LR, R8-R11 for thumb2 and -Osize. In most cases, there is no extra push/pop instrs as they will be folded into existing ones. There might be slight performance impact due to more stack usage, so we only enable it when opt for min size. https://reviews.llvm.org/D30324 llvm-svn: 365014
* Remove some autoconf references from docs and commentsSven van Haastregt2019-07-033-3/+3
| | | | | | | | | The autoconf build system support has been removed a while ago, remove some outdated references. Differential Revision: https://reviews.llvm.org/D63608 llvm-svn: 365013
* [InstCombine] Y - ~X --> X + Y + 1 fold (PR42457)Roman Lebedev2019-07-031-0/+6
| | | | | | | | | | | | | | | | | | | | | | Summary: I *think* we'd want this new variant, because we obviously have better handling for `add` as compared to `sub`/`not`. https://rise4fun.com/Alive/WMn Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=42457 | PR42457 ]] Reviewers: spatel, nikic, huihuiz, efriedma Reviewed By: spatel Subscribers: RKSimon, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63992 llvm-svn: 365011
* [Codegen][X86][AArch64][ARM][PowerPC] Inc-of-add vs sub-of-not (PR42457)Roman Lebedev2019-07-037-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the backend part of [[ https://bugs.llvm.org/show_bug.cgi?id=42457 | PR42457 ]]. In middle-end, we'd want to prefer the form with two adds - D63992, but as this diff shows, not every target will prefer that pattern. Out of 4 targets for which i added tests all seem to be ok with inc-of-add for scalars, but only X86 prefer that same pattern for vectors. Here i'm adding a new TLI hook, always defaulting to the inc-of-add, but adding AArch64,ARM,PowerPC overrides to prefer inc-of-add only for scalars. Reviewers: spatel, RKSimon, efriedma, t.p.northover, hfinkel Reviewed By: efriedma Subscribers: nemanjai, javed.absar, kristof.beyls, kbarton, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64090 llvm-svn: 365010
* [SCEV][LSR] Prevent using undefined value in binopsEugene Leviant2019-07-031-3/+1
| | | | | | | | | | | On some occasions ReuseOrCreateCast may convert previously expanded value to undefined. That value may be passed by SCEVExpander as an argument to InsertBinop making IV chain undefined. Differential revision: https://reviews.llvm.org/D63928 llvm-svn: 365009
* MSan: handle callbr instructionsAlexander Potapenko2019-07-031-21/+21
| | | | | | | | | | | | | | | | | | | | Summary: Handling callbr is very similar to handling an inline assembly call: MSan must checks the instruction's inputs. callbr doesn't (yet) have outputs, so there's nothing to unpoison, and conservative assembly handling doesn't apply either. Fixes PR42479. Reviewers: eugenis Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64072 llvm-svn: 365008
* [LoopPeel] Re-factor llvm::peelLoop method. NFC.Serguei Katkov2019-07-031-25/+49
| | | | | | | | | | | Extract code dealing with branch weights in separate functions. Reviewers: reames, mkuper, iajbar, fhahn Reviewed By: reames, fhahn Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D63917 llvm-svn: 365002
* Revert [InlineCost] cleanup calculations of Cost and ThresholdJordan Rupprecht2019-07-031-15/+13
| | | | | | | | This reverts r364422 (git commit 1a3dc761860d620ac8ed7e32a4285952142f780b) The inlining cost calculation is incorrect, leading to stack overflow due to large stack frames from heavy inlining. llvm-svn: 365000
* [AMDGPU] Enable serializing of argument info.Michael Liao2019-07-033-1/+253
| | | | | | | | | | | | | | | | Summary: - Support serialization of all arguments in machine function info. This enables fabricating MIR tests depending on argument info. Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64096 llvm-svn: 364995
* [AArch64][GlobalISel] Overhaul legalization & isel or shifts to select ↵Amara Emerson2019-07-036-20/+234
| | | | | | | | | | | | | | | | | | | | | | | | | immediate forms. There are two main issues preventing us from generating immediate form shifts: 1) We have partial SelectionDAG imported support for G_ASHR and G_LSHR shift immediate forms, but they currently don't work because the amount type is expected to be an s64 constant, but we only legalize them to have homogenous types. To deal with this, first we introduce a custom legalizer to *only* custom legalize s32 shifts which have a constant operand into a s64. There is also an additional artifact combiner to fold zexts(g_constant) to a larger G_CONSTANT if it's legal, a counterpart to the anyext version committed in an earlier patch. 2) For G_SHL the importer can't cope with the pattern. For this I introduced an early selection phase in the arm64 selector to select these forms manually before the tablegen selector pessimizes it to a register-register variant. Differential Revision: https://reviews.llvm.org/D63910 llvm-svn: 364994
* [PowerPC] exclude ICmpZero in LSR if icmp can be replaced in later hardware ↵Chen Zheng2019-07-034-7/+58
| | | | | | | | | loop. Differential Revision: https://reviews.llvm.org/D63477 llvm-svn: 364993
* [triple] Use 'macabi' environment name for the Mac Catalyst triplesAlex Lorenz2019-07-031-2/+2
| | | | | | The 'macabi' environment name is preferred instead of 'maccatalyst'. llvm-svn: 364988
* Revert Changing CodeView debug info type record representation in assembly ↵Nilanjana Basu2019-07-034-177/+32
| | | | | | | | files to make it more human-readable & editable This reverts r364982 (git commit 2082bf28ebea76cc187b508f801122866420d9ff) llvm-svn: 364987
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