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* Emit S_COMPILE3 record once per TU rather than once per functionAdrian McCarthy2016-11-021-2/+5
| | | | | | This has some ripple effects in several tests. llvm-svn: 285862
* Add the rest of the additional error checks for invalid Mach-O files whenKevin Enderby2016-11-021-19/+103
| | | | | | | | | | the offsets and sizes of an element of the Mach-O file overlaps with another element in the Mach-O file. Some other tests for malformed Mach-O files now run into these checks so their tests were also adjusted. llvm-svn: 285860
* DCE math library calls with a constant operand.Eli Friedman2016-11-022-0/+153
| | | | | | | | | | | On platforms which use -fmath-errno, math libcalls without any uses require some extra checks to figure out if they are actually dead. Fixes https://llvm.org/bugs/show_bug.cgi?id=30464 . Differential Revision: https://reviews.llvm.org/D25970 llvm-svn: 285857
* [Hexagon] Remove registers coalesced in expand-condsets from live intervalsKrzysztof Parzyszek2016-11-021-0/+3
| | | | llvm-svn: 285846
* [lli/COFF] Set the correct alignment for common symbolsDavide Italiano2016-11-021-0/+9
| | | | | | | | | | Otherwise we set it always to zero, which is not correct, and we assert inside alignTo (Assertion failed: Align != 0u && "Align can't be 0."). Differential Revision: https://reviews.llvm.org/D26173 llvm-svn: 285841
* Add CodeViewRecordIO for reading and writing.Zachary Turner2016-11-0210-452/+671
| | | | | | | | | | | | | | | Using a pattern similar to that of YamlIO, this allows us to have a single codepath for translating codeview records to and from serialized byte streams. The current patch only hooks this up to the reading of CodeView type records. A subsequent patch will hook it up for writing of CodeView type records, and then a third patch will hook up the reading and writing of CodeView symbols. Differential Revision: https://reviews.llvm.org/D26040 llvm-svn: 285836
* AMDGPU: Allow additional implicit operands on MOVRELS instructionsNicolai Haehnle2016-11-021-1/+4
| | | | | | | | | | | | | | | | | | | Summary: The post-RA scheduler occasionally uses additional implicit operands when the vector implicit operand as a whole is killed, but some subregisters are still live because they are directly referenced later. Unfortunately, this seems incredibly subtle to reproduce. Fixes piglit spec/glsl-110/execution/variable-indexing/vs-temp-array-mat2-index-wr.shader_test and others. Reviewers: arsenm, tstellarAMD Subscribers: kzhuravl, wdng, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25656 llvm-svn: 285835
* Fix Clang-tidy readability-redundant-string-cstr warningsMalcolm Parsons2016-11-027-8/+7
| | | | | | | | | | Reviewers: beanz, lattner, jlebar Subscribers: jholewinski, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D26235 llvm-svn: 285832
* [ARM][MC] Cleanup ARM Target Assembly ParserNirav Dave2016-11-021-540/+343
| | | | | | | | | | | | | | Summary: Correctly parse end-of-statement tokens and handle preprocessor end-of-line comments in ARM assembly processor. Reviewers: rnk, majnemer Subscribers: aemerson, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D26152 llvm-svn: 285830
* Improve and cleanup comments in DwarfExpression.hAdrian Prantl2016-11-021-15/+14
| | | | llvm-svn: 285829
* BranchRelaxation: Fix computing indirect branch block sizeMatt Arsenault2016-11-021-17/+17
| | | | llvm-svn: 285828
* Simplify control flow in the the DWARF expression compilerAdrian Prantl2016-11-024-69/+105
| | | | | | by refactoring common code into a DwarfExpressionCursor wrapper. llvm-svn: 285827
* Emit DW_OP_piece also if the previous value was a constant.Adrian Prantl2016-11-021-4/+6
| | | | | | This fixes a bug in the DWARF backend. llvm-svn: 285826
* Use !operator to test if APInt is zero/non-zero. NFCI.Simon Pilgrim2016-11-021-3/+3
| | | | | | Avoids APInt construction and slower comparisons. llvm-svn: 285822
* [mips] Always run the MipsOptimizePICCall pass.Vasileios Kalintiris2016-11-021-8/+1
| | | | | | | | | | | | | Summary: Remove this pass from addMachineSSAOptimization() and register it unconditionally in through addPreRegAlloc(). This pass is required for generating correct PIC calls. Reviewers: sdardis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26036 llvm-svn: 285814
* Create the virtual register for the global base in the intersection ofJoerg Sonnenberger2016-11-021-2/+2
| | | | | | | | GPRC and GPRC_NOR0 (or the 64bit equivalent) and not just the latter. GPRC_NOR0 contains ZERO as alternative meaning of r0 and is therefore not a true subclass of GPRC. llvm-svn: 285813
* Removing a switch statement that contains a default label, but no case ↵Aaron Ballman2016-11-021-5/+1
| | | | | | labels. Silences an MSVC warning; NFC. llvm-svn: 285806
* Simplify.Joerg Sonnenberger2016-11-021-2/+2
| | | | llvm-svn: 285802
* [SystemZ] Fix compiler warnings introduced by r285574Ulrich Weigand2016-11-021-3/+3
| | | | | | SystemZAsmParser::parseOperand returns a bool, not an enum. llvm-svn: 285800
* [llvm] FIx if-clause -Wmisleading-indentation issue.Kirill Bobyrev2016-11-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | While bootstrapping Clang with recent `gcc 6.2.0` I found a bug related to misleading indentation. I believe, a pair of `{}` was forgotten, especially given the above similar piece of code: ``` if (!RDef || !HII->isPredicable(*RDef)) { Done = coalesceRegisters(RD, RegisterRef(S1)); if (Done) { UpdRegs.insert(RD.Reg); UpdRegs.insert(S1.getReg()); } } ``` Reviewers: kparzysz Differential Revision: https://reviews.llvm.org/D26204 llvm-svn: 285794
* [Reassociate] Skip analysis of dead code to avoid infinite loop.Bjorn Pettersson2016-11-021-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | Summary: It was detected that the reassociate pass could enter an inifite loop when analysing dead code. Simply skipping to analyse basic blocks that are dead avoids such problems (and as a side effect we avoid spending time on optimising dead code). The solution is using the same Reverse Post Order ordering of the basic blocks when doing the optimisations, as when building the precalculated rank map. A nice side-effect of this solution is that we now know that we only try to do optimisations for blocks with ranked instructions. Fixes https://llvm.org/bugs/show_bug.cgi?id=30818 Reviewers: llvm-commits, davide, eli.friedman, mehdi_amini Subscribers: dberlin Differential Revision: https://reviews.llvm.org/D26154 llvm-svn: 285793
* [AVR] Add instruction selection lowering codeDylan McKay2016-11-022-0/+1938
| | | | | | | | | | | | Summary: This adds AVRISelLowering.cpp Reviewers: arsenm, kparzysz Subscribers: llvm-commits, modocache, japaric, wdng, beanz, mgorny Differential Revision: https://reviews.llvm.org/D25034 llvm-svn: 285790
* Bitcode: Check file size before reading bitcode header.Peter Collingbourne2016-11-021-1/+2
| | | | | | | | Should unbreak ocaml binding tests. Also added an llvm-dis test that checks for the same thing. llvm-svn: 285777
* Support: Remove MemoryObject and DataStreamer interfaces.Peter Collingbourne2016-11-028-245/+0
| | | | | | | | These interfaces are no longer used. Differential Revision: https://reviews.llvm.org/D26222 llvm-svn: 285774
* Bitcode: Change reader interface to take memory buffers.Peter Collingbourne2016-11-021-83/+21
| | | | | | | | | | | | | | | | | | | As proposed on llvm-dev: http://lists.llvm.org/pipermail/llvm-dev/2016-October/106595.html This change also fixes an API oddity where BitstreamCursor::Read() would return zero for the first read past the end of the bitstream, but would report_fatal_error for subsequent reads. Now we always report_fatal_error for all reads past the end. Updated clients to check for the end of the bitstream before reading from it. I also needed to add padding to the invalid bitcode tests in test/Bitcode/. This is because the streaming interface was not checking that the file size is a multiple of 4. Differential Revision: https://reviews.llvm.org/D26219 llvm-svn: 285773
* [RISCV] Add bare-bones RISC-V MCTargetDescAlex Bradbury2016-11-0113-9/+441
| | | | | | | | | | This is enough to compile and link but doesn't yet do anything particularly useful. Once an ASM parser and printer are added in the next two patches, the whole thing can be usefully tested. Differential Revision: https://reviews.llvm.org/D23562 llvm-svn: 285770
* [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.tdAlex Bradbury2016-11-015-0/+331
| | | | | | | | | | For now, only add instruction definitions for basic ALU operations. Our initial target is a working MC layer rather than codegen, so appropriate SelectionDAG patterns will come later. Differential Revision: https://reviews.llvm.org/D23561 llvm-svn: 285769
* AMDGPU: Handle CopyToReg in getOperandRegClassMatt Arsenault2016-11-011-1/+14
| | | | llvm-svn: 285768
* AMDGPU: Use brev for materializing SGPR constantsMatt Arsenault2016-11-011-11/+29
| | | | | | This is already done with VGPR immediates and saves 4 bytes. llvm-svn: 285765
* AMDGPU: Default to using scalar mov to materialize immediateMatt Arsenault2016-11-013-11/+39
| | | | | | | | | | | | This is the conservatively correct way because it's easy to move or replace a scalar immediate. This was incorrect in the case when the register class wasn't known from the static instruction definition, but still needed to be an SGPR. The main example of this is inlineasm has an SGPR constraint. Also start verifying the register classes of inlineasm operands. llvm-svn: 285762
* Move the initialization of PreferredLoopExit into runOnMachineFunction to be ↵Eric Christopher2016-11-011-1/+5
| | | | | | near the other function specific initializations. llvm-svn: 285758
* Fix uninitialized access in MachineBlockPlacement.Sam McCall2016-11-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Summary: Currently PreferredLoopExit is set only in buildLoopChains, which is never called if there are no MachineLoops. MSan is currently broken by this: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/145/steps/check-llvm%20msan/logs/stdio This is a naive fix to get things green again. iteratee: you may have a better fix. This change will also mean PreferredLoopExit will not carry over if buildCFGChains() is called a second time in runOnMachineFunction, this appears to be the right thing. Reviewers: bkramer, iteratee, echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26069 llvm-svn: 285757
* AMDGPU: Stop creating unused virtual registersMatt Arsenault2016-11-011-2/+5
| | | | | | | These are only used in the spill to VMEM path. Move them to the one use. llvm-svn: 285756
* [MemorySSA] Tighten up types to make our API prettier. NFC.George Burgess IV2016-11-012-17/+15
| | | | | | | | Patch by bryant. Differential Revision: https://reviews.llvm.org/D26126 llvm-svn: 285750
* [ValueTracking] remove TODO comment; NFCSanjay Patel2016-11-011-2/+0
| | | | | | | | | | InstCombine should always canonicalize patterns like the one shown in the comment when visiting 'select' insts in adjustMinMax(). Scalars were already handled there, and vector splats are handled after: https://reviews.llvm.org/rL285732 llvm-svn: 285744
* AMDGPU: Workaround for instruction size with literalsMatt Arsenault2016-11-015-2/+28
| | | | | | | | | | Instructions with a 32-bit base encoding with an optional 32-bit literal encoded after them report their size as 4 for the disassembler. Consider these when computing the MachineInstr size. This fixes problems caused by size estimate consistency in BranchRelaxation. llvm-svn: 285743
* [InstCombine] allow splat vector folds in adjustMinMax()Sanjay Patel2016-11-011-14/+10
| | | | llvm-svn: 285732
* [InstCombine] Fold nuw left-shifts in `ugt`/`ule` comparisons.Sanjay Patel2016-11-011-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This transforms %a = shl nuw %x, c1 %b = icmp {ugt|ule} %a, c0 into %b = icmp {ugt|ule} %x, (c0 >> c1) z3: (declare-const x (_ BitVec 64)) (declare-const c0 (_ BitVec 64)) (declare-const c1 (_ BitVec 64)) (push) (assert (= x (bvlshr (bvshl x c1) c1))) ; nuw (assert (not (= (bvugt (bvshl x c1) c0) (bvugt x (bvlshr c0 c1))))) (check-sat) (get-model) (pop) (push) (assert (= x (bvlshr (bvshl x c1) c1))) ; nuw (assert (not (= (bvule (bvshl x c1) c0) (bvule x (bvlshr c0 c1))))) (check-sat) (get-model) (pop) Patch by bryant! Differential Revision: https://reviews.llvm.org/D25913 llvm-svn: 285729
* [Hexagon] Rename operand/predicate names for unshifted integersKrzysztof Parzyszek2016-11-0113-605/+567
| | | | | | | | For example, rename s6Ext to s6_0Ext. The names for shifted integers include the underscore and this will make the naming consistent. It also exposed a few duplicates that were removed. llvm-svn: 285728
* BranchRelaxation: Expand unconditional branches firstMatt Arsenault2016-11-011-15/+22
| | | | | | | | | | | | | It's likely if a conditional branch needs to be expanded, the following unconditional branch will also need expansion. By expanding the unconditional branch first, the conditional branch can be simply inverted to jump over the inserted indirect branch block. If the conditional branch is expanded first, it results in an additional branch. This avoids test regressions in future commits. llvm-svn: 285722
* [InstCombine] clean up adjustMinMax(); NFCISanjay Patel2016-11-011-92/+87
| | | | | | | | | 1. Change param names for readability 2. Change pointer param to ref 3. Early exit to reduce indent 4. Change switch to if/else llvm-svn: 285718
* [AMDGPU] Check if type transforms to i16 (VI+) when getting AMDGPUISD::FFBH_U32Konstantin Zhuravlyov2016-11-013-17/+22
| | | | | | | | | | | This will prevent following regression when enabling i16 support (D18049): test/CodeGen/AMDGPU/ctlz.ll test/CodeGen/AMDGPU/ctlz_zero_undef.ll Differential Revision: https://reviews.llvm.org/D25802 llvm-svn: 285716
* [InstCombine] add helper function for adjustMinMax(); NFCISanjay Patel2016-11-011-6/+19
| | | | | | This is just a cut and paste; clean-up and enhancements to follow. llvm-svn: 285715
* [RISCV] Add stub backendAlex Bradbury2016-11-018-0/+197
| | | | | | | | | | | | | | This contains just enough for lib/Target/RISCV to compile. Notably a basic RISCVTargetMachine and RISCVTargetInfo. At this point you can attempt llc -march=riscv32 myinput.ll and will find it fails due to the lack of MCAsmInfo. See http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html for further discussion Differential Revision: https://reviews.llvm.org/D23560 llvm-svn: 285712
* AMDGPU: Fix buildbots broken by r285704Tom Stellard2016-11-011-2/+1
| | | | llvm-svn: 285711
* [RISCV] Add RISC-V ELF definesAlex Bradbury2016-11-012-0/+11
| | | | | | | | | | Add the necessary definitions for RISC-V ELF files, including relocs. Also make necessary trivial change to ELFYaml, llvm-objdump, and llvm-readobj in order to work with RISC-V ELFs. Differential Revision: https://reviews.llvm.org/D23557 llvm-svn: 285708
* [RISCV] Recognise riscv32 and riscv64 in triple parsing codeAlex Bradbury2016-11-011-0/+21
| | | | | | | | | | | This is the first in a series of 10 initial patches that incrementally add an MC layer for RISC-V to LLVM. See <http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html> for more discussion. Differential Revision: https://reviews.llvm.org/D23557 llvm-svn: 285707
* [TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.hAlex Bradbury2016-11-018-76/+76
| | | | | | | | | | | | | | | As it stands, the OperandMatchResultTy is only included in the generated header if there is custom operand parsing. However, almost all backends make use of MatchOperand_Success and friends from OperandMatchResultTy for e.g. parseRegister. This is a pain when starting an AsmParser for a new backend that doesn't yet have custom operand parsing. Move the enum to MCTargetAsmParser.h. This patch is a prerequisite for D23563 Differential Revision: https://reviews.llvm.org/D23496 llvm-svn: 285705
* AMDGPU: Implement expansion of f16 = FP_TO_FP16 f64Tom Stellard2016-11-012-0/+99
| | | | | | | | | | | | | | | | | | | | | | I wanted to implement this as a target independent expansion, however when targets say they want to expand FP_TO_FP16 what they actually want is the unsafe math expansion when possible and expansion to a libcall in all other cases. The only way to make this work as a target independent would be to add logic to target's TargetLowering construction to mark theses nodes as Expand when LegalizeDAG can use the unsafe expansion and mark them as LibCall when it cannot. I think this would be possible, but I think it would be too fragile and complex as it would require targets to keep their expansion logic up to date with the code in LegalizeDAG. Reviewers: bogner, ab, t.p.northover, arsenm Subscribers: wdng, llvm-commits, nhaehnle Differential Revision: https://reviews.llvm.org/D25999 llvm-svn: 285704
* [InstCombine] Folding of shifts by the sum of positive valuesSimon Pilgrim2016-11-011-1/+10
| | | | | | | | | | | | | | | This patch introduces the combine: (C1 shift (A add C2)) -> ((C1 shift C2) shift A) iff A and C2 are both positive If both A and C2 are know to be positive then we can safely split into 2 shifts, permitting the folding of the Inner shift. Fix for the spec benchmark case mentioned by @nadav on PR15141 (assuming we can prove that the inputs as positive). Differential Revision: https://reviews.llvm.org/D26000 llvm-svn: 285696
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