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* NVPTX: Refactor NVPTXInferAddressSpaces to check TTIMatt Arsenault2017-01-303-33/+61
| | | | | | Add a new TTI hook for getting the generic address space value. llvm-svn: 293563
* [InstCombine] enable more lshr(shl X, C1), C2 folds for vectors with splat ↵Sanjay Patel2017-01-301-23/+17
| | | | | | constants llvm-svn: 293562
* [X86][SSE] Fix unsigned <= 0 warning in assert. NFCI.Simon Pilgrim2017-01-301-2/+2
| | | | | | Thanks to @mkuper llvm-svn: 293561
* [X86][SSE] Generalize the number of decoded shuffle inputs. NFCI.Simon Pilgrim2017-01-301-22/+8
| | | | | | | | combineX86ShufflesRecursively can still only handle a maximum of 2 shuffle inputs but everything before it now supports any number of shuffle inputs. This will be necessary for combining OR(SHUFFLE, SHUFFLE) patterns. llvm-svn: 293560
* Expose isLegalToPromot as a global helper function so that SamplePGO pass ↵Dehao Chen2017-01-301-46/+36
| | | | | | | | | | | | | | | | can call it for legality check. Summary: SamplePGO needs to check if it is legal to promote a target before it actually promotes it. Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29306 llvm-svn: 293559
* Revert r292979 which causes compile time failure.Dehao Chen2017-01-301-19/+5
| | | | llvm-svn: 293557
* Fix line endings.Eli Friedman2017-01-303-1293/+1293
| | | | llvm-svn: 293554
* AMDGPU: Fix release build broken by r293551Tom Stellard2017-01-302-1/+2
| | | | llvm-svn: 293553
* Re-commit AMDGPU/GlobalISel: Add support for simple shadersTom Stellard2017-01-3016-10/+1142
| | | | | | | | | | | | | | Fix build when global-isel is disabled and fix a warning. Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP. Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris Differential Revision: https://reviews.llvm.org/D26730 llvm-svn: 293551
* GlobalISel: correctly translate invoke when callee is a register.Tim Northover2017-01-301-1/+5
| | | | | | This should fix the GlobalISel verifier. llvm-svn: 293550
* [AMDGPU] Internalize non-kernel symbolsStanislav Mekhanoshin2017-01-301-2/+33
| | | | | | | | | | | | | Since we have no call support and late linking we can produce code only for used symbols. This saves compilation time, size of the final executable, and size of any intermediate dumps. Run Internalize pass early in the opt pipeline followed by global DCE pass. To enable it RT can pass -amdgpu-internalize-symbols option. Differential Revision: https://reviews.llvm.org/D29214 llvm-svn: 293549
* GlobalISel: account for differing exception selector sizes.Tim Northover2017-01-301-1/+10
| | | | | | | | | For some reason the exception selector register must be a pointer (that's assumed by SDag); on the other hand, it gets moved into an IR-level type which might be entirely different (i32 on AArch64). IRTranslator needs to be aware of this. llvm-svn: 293546
* GlobalISel: tidy up def/use test. NFC.Tim Northover2017-01-301-2/+2
| | | | llvm-svn: 293545
* LSR: Don't drop address space when type doesn't matchMatt Arsenault2017-01-301-4/+7
| | | | | | | | | | For targets with different addressing modes in each address space, if this is dropped querying isLegalAddressingMode later with this will give a nonsense result, breaking the isLegalUse assertions. This is a candidate for the 4.0 release branch. llvm-svn: 293542
* GlobalISel: translate memset & memmove.Tim Northover2017-01-301-9/+25
| | | | llvm-svn: 293541
* AMDGPU: Undo sub x, c -> add x, -c canonicalizationMatt Arsenault2017-01-303-0/+30
| | | | | | | | | This is worse if the original constant is an inline immediate. This should also be done for 64-bit adds, but requires fixing operand folding bugs first. llvm-svn: 293540
* [RDF] Add support for regmasksKrzysztof Parzyszek2017-01-304-79/+272
| | | | llvm-svn: 293538
* GlobalISel: permit unused vregs without a register-class after ISel.Tim Northover2017-01-301-5/+9
| | | | | | | This can happen if earlier combining has removed all uses of some VReg, which is fine and shouldn't flag an error. llvm-svn: 293537
* Fix the GCC build.Benjamin Kramer2017-01-301-28/+40
| | | | | | This is fairly ugly, but apparently GCC still doesn't understand C++11. llvm-svn: 293535
* Use SelectionDAG::getBuildVector helper function where possible. NFCI.Simon Pilgrim2017-01-302-21/+19
| | | | llvm-svn: 293532
* [MC] Remove global constructors from MCSectionMachO.cpp.Benjamin Kramer2017-01-301-12/+12
| | | | llvm-svn: 293526
* AMDGPU: Run AMDGPUCodeGenPrepare after inliningMatt Arsenault2017-01-301-9/+9
| | | | | | | With leaf functions, this makes nonsensical decisions based on the uniformity of the arguments. llvm-svn: 293525
* [InstCombine] enable (X >>?exact C1) << C2 --> X >>?exact (C1-C2) for ↵Sanjay Patel2017-01-301-24/+22
| | | | | | vectors with splat constants llvm-svn: 293524
* SDAG: Update ChainNodesMatched during UpdateChains if a node is replacedJustin Bogner2017-01-301-1/+11
| | | | | | | | | | | Previously, we would hit UB (or the ISD::DELETED_NODE assert) if we happened to replace a node during UpdateChains, because it would be left in the list we were iterating over. This nulls out the pointer when that happens so that we can avoid the issue. Fixes llvm.org/PR31710 llvm-svn: 293522
* Use SelectionDAG::getBuildVector/getSplatBuildVector helper functions where ↵Simon Pilgrim2017-01-301-7/+3
| | | | | | possible. NFCI. llvm-svn: 293520
* [libFuzzer] Implement TmpDir() for Windows.Marcos Pividori2017-01-301-1/+11
| | | | | | Differential Revision: https://reviews.llvm.org/D28977 llvm-svn: 293516
* NewGVN: Instead of changeToUnreachable, insert an instruction SimplifyCFG ↵Daniel Berlin2017-01-301-4/+5
| | | | | | will turn into unreachable when it runs llvm-svn: 293515
* AMDGPU: Make i32 uaddo/usubo legalMatt Arsenault2017-01-302-0/+20
| | | | llvm-svn: 293514
* DAG: Fold fneg into compare with constant into the constantMatt Arsenault2017-01-301-0/+10
| | | | | | | | fcmp (fneg x), c, pred -> fcmp x, -c, (swap pred) InstCombine already does this. llvm-svn: 293512
* [RDF] Extract the physical register information into a separate classKrzysztof Parzyszek2017-01-307-254/+344
| | | | llvm-svn: 293510
* Revert "AMDGPU/GlobalISel: Add support for simple shaders"Tom Stellard2017-01-3016-1140/+10
| | | | | | | | This reverts commit r293503. Revert while I investigate some of the buildbot failures. llvm-svn: 293509
* [InstCombine] use auto with obvious type; NFCSanjay Patel2017-01-301-3/+3
| | | | llvm-svn: 293508
* [InstCombine] enable (X <<nsw C1) >>s C2 --> X <<nsw (C1-C2) for vectors ↵Sanjay Patel2017-01-301-20/+16
| | | | | | with splat constants llvm-svn: 293507
* unique_ptrify some containers in GlobalISel::RegisterBankInfoDavid Blaikie2017-01-301-19/+9
| | | | | | | | | To simplify/clarify memory ownership, make leaks (as one was found/fixed recently) harder to write, etc. (also, while I was there - removed a duplicate lookup in a container) llvm-svn: 293506
* AMDGPU: Fix atomic_inc/atomic_dec + ds_swizzle not being divergentMatt Arsenault2017-01-301-0/+3
| | | | llvm-svn: 293504
* AMDGPU/GlobalISel: Add support for simple shadersTom Stellard2017-01-3016-10/+1140
| | | | | | | | | | | | Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP. Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris Differential Revision: https://reviews.llvm.org/D26730 llvm-svn: 293503
* Revert "NewGVN: Make unreachable blocks be marked with unreachable"Daniel Berlin2017-01-301-13/+18
| | | | | | | | | This reverts commit r293196 Besides making things look nicer, ATM, we'd like to preserve analysis more than we'd like to destroy the CFG. We'll probably revisit in the future llvm-svn: 293501
* [X86][SSE] Add support for combining PINSRW+ASSERTZEXT+PEXTRW patterns with ↵Simon Pilgrim2017-01-301-0/+20
| | | | | | target shuffles llvm-svn: 293500
* DAG: Constant fold fp16_to_fp/fp16_to_fpMatt Arsenault2017-01-301-0/+19
| | | | | | | This fixes emitting conversions of constants on targets without legal f16 that need to use these for legalization. llvm-svn: 293499
* [InstCombine] fixed to propagate 'exact' on lshrSanjay Patel2017-01-301-1/+1
| | | | | | | | | | | | | | | | | The original shift is bigger, so this may qualify as 'obvious', but here's an attempt at an Alive-based proof: Name: exact Pre: (C1 u< C2) %a = shl i8 %x, C1 %b = lshr exact i8 %a, C2 => %c = lshr exact i8 %x, C2 - C1 %b = and i8 %c, ((1 << width(C1)) - 1) u>> C2 Optimization is correct! llvm-svn: 293498
* [Coroutines] Add header guard to header that's missing one.Benjamin Kramer2017-01-301-0/+5
| | | | llvm-svn: 293494
* [Inliner] Fold analysis remarks into missed remarksAdam Nemet2017-01-301-15/+12
| | | | | | This significantly reduces the noise level of these messages. llvm-svn: 293492
* [RDF] Add phis for entry block live-ins (in addition to function live-ins)Krzysztof Parzyszek2017-01-303-14/+22
| | | | llvm-svn: 293491
* [Inliner] Fix a comment to match the code. NFC.Haicheng Wu2017-01-301-2/+2
| | | | | | | | TotalAltCost => TotalSecondaryCost Differential Revision: https://reviews.llvm.org/D29231 llvm-svn: 293490
* [InstCombine] enable lshr(shl X, C1), C2 folds for vectors with splat constantsSanjay Patel2017-01-301-25/+25
| | | | llvm-svn: 293489
* Only print architecture dependent flags for that architecture.Rafael Espindola2017-01-305-11/+18
| | | | | | | | | | Different architectures can have different meaning for flags in the SHF_MASKPROC mask, so we should always check what the architecture use before checking the flag. NFC for now, but will allow fixing the value of an xmos flag. llvm-svn: 293484
* [Hexagon] Make header self-contained.Benjamin Kramer2017-01-301-0/+3
| | | | llvm-svn: 293482
* [X86][MCU] Minor bug fix for r293469 + test caseAsaf Badouh2017-01-301-1/+1
| | | | llvm-svn: 293478
* AMDGPU: Remove a useless VI SMRD patternMarek Olsak2017-01-302-10/+0
| | | | | | | | | | | | Summary: already covered by complex patterns Reviewers: arsenm, nhaehnle, tstellarAMD Subscribers: kzhuravl, wdng, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D28995 llvm-svn: 293477
* AMDGPU: Fix assembler encoding for EXP instructions on VIMarek Olsak2017-01-301-0/+2
| | | | | | | | | | Reviewers: arsenm, tstellarAMD Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D28992 llvm-svn: 293476
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