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* Generalize statepoint lowering to use ImmutableStatepoint. Move statepoint ↵Igor Laevsky2015-02-202-40/+41
| | | | | | | | lowering into a separate function 'LowerStatepoint' which uses ImmutableStatepoint instead of a CallInst. Also related utility functions are changed to receive ImmutableCallSite. Differential Revision: http://reviews.llvm.org/D7756 llvm-svn: 230017
* Constants.cpp: Only read 32 bits for float.Benjamin Kramer2015-02-201-3/+6
| | | | | | Otherwise we'll discard the wrong half of a uint64_t on big-endian systems. llvm-svn: 230016
* Constants.cpp: getElementAsAPFloat(): Don't handle constant value via host's ↵NAKAMURA Takumi2015-02-201-8/+5
| | | | | | | | float/double, just handle with APInt/APFloat. x87 FPU didn't keep SNAN, but demoted to QNAN. llvm-svn: 230013
* RewriteStatepointsForGC: Move details into anonymous namespaces. NFC.Benjamin Kramer2015-02-201-10/+12
| | | | | | While there reduce the number of duplicated std::map lookups. llvm-svn: 230012
* Wrap recursive function only used in assert in #ifndef NDEBUG.Benjamin Kramer2015-02-201-1/+5
| | | | | | Avoids unused function warnings in Release builds. llvm-svn: 230009
* [x86] Switching the shuffle equivalence test to a variadic template wasChandler Carruth2015-02-201-115/+108
| | | | | | | | the wrong answer. We also got initializer lists which are *way* cleaner for this kind of thing. Let's use those and make this a normal, boring functionn accepting ArrayRef. llvm-svn: 230004
* Fix wording and grammar in Mips subtarget options.Eric Christopher2015-02-201-23/+18
| | | | llvm-svn: 230001
* Get the cached subtarget off the MachineFunction rather thanEric Christopher2015-02-202-6/+5
| | | | | | inquiring for a new one from the TargetMachine. llvm-svn: 230000
* Get the cached subtarget off the MachineFunction rather thanEric Christopher2015-02-208-16/+17
| | | | | | inquiring for a new one from the TargetMachine. llvm-svn: 229999
* Get the cached subtarget off the MachineFunction rather thanEric Christopher2015-02-201-4/+4
| | | | | | inquiring for a new one from the TargetMachine. llvm-svn: 229998
* Save the MachineFunction in startFunction so that we can use it forEric Christopher2015-02-202-4/+6
| | | | | | lookups of the subtarget later. llvm-svn: 229996
* Use the cached subtarget from the MachineFunction rather thanEric Christopher2015-02-202-6/+4
| | | | | | doing a lookup on the TargetMachine. llvm-svn: 229995
* Make the TargetMachine::getSubtarget that takes a Function argumentEric Christopher2015-02-202-2/+2
| | | | | | | take a reference to match the getSubtargetImpl that takes a Function argument. llvm-svn: 229994
* Disallow implicit conversions from None to integer typesJustin Bogner2015-02-201-2/+6
| | | | | | | | | | | | This fixes an error introduced in r228934 where None was converted to an int instead of the int being converted to an Optional as intended. We make that sort of mistake a compile error by changing NoneType into a scoped enum. Finally, provide a static NoneType called None to avoid forcing all users to spell it NoneType::None. llvm-svn: 229980
* Fix build with gcc. This has a -Wsequence-point error on 'MII', which is a ↵Nick Lewycky2015-02-201-5/+3
| | | | | | good point. llvm-svn: 229979
* Remove more uses of TargetMachine::getSubtargetImpl from theEric Christopher2015-02-201-9/+8
| | | | | | | | | | AsmPrinter. getSubtargetInfo now asserts that the MachineFunction exists. Debug printing of register naming now uses the register info from MCAsmInfo as that's unchanging. llvm-svn: 229978
* Fix build in release mode, -Wunused-variable on this lambda function used ↵Nick Lewycky2015-02-201-0/+1
| | | | | | only in an assert. llvm-svn: 229977
* Fix build in release mode, four cases of -Wunused-variable.Nick Lewycky2015-02-201-0/+5
| | | | llvm-svn: 229976
* AsmPrinter::doFinalization is at the module level and so doesn'tEric Christopher2015-02-201-2/+7
| | | | | | | have access to a target specific subtarget info. Grab the module level MCSubtargetInfo for the JumpInstrTable output stubs. llvm-svn: 229974
* Remove the MCInstrInfo cached variable as it was only used in aEric Christopher2015-02-202-15/+13
| | | | | | | single place and replace calls to getSubtargetImpl with calls to get the subtarget from the MachineFunction where valid. llvm-svn: 229971
* Fix -Wunused-variable warning in non-asserts build, and optimize a little ↵David Blaikie2015-02-201-3/+3
| | | | | | bit while I'm here. llvm-svn: 229970
* [PowerPC] Loop Data Prefetching for the BG/QHal Finkel2015-02-204-0/+248
| | | | | | | | | | | | | | | | | | | | | The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it prefetches into its own L1P buffer, and the latency to access that buffer is significantly higher than that to the L1 cache (although smaller than the latency to the L2 cache). As a result, especially when multiple hardware threads are not actively busy, explicitly prefetching data into the L1 cache is advantageous. I've been using this pass out-of-tree for data prefetching on the BG/Q for well over a year, and it has worked quite well. It is enabled by default only for the BG/Q, but can be enabled for other cores as well via a command-line option. Eventually, we might want to add some TTI interfaces and move this into Transforms/Scalar (there is nothing particularly target dependent about it, although only machines like the BG/Q will benefit from its simplistic strategy). llvm-svn: 229966
* [x86] Remove the old vector shuffle lowering code and its flag.Chandler Carruth2015-02-201-2940/+22
| | | | | | | | | | | | | | | | | The new shuffle lowering has been the default for some time. I've enabled the new legality testing by default with no really blocking regressions. I've fuzz tested this very heavily (many millions of fuzz test cases have passed at this point). And this cleans up a ton of code. =] Thanks again to the many folks that helped with this transition. There was a lot of work by others that went into the new shuffle lowering to make it really excellent. In case you aren't using a diff algorithm that can handle this: X86ISelLowering.cpp: 22 insertions(+), 2940 deletions(-) llvm-svn: 229964
* [x86] Now that the new vector shuffle legality is enabled and everythingChandler Carruth2015-02-201-77/+5
| | | | | | | | | is going well, remove the flag and the code for the old legality tests. This is the first step toward removing the entire old vector shuffle lowering. *Much* more code to delete coming up next. llvm-svn: 229963
* Bitcode: Stop assuming non-null fieldsDuncan P. N. Exon Smith2015-02-203-16/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When writing the bitcode serialization for the new debug info hierarchy, I assumed two fields would never be null. Drop that assumption, since it's brittle (and crashes the `BitcodeWriter` if wrong), and is a check better left for the verifier anyway. (No need for a bitcode upgrade here, since the new hierarchy is still not in place.) The fields in question are `MDCompileUnit::getFile()` and `MDDerivedType::getBaseType()`, the latter of which isn't null in test/Transforms/Mem2Reg/ConvertDebugInfo2.ll (see !14, a pointer to nothing). While the testcase might have bitrotted, there's no reason for the bitcode format to rely on non-null for metadata operands. This also fixes a bug in `AsmWriter` where if the `file:` is null it isn't emitted (caught by the double-round trip in the testcase I'm adding) -- this is a required field in `LLParser`. I'll circle back to ConvertDebugInfo2. Once the specialized nodes are in place, I'll be trying to turn the debug info verifier back on by default (in the newer module pass form committed r206300) and throwing more logic in there. If the testcase has bitrotted (as opposed to me not understanding the schema correctly) I'll fix it then. llvm-svn: 229960
* [InstCombine] Remove unnecessary variable indexing into single-element arraysHal Finkel2015-02-201-0/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change addresses a deficiency pointed out in PR22629. To copy from the bug report: [from the bug report] Consider this code: int f(int x) { int a[] = {12}; return a[x]; } GCC knows to optimize this to movl $12, %eax ret The code generated by recent Clang at -O3 is: movslq %edi, %rax movl .L_ZZ1fiE1a(,%rax,4), %eax retq .L_ZZ1fiE1a: .long 12 # 0xc [end from the bug report] This definitely seems worth fixing. I've also seen this kind of code before (as the base case of generic vector wrapper templates with one element). The general idea is to look at the GEP feeding a load or a store, which has some variable as its first non-zero index, and determine if that index must be zero (or else an out-of-bounds access would occur). We can do this for allocas and globals with constant initializers where we know the maximum size of the underlying object. When we find such a GEP, we create a new one for the memory access with that first variable index replaced with a constant zero. Even if we can't eliminate the memory access (and sometimes we can't), it is still useful because it removes unnecessary indexing calculations. llvm-svn: 229959
* [x86] Make the new vector shuffle legality test on by default, whichChandler Carruth2015-02-201-1/+1
| | | | | | | | | | reflects the fact that the x86 backend can in fact lower any shuffle you want it to with reasonably high code quality. My recent work on the new vector shuffle has made this regress *very* little. The diff in the test cases makes me very, very happy. llvm-svn: 229958
* [fuzzer] one more experimental search mode: -use_coverage_pairs=1 Kostya Serebryany2015-02-207-2/+55
| | | | llvm-svn: 229957
* Adjust enablement of RewriteStatepointsForGCPhilip Reames2015-02-201-1/+2
| | | | | | | | When back merging the changes in 229945 I noticed that I forgot to mark the test cases with the appropriate GC. We want the rewriting to be off by default (even when manually added to the pass order), not on-by default. To keep the current test working, mark them as using the statepoint-example GC and whitelist that GC. Longer term, we need a better selection mechanism here for both actual usage and testing. As I migrate more tests to the in tree version of this pass, I will probably need to update the enable/disable logic as well. llvm-svn: 229954
* Revert r229944: EH: Prune unreachable resume instructions during Dwarf EH ↵Chandler Carruth2015-02-203-111/+22
| | | | | | | | | preparation This doesn't pass 'ninja check-llvm' for me. Lots of tests, including the ones updated, fail with crashes and other explosions. llvm-svn: 229952
* Add a pass for constructing gc.statepoint sequences w/explicit relocationsPhilip Reames2015-02-203-0/+1933
| | | | | | | | | | | | | This patch consists of a single pass whose only purpose is to visit previous inserted gc.statepoints which do not have gc.relocates inserted yet, and insert them. This can be used either immediately after IR generation to perform 'early safepoint insertion' or late in the pass order to perform 'late insertion'. This patch is setting the stage for work to continue in tree. In particular, there are known naming and style violations in the current patch. I'll try to get those resolved over the next week or so. As I touch each area to make style changes, I need to make sure we have adequate testing in place. As part of the cleanup, I will be cleaning up a collection of test cases we have out of tree and submitting them upstream. The tests included in this change are very basic and mostly to provide examples of usage. The pass has several main subproblems it needs to address: - First, it has identify any live pointers. In the current code, the use of address spaces to distinguish pointers to GC managed objects is hard coded, but this will become parametrizable in the near future. Note that the current change doesn't actually contain a useful liveness analysis. It was seperated into a followup change as the code wasn't ready to be shared. Instead, the current implementation just considers any dominating def of appropriate pointer type to be live. - Second, it has to identify base pointers for each live pointer. This is a fairly straight forward data flow algorithm. - Third, the information in the previous steps is used to actually introduce rewrites. Rather than trying to do this by hand, we simply re-purpose the code behind Mem2Reg to do this for us. llvm-svn: 229945
* EH: Prune unreachable resume instructions during Dwarf EH preparationReid Kleckner2015-02-203-22/+111
| | | | | | | | | | | | | | | | | Today a simple function that only catches exceptions and doesn't run destructor cleanups ends up containing a dead call to _Unwind_Resume (PR20300). We can't remove these dead resume instructions during normal optimization because inlining might introduce additional landingpads that do have cleanups to run. Instead we can do this during EH preparation, which is guaranteed to run after inlining. Fixes PR20300. Reviewers: majnemer Differential Revision: http://reviews.llvm.org/D7744 llvm-svn: 229944
* Revert "AVX-512: Full implementation for VRNDSCALESS/SD instructions and ↵Eric Christopher2015-02-205-85/+48
| | | | | | | | | | intrinsics." The instructions were being generated on architectures that don't support avx512. This reverts commit r229837. llvm-svn: 229942
* Add a license header to the AVX512 file.Eric Christopher2015-02-201-0/+15
| | | | llvm-svn: 229941
* [sanitizer] when dumping the basic block trace, also dump the module names. ↵Kostya Serebryany2015-02-201-3/+12
| | | | | | Patch by Laszlo Szekeres llvm-svn: 229940
* This needs to be a const variable so the two sides of the ternaryEric Christopher2015-02-201-1/+2
| | | | | | operator agree on type. llvm-svn: 229938
* [objc-arc-contract] We can not move retains over instructions which can not ↵Michael Gottesman2015-02-202-39/+152
| | | | | | | | | | conservatively be proven to not decrement the retain's RCIdentity. I also cleaned up the code to make it more understandable for mere mortals. <rdar://problem/19853758> llvm-svn: 229937
* [objc-arc] Add the predicate CanDecrementRefCount.Michael Gottesman2015-02-204-2/+61
| | | | | | | | | This is different from CanAlterRefCount since CanDecrementRefCount is attempting to prove specifically whether or not an instruction can decrement instead of the more general question of whether it can decrement or increment. llvm-svn: 229936
* IR: Fix MDType fields from unsigned to uint64_tDuncan P. N. Exon Smith2015-02-193-28/+28
| | | | | | | | | When trying to match the current schema with the new debug info hierarchy, I downgraded `SizeInBits`, `AlignInBits` and `OffsetInBits` to 32-bits (oops!). Caught this while testing my upgrade script to move the hierarchy into place. Bump it back up to 64-bits and update tests. llvm-svn: 229933
* [ARM] Re-re-apply VLD1/VST1 base-update combine.Ahmed Bougacha2015-02-192-19/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This re-applies r223862, r224198, r224203, and r224754, which were reverted in r228129 because they exposed Clang misalignment problems when self-hosting. The combine caused the crashes because we turned ISD::LOAD/STORE nodes to ARMISD::VLD1/VST1_UPD nodes. When selecting addressing modes, we were very lax for the former, and only emitted the alignment operand (as in "[r1:128]") when it was larger than the standard alignment of the memory type. However, for ARMISD nodes, we just used the MMO alignment, no matter what. In our case, we turned ISD nodes to ARMISD nodes, and this caused the alignment operands to start being emitted. And that's how we exposed alignment problems that were ignored before (but I believe would have been caught with SCTRL.A==1?). To fix this, we can just mirror the hack done for ISD nodes: only take into account the MMO alignment when the access is overaligned. Original commit message: We used to only combine intrinsics, and turn them into VLD1_UPD/VST1_UPD when the base pointer is incremented after the load/store. We can do the same thing for generic load/stores. Note that we can only combine the first load/store+adds pair in a sequence (as might be generated for a v16f32 load for instance), because other combines turn the base pointer addition chain (each computing the address of the next load, from the address of the last load) into independent additions (common base pointer + this load's offset). rdar://19717869, rdar://14062261. llvm-svn: 229932
* Only use the initialized MCInstrInfo if it's been initialized alreadyEric Christopher2015-02-191-1/+5
| | | | | | | | during SetupMachineFunction. This is also the single use of MII and it'll be changing to TargetInstrInfo (which is MachineFunction based) in the next commit here. llvm-svn: 229931
* [ARM] Minor cleanup to CombineBaseUpdate. NFC.Ahmed Bougacha2015-02-191-20/+22
| | | | | | | | | | | In preparation for a future patch: - rename isLoad to isLoadOp: the former is confusing, and can be taken to refer to the fact that the node is an ISD::LOAD. (it isn't, yet.) - change formatting here and there. - add some comments. - const-ify bools. llvm-svn: 229929
* Migrate away a use of the subtarget (and TargetMachine) fromEric Christopher2015-02-191-5/+4
| | | | | | | AsmPrinterDwarf since the information is on the MCRegisterInfo via the MCContext and MMI that we already have on the AsmPrinter. llvm-svn: 229928
* IR: Add missing null operand to MDSubroutineTypeDuncan P. N. Exon Smith2015-02-191-1/+1
| | | | | | | | | Add missing `nullptr` from `MDSubroutineType`'s operands for `MDCompositeTypeBase::getIdentifier()` (and add tests for all the other unused fields). This highlights just how crazy it is that `MDSubroutineType` inherits from `MDCompositeTypeBase`. llvm-svn: 229926
* [CodeGen] Use ArrayRef instead of std::vector&. NFC.Ahmed Bougacha2015-02-193-3/+3
| | | | | | The former lets us use SmallVectors. Do so in ARM and AArch64. llvm-svn: 229925
* MCTargetOptions reside on the TargetMachine that we always have viaEric Christopher2015-02-191-5/+2
| | | | | | TargetOptions. llvm-svn: 229917
* Remove a call to TargetMachine::getSubtarget from the inlineEric Christopher2015-02-191-1/+11
| | | | | | | | | asm support in the asm printer. If we can get a subtarget from the machine function then we should do so, otherwise we can go ahead and create a default one since we're at the module level. llvm-svn: 229916
* [Hexagon] Moving remaining methods off of HexagonMCInst in to ↵Colin LeMahieu2015-02-1913-173/+113
| | | | | | HexagonMCInstrInfo and eliminating HexagonMCInst class. llvm-svn: 229914
* MC: Allow multiple comma-separated expressions on the .uleb128 directive.Benjamin Kramer2015-02-191-9/+15
| | | | | | | For compatiblity with GNU as. Binutils documents this as '.uleb128 expressions'. Subtle, isn't it? llvm-svn: 229911
* SSAUpdater: Use range-based for. NFC.Benjamin Kramer2015-02-191-24/+17
| | | | llvm-svn: 229908
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