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* Revert r277408 and r277407Bruno Cardoso Lopes2016-08-021-34/+0
| | | | | | | | | | Revert r277408 "Fix test from rL277407." Revert r277407 "[MC] Fix handling of end-of-line preprocessor comments" This is currently breaking: http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_check/20731 llvm-svn: 277412
* CodeExtractor : Add ability to preserve profile data.Sean Silva2016-08-025-20/+142
| | | | | | | | | | | Added ability to estimate the entry count of the extracted function and the branch probabilities of the exit branches. Patch by River Riddle! Differential Revision: https://reviews.llvm.org/D22744 llvm-svn: 277411
* Tie the Verifier class to a Module; NFCISanjoy Das2016-08-021-72/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit changes the Verifier class to accept a Module via the constructor to make it obvious that a specific instance of the class is only intended to work with a specific module. The `updateModule` setter (despite being private) was making this fact less transparent. There are fields in the `Verifier` class like `DeoptimizeDeclarations` and `GlobalValueVisited` which are module specific, so a given Verifier instance will not in fact work across multiple modules today. This change just makes that more obvious. The motivation is to make it easy to get to the datalayout of the module unambiguously. That is required to verify that `inttoptr` and `ptrtoint` constant expressions are well typed in the face of non-integral pointer types. Reviewers: dexonsmith, bkramer, majnemer, chandlerc Subscribers: mehdi_amini, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D23040 llvm-svn: 277409
* [MC] Fix handling of end-of-line preprocessor commentsNirav Dave2016-08-021-0/+34
| | | | | | | | | | | | | | | | | | | | | Summary: When parsing assembly where the line comment syntax is not hash, the lexer cannot distinguish between hash's that start a hash line comment and one that is part of an assembly statement and must be distinguished during parsing. Previously, this was incompletely handled by not checking for EndOfStatement at the end of statements and interpreting hash prefixed statements as comments. Change EndOfStatement Parsing to check for Hash comments and reintroduce Hash statement parsing to catch previously handled cases. Reviewers: rnk, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23017 llvm-svn: 277407
* Revert r276895 "[MC][X86] Fix Intel Operand assembly parsing for .set ids"Hans Wennborg2016-08-011-79/+115
| | | | | | This caused PR28805. Adding a regression test. llvm-svn: 277402
* [ADT] NFC: Generalize GraphTraits requirement of "NodeType *" in interfaces ↵Tim Shen2016-08-012-0/+2
| | | | | | | | | | | | | | to "NodeRef", and migrate SCCIterator.h to use NodeRef Summary: By generalize the interface, users are able to inject more flexible Node token into the algorithm, for example, a pair of vector<Node>* and index integer. Currently I only migrated SCCIterator to use NodeRef, but more is coming. It's a NFC. Reviewers: dblaikie, chandlerc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22937 llvm-svn: 277399
* [WebAssembly] Support CFI for WebAssembly targetDerek Schuff2016-08-015-28/+96
| | | | | | | | | | | | | | | Summary: This patch implements CFI for WebAssembly. It modifies the LowerTypeTest pass to pre-assign table indexes to functions that are called indirectly, and lowers type checks to test against the appropriate table indexes. It also modifies the WebAssembly backend to support a special ".indidx" assembly directive that propagates the table index assignments out to the linker. Patch by Dominic Chen Differential Revision: https://reviews.llvm.org/D21768 llvm-svn: 277398
* [Orc] Fix common symbol support in ORC.Lang Hames2016-08-011-2/+8
| | | | | | | | | | | | | Common symbol support in ORC was broken in r270716 when the symbol resolution rules in RuntimeDyld were changed. With the switch to lazily materialized symbols in r277386, common symbols can be supported by having RuntimeDyld::emitCommonSymbols search for (but not materialize!) definitions elsewhere in the logical dylib. This patch adds the 'Common' flag to JITSymbolFlags, and the necessary check to RuntimeDyld::emitCommonSymbols. llvm-svn: 277397
* Simplify some code found when it was moved in r277177David Blaikie2016-08-011-10/+10
| | | | llvm-svn: 277394
* [PM] Port SpeculativeExecution to the new PMMichael Kuperstein2016-08-014-40/+60
| | | | | | Differential Revision: https://reviews.llvm.org/D23033 llvm-svn: 277393
* [WebAssembly] Add asm.js-style exception handling supportDerek Schuff2016-08-014-0/+477
| | | | | | | | | | | | | | | | | | Summary: This patch includes asm.js-style exception handling support for WebAssembly. The WebAssembly MVP does not have any support for unwinding or non-local control flow. In order to support C++ exceptions, emscripten currently uses JavaScript exceptions along with some support code (written in JavaScript) that is bundled by emscripten with the generated code. This scheme lowers exception-related instructions for wasm such that wasm modules can be compatible with emscripten's existing scheme and share the support code. Patch by Heejin Ahn Differential Revision: https://reviews.llvm.org/D22958 llvm-svn: 277391
* [msf] Teach LLVM to parse a split Fpm.Zachary Turner2016-08-011-8/+35
| | | | | | | | | | | | | | | | | | | | The FPM is split at regular intervals across the MSF file, as the MS code suggests. It turns out that the value of the interval is precisely the block size. If the block size is 4096, then there are two Fpm pages every 4096 blocks. So here we teach the PDBFile class to parse a split FPM, and also add more options when dumping the FPM to display some additional information such as orphaned pages (pages which the FPM says are allocated, but which nothing appears to use), use after free pages (pages which the FPM says are not allocated, but which are referenced by a stream), and multiple use pages (pages which the FPM says are allocated but are used more than once). Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D23022 llvm-svn: 277388
* [ExecutionEngine][MCJIT][Orc] Replace RuntimeDyld::SymbolInfo with JITSymbol.Lang Hames2016-08-0122-89/+86
| | | | | | | | | | | | | | | | This patch replaces RuntimeDyld::SymbolInfo with JITSymbol: A symbol class that is capable of lazy materialization (i.e. the symbol definition needn't be emitted until the address is requested). This can be used to support common and weak symbols in the JIT (though this is not implemented in this patch). For consistency, RuntimeDyld::SymbolResolver is renamed to JITSymbolResolver. For space efficiency a new class, JITEvaluatedSymbol, is introduced that behaves like the old RuntimeDyld::SymbolInfo - i.e. it is just a pair of an address and symbol flags. Instances of JITEvaluatedSymbol can be used in symbol-tables to avoid paying the space cost of the materializer. llvm-svn: 277386
* [Hexagon] Tidy up some code, NFC: reapply r277372 with a fixKrzysztof Parzyszek2016-08-012-192/+175
| | | | llvm-svn: 277383
* [Profile] IR profiling minor cleanup /nfcXinliang David Li2016-08-011-5/+15
| | | | | | Differential Revision: http://reviews.llvm.org/D22995 llvm-svn: 277379
* [LV] Move isGatherOrScatterLegal into LoopVectorizationLegality (NFC)Matthew Simpson2016-08-011-15/+13
| | | | llvm-svn: 277376
* [LV] Use getPointerOperand helper where appropriate (NFC)Matthew Simpson2016-08-011-27/+21
| | | | llvm-svn: 277375
* Revert r277372, it is causing buildbot failuresKrzysztof Parzyszek2016-08-012-173/+186
| | | | llvm-svn: 277374
* [Hexagon] Tidy up some code, NFCKrzysztof Parzyszek2016-08-012-186/+173
| | | | llvm-svn: 277372
* [DAGCombine] Make sext(setcc) combine respect getBooleanContentsMichael Kuperstein2016-08-012-9/+33
| | | | | | | | | | | We used to combine "sext(setcc x, y, cc) -> (select (setcc x, y, cc), -1, 0)" Instead, we should combine to (select (setcc x, y, cc), T, 0) where the value of T is 1 or -1, depending on the type of the setcc, and getBooleanContents() for the type if it is not i1. This fixes PR28504. llvm-svn: 277371
* [Hexagon] Generate vector printing instructionsRon Lieberman2016-08-013-0/+188
| | | | llvm-svn: 277370
* [CFLAA] Remove modref queries from CFLAA.George Burgess IV2016-08-012-188/+0
| | | | | | | | | | | | | | | | | | | | As it turns out, modref queries are broken with CFLAA. Specifically, the data source we were using for determining modref behaviors explicitly ignores operations on non-pointer values. So, it wouldn't note e.g. storing an i32 to an i32* (or loading an i64 from an i64*). It also ignores external function calls, rather than acting conservatively for them. (N.B. These operations, where necessary, *are* tracked by CFLAA; we just use a different mechanism to do so. Said mechanism is relatively imprecise, so it's unlikely that we can provide reasonably good modref answers with it as implemented.) Patch by Jia Chen. Differential Revision: https://reviews.llvm.org/D22978 llvm-svn: 277366
* [AArch64] Add support for Samsung Exynos M2 (NFC).Evandro Menezes2016-08-012-0/+7
| | | | llvm-svn: 277364
* [CFLAA] Make CFLAnders more conservative with new Values.George Burgess IV2016-08-011-4/+7
| | | | | | | | | | | | | | Currently, CFLAnders assumes that values it hasn't seen don't alias anything. This patch fixes that. Given that the only way for this to happen is to query AA, rely on specific transformations happening, then query AA again (looking for a specific set of queries), lit testing is a bit difficult. If someone really wants a test, I'm happy to add one. Patch by Jia Chen. Differential Revision: https://reviews.llvm.org/D22981 llvm-svn: 277362
* [Verifier] Resume instructions can only be in functions w/ a personalityDavid Majnemer2016-08-011-0/+16
| | | | | | This fixes PR28799. llvm-svn: 277360
* Replace MachineInstr* with MachineInstr& in TargetInstrInfo, NFCKrzysztof Parzyszek2016-08-016-40/+40
| | | | | | There were a few cases introduced with the modulo scheduler. llvm-svn: 277358
* [Hexagon] Check for offset overflow when reserving scavenging slotsKrzysztof Parzyszek2016-08-012-2/+16
| | | | | | | | | Scavenging slots were only reserved when pseudo-instruction expansion in frame lowering created new virtual registers. It is possible to still need a scavenging slot even if no virtual registers were created, in cases where the stack is large enough to overflow instruction offsets. llvm-svn: 277355
* [mips][fastisel] Correct argument lowering for (f64, f64, i32) and similar.Daniel Sanders2016-08-011-29/+55
| | | | | | | | | | | | | | | Summary: Allocating an AFGR64 shadows two GPR32's instead of just one. This fixes an LNT regression detected by our internal buildbots. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D23012 llvm-svn: 277348
* [AMDGPU] refactor DS instruction definitions. NFC.Valery Pykhtin2016-08-017-608/+896
| | | | | | Differential revision: https://reviews.llvm.org/D22522 llvm-svn: 277344
* [X86] Use implicit masking of SHLD/SHRD shift double instructionsSimon Pilgrim2016-08-011-3/+16
| | | | | | Similar to the regular shift instructions, SHLD/SHRD only use the bottom bits of the shift value llvm-svn: 277341
* Fixed MSVC out of range shift warningSimon Pilgrim2016-08-011-1/+1
| | | | llvm-svn: 277333
* [SimplifyCFG] Fix nasty RAUW bug from r277325James Molloy2016-08-011-3/+4
| | | | | | | | | | | | | | | Using RAUW was wrong here; if we have a switch transform such as: 18 -> 6 then 6 -> 0 If we use RAUW, while performing the second transform the *transformed* 6 from the first will be also replaced, so we end up with: 18 -> 0 6 -> 0 Found by clang stage2 bootstrap; testcase added. llvm-svn: 277332
* [AArch64] Return the correct size for TLSDESC_CALLSEQDiana Picus2016-08-011-0/+3
| | | | | | | | | | | | | | The branch relaxation pass is computing the wrong offsets because it assumes TLSDESC_CALLSEQ eats up 4 bytes, when in fact it is lowered to an instruction sequence taking up 16 bytes. This can become a problem in huge files with lots of TLS accesses, as it may slowly move branch targets out of the range computed by the branch relaxation pass. Fixes PR24234 https://llvm.org/bugs/show_bug.cgi?id=24234 Differential Revision: https://reviews.llvm.org/D22870 llvm-svn: 277331
* [AVX-512] Fix duplicate column in AVX512 execution dependency table that was ↵Craig Topper2016-08-011-18/+18
| | | | | | preventing VMOVDQU32/VMOVDQA32 from being recognized. Fix a bug in the code that stops execution dependency fix from turning operations on 32-bit integer element types into operations on 64-bit integer element types. llvm-svn: 277327
* [SimplifyCFG] Range reduce switchesJames Molloy2016-08-011-0/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a switch is sparse and all the cases (once sorted) are in arithmetic progression, we can extract the common factor out of the switch and create a dense switch. For example: switch (i) { case 5: ... case 9: ... case 13: ... case 17: ... } can become: if ( (i - 5) % 4 ) goto default; switch ((i - 5) / 4) { case 0: ... case 1: ... case 2: ... case 3: ... } or even better: switch ( ROTR(i - 5, 2) { case 0: ... case 1: ... case 2: ... case 3: ... } The division and remainder operations could be costly so we only do this if the factor is a power of two, and emit a right-rotate instead of a divide/remainder sequence. Dense switches can be lowered significantly better than sparse switches and can even be transformed into lookup tables. llvm-svn: 277325
* [mips] Clang generates unaligned offset for MSA instruction st.dHrvoje Varga2016-08-016-49/+123
| | | | | | Differential Revision: https://reviews.llvm.org/D19475 llvm-svn: 277323
* [AArch64] Register passes so they can be run by llcDiana Picus2016-08-0115-110/+125
| | | | | | | | | | | | | | Initialize all AArch64-specific passes in the TargetMachine so they can be run by llc. This can lead to conflicts in opt with some command line options that share the same name as the pass, so I took this opportunity to do some cleanups: * rename all relevant command line options from "aarch64-blah" to "aarch64-enable-blah" and update the tests accordingly * run clang-format on their declarations * move all these declarations to a common place (the TargetMachine) as opposed to having them scattered around (AArch64BranchRelaxation and AArch64AddressTypePromotion were the only offenders) llvm-svn: 277322
* [AVX-512] Teach X86InstrInfo::getLargestLegalSuperClass to inflate to ↵Craig Topper2016-08-011-4/+26
| | | | | | | | FR32X/FR64X if AVX512 is supported and VR128X/VR256X if VLX is supported. Had to update a stack folding test to clobber the other 16 registers since this now made them get used instead of spilling. llvm-svn: 277321
* [AVX-512] Use FR32X/FR64X/VR128X/VR256X register classes in addRegisterClass ↵Craig Topper2016-08-011-15/+30
| | | | | | if AVX512(for FR32X/FR64) or VLX(for VR128X/VR256) is supported. This is a minimal requirement to be able to allocate all 32 registers. llvm-svn: 277319
* [X86] Move mask register handling into the main switch of ↵Craig Topper2016-08-011-22/+6
| | | | | | getLoadStoreRegOpcode. No functional change intended. llvm-svn: 277318
* Revert r277313 and r277314.Sean Silva2016-08-015-163/+23
| | | | | | | | | | | | | | | They seem to trigger an LSan failure: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/15140/steps/check-llvm%20asan/logs/stdio Revert "Add the tests for r277313" This reverts commit r277314. Revert "CodeExtractor : Add ability to preserve profile data." This reverts commit r277313. llvm-svn: 277317
* Fix - CodeExtractor : Inherit Target Dependent Attributes from the parent ↵Sean Silva2016-08-011-1/+16
| | | | | | | | | | | | | | | | | | | function. When extracting a set of blocks make sure to inherit all of the target dependent attributes to make sure that the function will be valid for lowering. One example is the "target-features" attribute for x86, if the extracted region has functionality that relies on a specific feature it will fail to be lowered. This also allows for extracted functions to be valid for inlining, at least back into the parent function, as the target attributes are tested when inlining for compatibility. Patch by River Riddle! Differential Revision: https://reviews.llvm.org/D22713 llvm-svn: 277315
* CodeExtractor : Add ability to preserve profile data.Sean Silva2016-08-015-23/+163
| | | | | | | | | | | Added ability to estimate the entry count of the extracted function and the branch probabilities of the exit branches. Patch by River Riddle! Differential Revision: https://reviews.llvm.org/D22744 llvm-svn: 277313
* Fix the MemorySSA updating API to enable people to create memory accesses ↵Daniel Berlin2016-07-311-4/+6
| | | | | | before removing old ones llvm-svn: 277309
* [X86] Simplify code for determing GR or FR reg classes by querying for super ↵Craig Topper2016-07-311-49/+10
| | | | | | classes instead of manually listing individual classes. llvm-svn: 277306
* [AVX512] Always use EVEX encodings for 128/256-bit move instructions in ↵Craig Topper2016-07-311-24/+15
| | | | | | getLoadStoreRegOpcode if VLX is supported. llvm-svn: 277305
* [AVX512] Add VLX packed move instructions to the execution dependency fix ↵Craig Topper2016-07-311-5/+15
| | | | | | pass and update tests. llvm-svn: 277304
* [AVX512] Move FR32X/FR64X handling in getLoadStoreRegOpcode into the main ↵Craig Topper2016-07-311-15/+11
| | | | | | switch. No functional change intended. llvm-svn: 277303
* [AVX512] Stop treating VR512 specially in getLoadStoreRegOpcode and use the ↵Craig Topper2016-07-311-3/+1
| | | | | | regular switch which already tried to handle it, but was unreachable. This has the added benefit of enabling aligned loads/stores if the stack is aligned. llvm-svn: 277302
* [AVX512] Add X86::VR512RegClassID to X86RegisterInfo::getLargestLegalSuperClass.Craig Topper2016-07-311-0/+1
| | | | llvm-svn: 277301
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