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* [X86] Simplify early-exit check. NFC.Ahmed Bougacha2016-04-051-4/+4
| | | | llvm-svn: 265447
* [GlobalISel] Add a class, RegisterBank, to represent register banks.Quentin Colombet2016-04-052-0/+40
| | | | llvm-svn: 265445
* fix typo; NFCSanjay Patel2016-04-051-1/+1
| | | | llvm-svn: 265442
* [GlobalISel] Add the skeleton of the RegBankSelect pass.Quentin Colombet2016-04-053-0/+34
| | | | | | | This pass is reponsible for assigning the generic virtual registers to register banks. llvm-svn: 265440
* fix documentation comments; NFCSanjay Patel2016-04-051-39/+34
| | | | llvm-svn: 265434
* Swift Calling Convention: swifterror target-independent change.Manman Ren2016-04-055-4/+353
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At IR level, the swifterror argument is an input argument with type ErrorObject**. For targets that support swifterror, we want to optimize it to behave as an inout value with type ErrorObject*; it will be passed in a fixed physical register. The main idea is to track the virtual registers for each swifterror value. We define swifterror values as AllocaInsts with swifterror attribute or a function argument with swifterror attribute. In SelectionDAGISel.cpp, we set up swifterror values (SwiftErrorVals) before handling the basic blocks. When iterating over all basic blocks in RPO, before actually visiting the basic block, we call mergeIncomingSwiftErrors to merge incoming swifterror values when there are multiple predecessors or to simply propagate them. There, we create a virtual register for each swifterror value in the entry block. For predecessors that are not yet visited, we create virtual registers to hold the swifterror values at the end of the predecessor. The assignments are saved in SwiftErrorWorklist and will be materialized at the end of visiting the basic block. When visiting a load from a swifterror value, we copy from the current virtual register assignment. When visiting a store to a swifterror value, we create a virtual register to hold the swifterror value and update SwiftErrorMap to track the current virtual register assignment. Differential Revision: http://reviews.llvm.org/D18108 llvm-svn: 265433
* [lanai] LanaiSetflagAluCombiner more conservativeJacques Pienaar2016-04-051-5/+7
| | | | | | | | | | | | Summary: LanaiSetflagAluCombiner could previously combine instructions across basic building blocks even when not legal. Make the LanaiSetflagAluCombiner more conservative to avoid this. Reviewers: eliben Subscribers: joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D18746 llvm-svn: 265411
* [ARM] Cleanup of smul and smla instruction descriptionsSam Parker2016-04-051-12/+12
| | | | | | | | | Removed the SDNode argument passed to the AI_smul and AI_smla multiclass definitions as they are always mul. Differential Revision: http://reviews.llvm.org/D18791 llvm-svn: 265409
* [AMDGPU] Emit linkonce and linkonce_odr symbolsKonstantin Zhuravlyov2016-04-051-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D18726 llvm-svn: 265408
* [BlockPlacement] Remove an unnecessary continueHaicheng Wu2016-04-051-1/+0
| | | | | | NFC. llvm-svn: 265407
* Don't delete empty preheaders in CodeGenPrepare if it would create a ↵Chuang-Yu Cheng2016-04-051-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | critical edge Presently, CodeGenPrepare deletes all nearly empty (only phi and branch) basic blocks. This pass can delete loop preheaders which frequently creates critical edges. A preheader can be a convenient place to spill registers to the stack. If the entrance to a loop body is a critical edge, then spills may occur in the loop body rather than immediately before it. This patch protects loop preheaders from deletion in CodeGenPrepare even if they are nearly empty. Since the patch alters the CFG, it affects a large number of test cases. In most cases, the changes are merely cosmetic (basic blocks have different names or instruction orders change slightly). I am somewhat concerned about the test/CodeGen/Mips/brdelayslot.ll test case. If the loop preheader is not deleted, then the MIPS backend does not take advantage of a branch delay slot. Consequently, I would like some close review by a MIPS expert. The patch also partially subsumes D16893 from George Burgess IV. George correctly notes that CodeGenPrepare does not actually preserve the dominator tree. I think the dominator tree was usually not valid when CodeGenPrepare ran, but I am using LoopInfo to mark preheaders, so the dominator tree is now always valid before CodeGenPrepare. Author: Tom Jablin (tjablin) Reviewers: hfinkel george.burgess.iv vkalintiris dsanders kbarton cycheng http://reviews.llvm.org/D16984 llvm-svn: 265397
* [llvm-c] Expose LLVM{Get,Set}ModuleIdentifierPeter Zotov2016-04-051-0/+11
| | | | | | | | Patch by Nicole Mazzuca <npmazzuca@gmail.com>. Differential Revision: http://reviews.llvm.org/D18736 llvm-svn: 265394
* [mips] MIPSR6 Compact jump supportSimon Dardis2016-04-054-67/+109
| | | | | | | | | | | | | | | This patch adds support for compact jumps similiar to the previous compact branch support for MIPSR6. Unlike compact branches, compact jumps do not have a forbidden slot. As MipsInstrInfo::getEquivalentCompactForm can determine the correct expansion for jumps and branches for both microMIPS and MIPSR6, remove the unnecessary distinction in the delay slot filler. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders llvm-svn: 265390
* [NVPTX] Handle ldg created from sign-/zero-extended loadJustin Holewinski2016-04-052-4/+91
| | | | | | | | | | Reviewers: jingyue Subscribers: jholewinski Differential Revision: http://reviews.llvm.org/D18053 llvm-svn: 265389
* Adds the ability to use an epilog remainder loop during loop unrolling and makesDavid L Kreitzer2016-04-052-78/+336
| | | | | | | | | | this the default behavior. Patch by Evgeny Stupachenko (evstupac@gmail.com). Differential Revision: http://reviews.llvm.org/D18158 llvm-svn: 265388
* Add parentheses around `&&` within `||` to avoid compiler warning message.Haojian Wu2016-04-051-3/+2
| | | | | | | | | | | | Summary: The assert code is introduced by r265370. Reviewers: bkramer Subscribers: tejohnson Differential Revision: http://reviews.llvm.org/D18786 llvm-svn: 265383
* [IFUNC] Use GlobalIndirectSymbol when aliases and ifuncs have something similarDmitry Polukhin2016-04-057-102/+137
| | | | | | | | | | | Second part extracted from http://reviews.llvm.org/D15525 Use GlobalIndirectSymbol in all cases when aliases and ifuncs have something in common. Differential Revision: http://reviews.llvm.org/D18754 llvm-svn: 265382
* [ThinLTO] Refactor some common code into getGlobalValueInfo method (NFC)Teresa Johnson2016-04-052-12/+14
| | | | | | | | Refactor common code that queries the ModuleSummaryIndex for a value's GlobalValueInfo struct into getGlobalValueInfo helper methods, which will also be used by D18763. llvm-svn: 265370
* Lanai: fix -Wsign-compare warningJF Bastien2016-04-051-1/+1
| | | | llvm-svn: 265368
* Don't fold double constant to an integer if dest type not integralTeresa Johnson2016-04-041-0/+4
| | | | | | | | | | | | | | Summary: I encountered this issue when constant folding during inlining tried to fold away a bitcast of a double to an x86_mmx, which is not an integral type. The test case exposes the same issue with a smaller code snippet during early CSE. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18528 llvm-svn: 265367
* Lanai: fix -Wpedantic warningsJF Bastien2016-04-042-2/+2
| | | | | | Extra semicolon. llvm-svn: 265365
* Fix non-determinism in order of LLVM attributesReid Kleckner2016-04-041-2/+6
| | | | | | | | | | | | | | | | | | We were using array_pod_sort on an array of type 'Attribute', which wraps a pointer to AttributeImpl. For the most part this didn't matter because the printing code prints enum attributes in a defined order, but integer attributes such as 'align' and 'dereferenceable' were not ordered. Furthermore, AttributeImpl::operator< was broken for integer attributes. An integer attribute is a kind and an integer value, and both pieces need to be compared. By fixing the comparison operator, we can go back to std::sort, and things look good now. This should fix clang arm-swiftcall.c test failures on Windows. llvm-svn: 265361
* use range loop; NFCISanjay Patel2016-04-041-3/+3
| | | | llvm-svn: 265360
* fix typos; NFCSanjay Patel2016-04-041-2/+2
| | | | llvm-svn: 265356
* Style update in Core.h/Core.cpp . NFCAmaury Sechet2016-04-041-2/+2
| | | | llvm-svn: 265353
* Revert "CodeGen: Remove dead code in TailDuplicate"Justin Bogner2016-04-041-14/+58
| | | | | | | | | | | It seems this is reachable after all. It hit on 7zip-benchmark in lnt on ppc64: http://lab.llvm.org:8011/builders/clang-ppc64be-linux-lnt/builds/2317 This reverts r265347. llvm-svn: 265352
* MachineScheduler: Ignore COPYs with undef/dead op in CopyConstrain mutation.Matthias Braun2016-04-041-4/+6
| | | | | | | | There is no problem with the code today, but the fix will avoid a crash in test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll once the DetectDeadLanes pass is added. llvm-svn: 265351
* Clean up calls to WriteBitcodeToFile (NFC)Teresa Johnson2016-04-041-1/+1
| | | | | | | | | | | Remove a default parameter value being passed unnecessarily, which also reduces the changes required when this parameter is changed in D18763. Document the remaining non-default bool value passed for another parameter. llvm-svn: 265348
* CodeGen: Remove dead code in TailDuplicateJustin Bogner2016-04-041-58/+14
| | | | | | | | | | | | | | | | I noticed that this isn't covered by our existing tests and spent some time trying to come up with an example it actually hits. I tried hand rolling something based on the explanation in the comment, but couldn't get anything that didn't abort tail duplication earlier for one reason or another. Then, I tried cranking tail-dup-size cranked up so this would fire more and ran a bootstrap of clang and the nightly test suite - those don't hit this either. This reverts r132816 and replaces it with an assert. llvm-svn: 265347
* Re-commit r265039 "[X86] Merge adjacent stack adjustments in ↵Hans Wennborg2016-04-041-13/+26
| | | | | | | | | | | | | | | | | | | | eliminateCallFramePseudoInstr (PR27140)" The original commit miscompiled things on 32-bit Windows, e.g. a Clang boostrap. It turns out that mergeSPUpdates() was a bit too generous in what it interpreted as a stack adjustment, causing the following code: addl $12, %esp leal -4(%ebp), %esp To be "optimized" into simply: addl $8, %esp This commit tightens up mergeSPUpdates() and includes a new test (test14 in movtopush.ll) for this situation. llvm-svn: 265345
* Enable unroll for constant bound loops when TripCount is not modulo of ↵Zia Ansari2016-04-041-0/+10
| | | | | | | | | | unroll factor, reducing it to maximum power-of-2 that satisfies threshold limit. Commit for Evgeny Stupachenko (evstupac@gmail.com) Differential Revision: http://reviews.llvm.org/D18290 llvm-svn: 265337
* Revert r263460: [SpillPlacement] Fix a quadratic behavior in spill placement.Chandler Carruth2016-04-042-44/+53
| | | | | | | | | | | | | | | | | That commit looks wonderful and awesome. Sadly, it greatly exacerbates PR17409 and effectively regresses build time for a lot of (very large) code when compiled with ASan or MSan. We thought this could be fixed forward by landing D15302 which at last fixes that PR, but some issues were discovered and it looks like that got reverted, so reverting this as well temporarily. As soon as the fix for PR17409 lands and sticks, we should re-land this patch as it won't trigger more significant test cases hitting that bug. Many thanks to Quentin and Wei here as they're doing all the awesome hard work!!! llvm-svn: 265331
* [PGO] Avoid instrumenting direct callee's at value sites.Betul Buyukkurt2016-04-041-0/+2
| | | | | | | | | | Direct callees' that are cast to other function prototypes, show up in the Call/Invoke instructions as ConstantExpr's. Currently llvm::CallSite's getCalledFunction() fails to return the callees in such expressions as direct calls. Value profiling should avoid instrumenting such cases. Mostly NFC. llvm-svn: 265330
* ARM, AArch64, X86: Check preserved registers for tail calls.Matthias Braun2016-04-044-22/+30
| | | | | | | | | | | | | | | | We can only perform a tail call to a callee that preserves all the registers that the caller needs to preserve. This situation happens with calling conventions like preserver_mostcc or cxx_fast_tls. It was explicitely handled for fast_tls and failing for preserve_most. This patch generalizes the check to any calling convention. Related to rdar://24207743 Differential Revision: http://reviews.llvm.org/D18680 llvm-svn: 265329
* [ThinLTO] Add option to dump value name to GUID mappingTeresa Johnson2016-04-041-5/+17
| | | | | | | | | | | | | | | Summary: Useful for debugging since we lose this correlation after the permodule summary/VST is read and until we later materialize source modules in the function importer. Reviewers: joker.eph Subscribers: llvm-commits, joker.eph Differential Revision: http://reviews.llvm.org/D18555 llvm-svn: 265327
* [ThinLTO] Augment FunctionImport dump with value name to GUID mapTeresa Johnson2016-04-041-3/+18
| | | | | | | | | | | | | | | | Summary: To aid in debugging, dump out the correlation between value names and GUID for each source module when it is materialized. This will make it easier to comprehend the earlier summary-based function importing debug trace which only has access to and prints the GUIDs. Reviewers: joker.eph Subscribers: llvm-commits, joker.eph Differential Revision: http://reviews.llvm.org/D18556 llvm-svn: 265326
* [DependenceAnalysis] Check if result of getConstantPart is nullBrendon Cahoon2016-04-041-0/+6
| | | | | | | | | | | A seg-fault occurs due to a reference of a null pointer, which is the value returned by getConstantPart. This function returns null if the constant part is not found. The code that calls this function needs to check for the null return value. Differential Revision: http://reviews.llvm.org/D18718 llvm-svn: 265319
* Replace MachineRegisterInfo::isSSA() with a MachineFunctionPropertyDerek Schuff2016-04-042-17/+15
| | | | | | | | | Use the MachineFunctionProperty mechanism to indicate whether a MachineFunction is in SSA form instead of a custom method on MachineRegisterInfo. NFC Differential Revision: http://reviews.llvm.org/D18574 llvm-svn: 265318
* Revert r265309 and r265312 because they caused some errors I need to ↵Wei Mi2016-04-0410-715/+527
| | | | | | investigate. llvm-svn: 265317
* Add MachineFunctionProperty checks for AllVRegsAllocated for target passesDerek Schuff2016-04-0444-6/+209
| | | | | | | | | | | | | | Summary: This adds the same checks that were added in r264593 to all target-specific passes that run after register allocation. Reviewers: qcolombet Subscribers: jyknight, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18525 llvm-svn: 265313
* Fix unused var warning caused by r265309.Wei Mi2016-04-041-3/+3
| | | | llvm-svn: 265312
* Replace analyzeSiblingValues with new algorithm to fix its compileWei Mi2016-04-0410-526/+714
| | | | | | | | | | | | | | | | | | | | | | | | | time issue. The patch is to solve PR17409 and its duplicates. analyzeSiblingValues is a N x N complexity algorithm where N is the number of siblings generated by reg splitting. Although it causes siginificant compile time issue when N is large, it is also important for performance since it removes redundent spills and enables rematerialization. To solve the compile time issue, the patch removes analyzeSiblingValues and replaces it with lower cost alternatives containing two parts. The first part creates a new spill hoisting method in postOptimization of register allocation. It does spill hoisting at once after all the spills are generated instead of inside every instance of selectOrSplit. The second part queries the define expr of the original register for rematerializaiton and keep it always available during register allocation even if it is already dead. It deletes those dead instructions only in postOptimization. With the two parts in the patch, it can remove analyzeSiblingValues without sacrificing performance. Differential Revision: http://reviews.llvm.org/D15302 llvm-svn: 265309
* [mips] Range check simm32 and fold MIPS16's imm32 into simm32.Daniel Sanders2016-04-043-39/+67
| | | | | | | | | | | | | | Summary: At this point we should be able to enable IAS by default for O32 without breaking check-all, or recursion. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18439 llvm-svn: 265302
* [SystemZ] Add compare-and-branch instructions to MCUlrich Weigand2016-04-042-21/+106
| | | | | | | | | | | | This adds MC support for fused compare + indirect branch instructions, ie. CRB, CGRB, CLRB, CLGRB, CIB, CGIB, CLIB, CLGIB. They aren't actually generated yet -- this is preparation for their use for conditional returns in the next iteration of D17339. Author: koriakin Differential Revision: http://reviews.llvm.org/D18742 llvm-svn: 265296
* [SystemZ] Support ATOMIC_FENCEUlrich Weigand2016-04-045-0/+40
| | | | | | | | | | | A cross-thread sequentially consistent fence should be lowered into z/Architecture's BCR serialization instruction, instead of causing a fatal error in the back-end. Author: bryanpkc Differential Revision: http://reviews.llvm.org/D18644 llvm-svn: 265292
* [SystemZ] Support llvm.frameaddress/llvm.returnaddress intrinsicsUlrich Weigand2016-04-043-2/+64
| | | | | | | | | | | Enable the SystemZ back-end to lower FRAMEADDR and RETURNADDR, which previously would cause the back-end to crash. Currently, only a frame count of zero is supported. Author: bryanpkc Differential Revision: http://reviews.llvm.org/D18514 llvm-svn: 265291
* AVX-512: Truncating store for i1 vectorsElena Demikhovsky2016-04-041-1/+62
| | | | | | | | | Implemented truncstore for KNL and skylake-avx512. Covered vectors from v2i1 to v64i1. We save the value in bits (not in bytes) - v32i1 is saved in 4 bytes. Differential Revision: http://reviews.llvm.org/D18740 llvm-svn: 265283
* ValueMapper: Remove old FIXMEs; almost NFCDuncan P. N. Exon Smith2016-04-041-21/+1
| | | | | | | | | | | | | | | | | | | | | Remove a few old FIXMEs from the original commit of the Metadata/Value split in r223802. These are commented out assertions to the effect that calls between mapValue and mapMetadata never return nullptr. (The only behaviour change is that Mapper::mapSimpleMetadata memoizes the nullptr return.) When I originally rewrote the mapping code, I thought we could be stricter in the new metadata hierarchy and never return nullptr when RF_NullMapMissingGlobalValues was off. It's still not entirely clear to me why these assertions failed (a few months ago, I had a theory that I forgot to write down, but that's helping no one). Understood or not, I no longer see how these commented-out assertions would be useful. I'm relegating them to the annals of source control before making significant changes to ValueMapper.cpp. llvm-svn: 265282
* IR: Lazily create ReplaceableMetadataImpl on MDNodeDuncan P. N. Exon Smith2016-04-031-31/+60
| | | | | | | | | | | | | | | | | | | RAUW support on MDNode usually requires an extra allocation for ReplaceableMetadataImpl. This is only strictly necessary if there are tracking references to the MDNode. Make the construction of ReplaceableMetadataImpl lazy, so that we don't get allocations if we don't need them. Since MDNode::isResolved now checks MDNode::isTemporary and MDNode::NumUnresolved instead of whether a ReplaceableMetadataImpl is allocated, the internal changes are intrusive (at various internal checkpoints, isResolved now has a different answer). However, there should be no real functionality change here; just slightly lazier allocation behaviour. The external semantics should be identical. llvm-svn: 265279
* Various style fix in Core.h/Core.cpp . NFCAmaury Sechet2016-04-031-7/+7
| | | | llvm-svn: 265277
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