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* Revert "Hopefully one last commit to fix this patch, addresses string reference"Eric Beckmann2017-05-081-43/+2
| | | | | | | | | | | | | | | | | | | | | Summary: This reverts commit 56beec1b1cfc6d263e5eddb7efff06117c0724d2. Revert "Quick fix to D32609, it seems .o files are not transferred in all cases." This reverts commit 7652eecd29cfdeeab7f76f687586607a99ff4e36. Revert "Update llvm-readobj -coff-resources to display tree structure." This reverts commit 422b62c4d302cfc92401418c2acd165056081ed7. Reviewers: zturner Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32958 llvm-svn: 302397
* Hopefully one last commit to fix this patch, addresses string referenceEric Beckmann2017-05-081-7/+3
| | | | | | issues. llvm-svn: 302395
* Update llvm-readobj -coff-resources to display tree structure.Eric Beckmann2017-05-071-2/+47
| | | | | | | | | | | | Summary: Continue making updates to llvm-readobj to display resource sections. This is necessary for testing the up and coming cvtres tool. Reviewers: zturner Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32609 llvm-svn: 302386
* [ConstantRange][SimplifyCFG] Add a helper method to allow SimplifyCFG to ↵Craig Topper2017-05-072-1/+12
| | | | | | | | | | determine if a ConstantRange has more than 8 elements without requiring an allocation if the ConstantRange is 64-bits wide. Previously SimplifyCFG used getSetSize which returns an APInt that is 1 bit wider than the ConstantRange's bit width. In the reasonably common case that the ConstantRange is 64-bits wide, this requires returning a 65-bit APInt. APInt's can only store 64-bits without a memory allocation so this is inefficient. The new method takes the 8 as an input and tells if the range contains more than that many elements without requiring any wider math. llvm-svn: 302385
* [ConstantRange] Remove 'Of' from name of ↵Craig Topper2017-05-071-9/+9
| | | | | | ConstantRange::isSizeStrictlySmallerThanOf so that it reads better. NFC llvm-svn: 302383
* [X86][AVX1] Improve 256-bit vector costs for integer unary intrinsics.Simon Pilgrim2017-05-071-16/+16
| | | | | | Account for subvector extraction/insertion, helps prevent the vectorizers from selecting 256-bit vectors that will have to be split anyhow on AVX1 targets. llvm-svn: 302378
* InstructionSimplify: Relanding r301766Zvi Rackover2017-05-071-20/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Re-applying r301766 with a fix to a typo and a regression test. The log message for r301766 was: ================================================================================== InstructionSimplify: Canonicalize shuffle operands. NFC-ish. Summary: Apply canonicalization rules: 1. Input vectors with no elements selected from can be replaced with undef. 2. If only one input vector is constant it shall be the second one. This allows constant-folding to cover more ad-hoc simplifications that were in place and avoid duplication for RHS and LHS checks. There are more rules we may want to add in the future when we see a justification. e.g. mask elements that select undef elements can be replaced with undef. ================================================================================== Reviewers: spatel, RKSimon Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32863 llvm-svn: 302373
* Make llvm-rtdlyd -check preserve automatic address mappings made by RuntimeDyld.Lang Hames2017-05-072-0/+16
| | | | | | | | | | | | | | | | | Currently llvm-rtdyld in -check mode will map sections to back-to-back 4k aligned slabs starting at 0x1000. Automatically remapping sections by default is helpful because it quickly exposes relocation bugs due to use of local addresses rather than load addresses (these would silently pass if the load address was not remapped). These mappings can be explicitly overridden on a per-section basis using llvm-rtdlyd's -map-section option. This patch extends this scheme to also preserve any mappings made by RuntimeDyld itself. Preserving RuntimeDyld's automatic mappings allows us to write test cases to verify that these automatic mappings have been applied. This will allow the fix in https://reviews.llvm.org/D32899 to be tested with llvm-rtdyld -check. llvm-svn: 302372
* [SCEV] Use move semantics in ScalarEvolution::setRangeCraig Topper2017-05-071-3/+3
| | | | | | | | | | | | | | Summary: This makes setRange take ConstantRange by rvalue reference since most callers were passing an unnamed temporary ConstantRange. We can then move that ConstantRange into the DenseMap caches. For the callers that weren't passing a temporary, I've added std::move to to the local variable being passed. Reviewers: sanjoy, mzolotukhin, efriedma Reviewed By: sanjoy Subscribers: takuto.ikuta, llvm-commits Differential Revision: https://reviews.llvm.org/D32943 llvm-svn: 302371
* [InstSimplify] use ConstantRange to simplify or-of-icmpsSanjay Patel2017-05-072-74/+49
| | | | | | | | | | | | | We can simplify (or (icmp X, C1), (icmp X, C2)) to 'true' or one of the icmps in many cases. I had to check some of these with Alive to prove to myself it's right, but everything seems to check out. Eg, the deleted code in instcombine was completely ignoring predicates with mismatched signedness. This is a follow-up to: https://reviews.llvm.org/rL301260 https://reviews.llvm.org/D32143 llvm-svn: 302370
* Remove unnecessary const_castSanjoy Das2017-05-071-7/+4
| | | | llvm-svn: 302368
* Use array_pod_sort instead of std::sortSanjoy Das2017-05-071-1/+1
| | | | llvm-svn: 302367
* [X86][AVX512] Relax assertion and just exit combine for unsupported types ↵Simon Pilgrim2017-05-061-1/+3
| | | | | | (PR32907) llvm-svn: 302361
* [X86][AVX512] Move v2i64/v4i64 VPABS lowering to tablegenSimon Pilgrim2017-05-062-2/+18
| | | | | | Extend NoVLX targets to use the 512-bit versions llvm-svn: 302359
* [X86] Reduce code for setting operations actions by merging into loops ↵Simon Pilgrim2017-05-061-37/+21
| | | | | | across multiple types/ops. NFCI. llvm-svn: 302357
* [NVPTX] Add support for ISD::ABS loweringSimon Pilgrim2017-05-062-7826/+7826
| | | | | | | | Use the ISD::ABS opcode directly Differential Revision: https://reviews.llvm.org/D32944 llvm-svn: 302356
* [X86][SSE] Break register dependencies on v16i8/v8i16 BUILD_VECTOR on SSE41Simon Pilgrim2017-05-061-2/+2
| | | | | | rL294581 broke unnecessary register dependencies on partial v16i8/v8i16 BUILD_VECTORs, but on SSE41 we (currently) use insertion for full BUILD_VECTORs as well. By allowing full insertion to occur on SSE41 targets we can break register dependencies here as well. llvm-svn: 302355
* [DAGCombiner] If ISD::ABS is legal/custom, use it directly instead of ↵Simon Pilgrim2017-05-061-0/+3
| | | | | | | | | | canonicalizing first. Remove an extra canonicalization step if ISD::ABS is going to be used anyway. Updated x86 abs combine to check that we are lowering from both canonicalizations. llvm-svn: 302337
* [SCEV] Remove extra APInt copies from getRangeForAffineARHelper.Craig Topper2017-05-061-13/+10
| | | | | | This changes one parameter to be a const APInt& since we only read from it. Use std::move on local APInts once they are no longer needed so we can reuse their allocations. Lastly, use operator+=(uint64_t) instead of adding 1 to an APInt twice creating a new APInt each time. llvm-svn: 302335
* [SCEV] Use std::move to avoid some APInt copies.Craig Topper2017-05-061-5/+5
| | | | llvm-svn: 302334
* [SCEV] Use APInt's uint64_t operations instead of creating a temporary APInt ↵Craig Topper2017-05-061-3/+2
| | | | | | to hold 1. llvm-svn: 302333
* [SCEV] Avoid a couple APInt copies by capturing by reference since the ↵Craig Topper2017-05-061-2/+2
| | | | | | method returns a reference. llvm-svn: 302332
* [LazyValueInfo] Avoid unnecessary copies of ConstantRangesCraig Topper2017-05-061-7/+7
| | | | | | | | | | | | | | | | | | | | | Summary: ConstantRange contains two APInts which can allocate memory if their width is larger than 64-bits. So we shouldn't copy it when we can avoid it. This changes LVILatticeVal::getConstantRange() to return its internal ConstantRange by reference. This allows many places that just need a ConstantRange reference to avoid making a copy. Several places now capture the return value of getConstantRange() by reference so they can call methods on it that don't need a new object. Lastly it adds std::move in one place to capture to move a local ConstantRange into an LVILatticeVal. Reviewers: reames, dberlin, sanjoy, anna Reviewed By: reames Subscribers: grandinj, llvm-commits Differential Revision: https://reviews.llvm.org/D32884 llvm-svn: 302331
* [sanitizer-coverage] implement -fsanitize-coverage=no-prune,... instead of a ↵Kostya Serebryany2017-05-051-4/+7
| | | | | | hidden -mllvm flag. llvm part. llvm-svn: 302319
* [RegisterBankInfo] Uniquely allocate instruction mapping.Quentin Colombet2017-05-0510-130/+176
| | | | | | | | | | This is a step toward having statically allocated instruciton mapping. We are going to tablegen them eventually, so let us reflect that in the API. NFC. llvm-svn: 302316
* Fix spelling error in command line option description. NFCCraig Topper2017-05-051-2/+2
| | | | llvm-svn: 302311
* [IR] Fix some Clang-tidy modernize-use-using warnings; other minor fixes (NFC).Eugene Zelenko2017-05-052-28/+38
| | | | llvm-svn: 302310
* [Hexagon] Disable predicated calls by defaultKrzysztof Parzyszek2017-05-053-1/+18
| | | | llvm-svn: 302307
* [Hexagon] Remove C6 and C7 as separate registersKrzysztof Parzyszek2017-05-053-20/+6
| | | | | | | These are M0 and M1. Removing duplicated registers reduces the number of explicit register aliasing. llvm-svn: 302306
* [RDF] Remove covered parts of reached uses for phi and use in same blockKrzysztof Parzyszek2017-05-053-13/+36
| | | | llvm-svn: 302305
* ARM: Compute MaxCallFrame size earlyMatthias Braun2017-05-058-12/+57
| | | | | | | | | | | | | | | | | This exposes a method in MachineFrameInfo that calculates MaxCallFrameSize and calls it after instruction selection in the ARM target. This avoids ARMBaseRegisterInfo::canRealignStack()/ARMFrameLowering::hasReservedCallFrame() giving different answers in early/late phases of codegen. The testcase shows a particular nasty example result of that where we would fail to properly align an alloca. Differential Revision: https://reviews.llvm.org/D32622 llvm-svn: 302303
* [CodeView] Reserve TypeDatabase records up front.Zachary Turner2017-05-052-1/+6
| | | | | | | | | | | | | Most of the time we know exactly how many type records we have in a list, and we want to use the visitor to deserialize them into actual records in a database. Previously we were just using push_back() every time without reserving the space up front in the vector. This is obviously terrible from a performance standpoint, and it's not uncommon to have PDB files with half a million type records, where the performance degredation was quite noticeable. llvm-svn: 302302
* [AMDGPU] In the new waitcnt insertion pass, use getHeader Kannan Narayanan2017-05-051-5/+5
| | | | | | | | instead of getTopBlock to find the loop header. Differential Revision: https://reviews.llvm.org/D32831 llvm-svn: 302290
* MIParser/MIRPrinter: Compute block successors if not explicitely specifiedMatthias Braun2017-05-054-44/+107
| | | | | | | | | | | | | | | | | - MIParser: If the successor list is not specified successors will be added based on basic block operands in the block and possible fallthrough. - MIRPrinter: Adds a new `simplify-mir` option, with that option set: Skip printing of block successor lists in cases where the parser is guaranteed to reconstruct it. This means we still print the list if some successor cannot be determined (happens for example for jump tables), if the successor order changes or branch probabilities being unequal. Differential Revision: https://reviews.llvm.org/D31262 llvm-svn: 302289
* [X86] Use SDValue::getConstantOperandVal helper. NFCI.Simon Pilgrim2017-05-051-9/+6
| | | | llvm-svn: 302286
* TargetLibraryInfo: Introduce wcslenMatthias Braun2017-05-052-0/+5
| | | | | | | | | | | wcslen is part of the C99 and C++98 standards. - This introduces the function to TargetLibraryInfo. - Also set attributes for wcslen in llvm::inferLibFuncAttributes(). Differential Revision: https://reviews.llvm.org/D32837 llvm-svn: 302278
* AMDGPU/AMDHSA: Set COMPUTE_PGM_RSRC2:LDS_SIZE to 0Konstantin Zhuravlyov2017-05-051-1/+2
| | | | | | | | This field is populated by the CP Differential Revision: https://reviews.llvm.org/D32619 llvm-svn: 302277
* Simplify dbg.value handling in SDISel with early returnsReid Kleckner2017-05-051-35/+23
| | | | | | | | | | | | | | No functional change other than improving dbgs logging accuracy on constant dbg values. Previously we would add things like "i32 42" as debug values, and then log that we were dropping the debug info, which is silly. Delete some dead code that was checking for static allocas. This remained after r207165, but served no purpose. Currently, static alloca dbg.values are always sent through the DanglingDebugInfoMap, and are usually made valid the first time the alloca is used. llvm-svn: 302267
* [WebAssembly] Add ObjectYAML support for wasm name sectionSam Clegg2017-05-051-1/+11
| | | | | | Differential Revision: https://reviews.llvm.org/D32841 llvm-svn: 302266
* [bpf] fix a bug which causes incorrect big endian reloc fixupAlexei Starovoitov2017-05-051-1/+1
| | | | | | | | o Add bpfeb support in BPF dwarfdump unit test case Signed-off-by: Yonghong Song <yhs@fb.com> Signed-off-by: Alexei Starovoitov <ast@fb.com> llvm-svn: 302265
* If posix_fallocate returns EOPNOTSUPP, fallback to ftruncate.Joerg Sonnenberger2017-05-051-4/+5
| | | | | | This can happen at least on NetBSD. llvm-svn: 302263
* [KnownBits] Add wrapper methods for setting and clear all bits in the ↵Craig Topper2017-05-0513-53/+36
| | | | | | | | | | underlying APInts in KnownBits. This adds routines for reseting KnownBits to unknown, making the value all zeros or all ones. It also adds methods for querying if the value is zero, all ones or unknown. Differential Revision: https://reviews.llvm.org/D32637 llvm-svn: 302262
* [Float2Int] Replace a ConstantRange copy with a move. Remove an extra call ↵Craig Topper2017-05-051-3/+4
| | | | | | to MapVector::find. llvm-svn: 302256
* fix build on CygwinNuno Lopes2017-05-051-1/+1
| | | | llvm-svn: 302246
* [AArch64] Remove AArch64AddressTypePromotion passJun Bum Lim2017-05-054-505/+0
| | | | | | | | | | | | | | | | Summary: Remove the AArch64AddressTypePromotion pass as we migrated all transformations done in this pass into CGP in r299379. Reviewers: qcolombet, jmolloy, javed.absar, mcrosier Reviewed By: qcolombet Subscribers: aemerson, rengolin, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D31623 llvm-svn: 302245
* [LoopIdiom] check for safety while expandingAditya Kumar2017-05-051-0/+10
| | | | | | | | | Loop Idiom recognition was generating memset in a case that would result generating a division operation to an unsafe location. Differential Revision: https://reviews.llvm.org/D32674 llvm-svn: 302238
* [X86][AVX512] Improve support and testing for CTLZ of 512-bit vectors ↵Simon Pilgrim2017-05-051-3/+7
| | | | | | without CDI llvm-svn: 302233
* [X86] Remove duplicate operation actions. NFCI.Simon Pilgrim2017-05-051-5/+0
| | | | llvm-svn: 302230
* [X86][AVX512CDI] Move v2i64/v4i64 and v4i32/v8i32 VPLZCNT lowering to tablegenSimon Pilgrim2017-05-052-39/+38
| | | | | | Extend NoVLX targets to use the 512-bit versions llvm-svn: 302229
* Remove stale live-ins in the branch folderKrzysztof Parzyszek2017-05-051-12/+22
| | | | | | | | | | | Hoisting common code can cause registers that live-in in the successor blocks to no longer be live-in. The live-in information needs to be updated to reflect this, or otherwise incorrect code can be generated later on. Differential Revision: https://reviews.llvm.org/D32661 llvm-svn: 302228
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