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* [RuntimeDyld] Adds the necessary hooks to MCJIT to be able to debug generatedLang Hames2014-06-253-10/+129
| | | | | | | | MachO files using the GDB JIT debugging interface. Patch by Keno Fischer. Thanks Keno! llvm-svn: 211652
* Simplify the handling of .cfi_endproc.Rafael Espindola2014-06-255-24/+9
| | | | | | No functionality change. llvm-svn: 211651
* Simplify EmitLabel.Rafael Espindola2014-06-242-6/+1
| | | | | | | All the "real" streamers were already calling to MCStreamer::EmitLabel to do part of the work. llvm-svn: 211646
* [FastISel][X86] Fold XALU condition into branch and compare.Juergen Ributzka2014-06-241-0/+150
| | | | | | | Optimize the codegen of select and branch instructions to directly use the EFLAGS from the {s|u}{add|sub|mul}.with.overflow intrinsics. llvm-svn: 211645
* R600/SI: Use a ComplexPattern for MUBUF storesTom Stellard2014-06-243-36/+67
| | | | | | | | Now that non-leaf ComplexPatterns are allowed we can fold all the MUBUF store patterns into the instruction definition. We will also be able to reuse this new ComplexPattern for MUBUF loads and atomic operations. llvm-svn: 211644
* R600: Promote i64 stores to v2i32Tom Stellard2014-06-243-3/+10
| | | | | | Now we need only one 64-bit pattern for stores. llvm-svn: 211643
* Print a=b as an assignment.Rafael Espindola2014-06-2411-42/+13
| | | | | | | | | | | In assembly the expression a=b is parsed as an assignment, so it should be printed as one. This remove a truly horrible hack for producing a label with "a=.". It would be used by codegen but would never be reached by the asm parser. Sorry I missed this when it was first committed. llvm-svn: 211639
* R600: Fix inconsistency in rsq instructions.Matt Arsenault2014-06-248-14/+55
| | | | | | | | | | | | | R600 was using a clamped version of rsq, but SI was not. Add a new rsq_clamped intrinsic and use them consistently. It's unclear to me from the documentation what behavior the R600 instructions have, so I assume they have the legacy behavior described by the SI documents. For R600, use RECIPSQRT_IEEE for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also has RECIPSQRT_FF, which I'm not sure how it fits in here. llvm-svn: 211637
* fixed a few typos in commentsSanjay Patel2014-06-242-14/+12
| | | | llvm-svn: 211634
* [PPC64] Fix PR20071 (fctiduz generated for targets lacking that instruction)Bill Schmidt2014-06-241-0/+4
| | | | | | | | | | | | | | | | | PR20071 identifies a problem in PowerPC's fast-isel implementation for floating-point conversion to integer. The fctiduz instruction was added in Power ISA 2.06 (i.e., Power7 and later). However, this instruction is being generated regardless of which 64-bit PowerPC target is selected. The intent is for fast-isel to punt to DAG selection when this instruction is not available. This patch implements that change. For testing purposes, the existing fast-isel-conversion.ll test adds a RUN line for -mcpu=970 and tests for the expected code generation. Additionally, the existing test fast-isel-conversion-p5.ll was found to be incorrectly expecting the unavailable instruction to be generated. I've removed these test variants since we have adequate coverage in fast-isel-conversion.ll. llvm-svn: 211627
* vpblend intrinsics combines as shifts intrinsics due to absence return stmt ↵Robert Khasanov2014-06-241-0/+2
| | | | | | | | | | between them Fix PR20088 Differential Revision: http://reviews.llvm.org/D4277 llvm-svn: 211617
* R600: Remove DIV_INFMatt Arsenault2014-06-242-3/+2
| | | | | | | This corresponded to an amdil instruction which there is a 2 instruction equivalent for. llvm-svn: 211616
* R600/SI: Move pattern to instruction definitionMatt Arsenault2014-06-241-6/+1
| | | | llvm-svn: 211614
* Add new debug kind LocTrackingOnly.Diego Novillo2014-06-241-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This new debug emission kind supports emitting line location information in all instructions, but stops code generation from emitting debug info to the final output. This mode is useful when the backend wants to track source locations during code generation, but it does not want to produce debug info. This is currently used by optimization remarks (-pass-remarks, -pass-remarks-missed and -pass-remarks-analysis). To prevent debug info emission, DIBuilder never inserts the annotation 'llvm.dbg.cu' when LocTrackingOnly is enabled. Reviewers: echristo, dblaikie Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D4234 llvm-svn: 211609
* Resubmit commit r211533Weiming Zhao2014-06-243-1/+95
| | | | | | | "Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64" Missed files are added in this commit. llvm-svn: 211605
* CodeGen: Avoid multiple strlen callsDavid Majnemer2014-06-241-5/+4
| | | | | | | Use a StringRef to hold our section prefix. This avoids multiple calls to strlen. llvm-svn: 211602
* ARM: Fix TPsoft for Thumb modeChristian Pirker2014-06-242-5/+13
| | | | | | Reviewed at http://reviews.llvm.org/D4230 llvm-svn: 211601
* Replace two release calls with std::move. I missed this on the previous commit.Rafael Espindola2014-06-241-2/+2
| | | | llvm-svn: 211597
* Pass a unique_ptr<MemoryBuffer> to the constructors in the Binary hierarchy.Rafael Espindola2014-06-2410-68/+78
| | | | | | | Once the objects are constructed, they own the buffer. Passing a unique_ptr makes that clear. llvm-svn: 211595
* Revert: r211588 - [mips] Use __clear_cache builtin instead of cacheflush() ↵Daniel Sanders2014-06-241-2/+10
| | | | | | | | | | | | in Unix Memory::InvalidateInstructionCache() Buildbot reports a test failure on the llvm-mips-linux builder and blames r211588. Although it doesn't appear in the blamelist, it seems it could also be r211587 (because it's committed to compiler-rt?) since they were tested together. Reverting the most likely suspect (r211588) to confirm one way or the other. llvm-svn: 211594
* Revert r211287, "Remove support for LLVM runtime multi-threading."NAKAMURA Takumi2014-06-242-4/+28
| | | | | | libclang still requires it on cygming, lack of incomplete <mutex>. llvm-svn: 211592
* [mips] Added support for assembling sdbbp.Daniel Sanders2014-06-244-7/+47
| | | | | | | | | | Summary: This instruction is re-encoded in MIPS32r6/MIPS64r6 without changing the restrictions. We hadn't implemented it for earlier ISA's so it has been added to those too. Differential Revision: http://reviews.llvm.org/D4265 llvm-svn: 211590
* [mips] Use __clear_cache builtin instead of cacheflush() in Unix ↵Daniel Sanders2014-06-241-10/+2
| | | | | | | | | | Memory::InvalidateInstructionCache() MIPS64 Android bionic has removed cacheflush(). Use __clear_cache() instead for 32-bit and 64-bit MIPS Patch by Duane Sand <Duane.Sand@imgtec.com> llvm-svn: 211588
* InstCombine: Disable umul.with.overflow recognition for vectors.Benjamin Kramer2014-06-241-1/+5
| | | | | | It doesn't make a lot on most targets and the code isn't ready for it. PR20113. llvm-svn: 211583
* InstCombine: Don't try to reorder shuffles where the mask is a ConstantExpr.Benjamin Kramer2014-06-241-1/+3
| | | | | | We can't analyze the individual values of a vector expression. PR20114. llvm-svn: 211581
* GlobalOpt: Don't optimize dllimport for initializersDavid Majnemer2014-06-241-6/+7
| | | | | | | | | Referencing a dllimport variable requires actually instructions, not just a relocation. This fixes PR19955. Differential Revision: http://reviews.llvm.org/D4249 llvm-svn: 211571
* [AArch64] Fix a build_vector pattern match failKevin Qin2014-06-241-24/+25
| | | | | | caused by defect in isBuildVectorAllZeros(). llvm-svn: 211567
* [Disasm][AVX512] Implement decoding of top bit for non-destructive reg fieldsAdam Nemet2014-06-241-1/+2
| | | | | | | | | V' bit in the P2 byte of the EVEX prefix provides the top bit of the NDD and NDS register fields. This was simply not used in the decoder until now. Fixes <rdar://problem/17402661> llvm-svn: 211565
* Support: Move class ScaledNumberDuncan P. N. Exon Smith2014-06-242-190/+187
| | | | | | | | ScaledNumber has been cleaned up enough to pull out of BFI now. Still work to do there (tests for shifting, bloated printing code, etc.), but it seems clean enough for its new home. llvm-svn: 211562
* BFI: Un-floatify more languageDuncan P. N. Exon Smith2014-06-241-23/+24
| | | | llvm-svn: 211561
* Support: Extract ScaledNumbers::MinScale and MaxScaleDuncan P. N. Exon Smith2014-06-241-10/+5
| | | | llvm-svn: 211558
* BFI: Change language from "exponent" to "scale"Duncan P. N. Exon Smith2014-06-231-8/+8
| | | | llvm-svn: 211557
* BFI: Rename UnsignedFloat => ScaledNumberDuncan P. N. Exon Smith2014-06-231-17/+17
| | | | | | | A lot of the docs and API are out of date, but I'll leave that for a separate commit. llvm-svn: 211555
* Pass a std::unique_ptr& to the create??? methods is lib/Object.Rafael Espindola2014-06-239-36/+46
| | | | | | | | This makes the buffer ownership on error conditions very natural. The buffer is only moved out of the argument if an object is constructed that now owns the buffer. llvm-svn: 211546
* [FastISel][X86] Lower unsupported selects to control-flow.Juergen Ributzka2014-06-231-0/+71
| | | | | | | | The extends the select lowering coverage by emiting pseudo cmov instructions. These insturction will be later on lowered to control-flow to simulate the select. llvm-svn: 211545
* [FastISel][X86] Add support for floating-point select.Juergen Ributzka2014-06-231-0/+128
| | | | | | | | | | This extends the select lowering to support floating-point selects. The lowering depends on SSE instructions and that the conditon comes from a floating-point compare. Under this conditions it is possible to emit an optimized instruction sequence that doesn't require any branches to simulate the select. llvm-svn: 211544
* [FastISel][X86] Optimize selects when the condition comes from a compare.Juergen Ributzka2014-06-233-37/+152
| | | | | | | Optimize the select instructions sequence to use the EFLAGS directly from a compare when possible. llvm-svn: 211543
* Make ObjectFile and BitcodeReader always own the MemoryBuffer.Rafael Espindola2014-06-2311-121/+91
| | | | | | | | | | This allows us to just use a std::unique_ptr to store the pointer to the buffer. The flip side is that they have to support releasing the buffer back to the caller. Overall this looks like a more efficient and less brittle api. llvm-svn: 211542
* This reverts commit r211533 and r211539.Rafael Espindola2014-06-231-54/+1
| | | | | | | | | Revert "Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64" Revert "Fix cmake build." It was missing a file. llvm-svn: 211540
* Fix cmake build.Juergen Ributzka2014-06-231-1/+0
| | | | llvm-svn: 211539
* Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64Weiming Zhao2014-06-232-1/+55
| | | | | | | | | | | | | | | | | | | This patch is based on the changes from ARM target [1,2] Based on ARM doc [3], if the literal value can be loaded with a valid MOV, it can emit that instruction. This is implemented in this patch. [1] Fix PR18345: ldr= pseudo instruction produces incorrect code when using in inline assembly Author: David Peixotto <dpeixott@codeaurora.org> commit b92cca222898d87bbc764fa22e805adb04ef7f13 (r200777) [2] Implement the ldr-pseudo opcode for ARM assembly Author: David Peixotto <dpeixott@codeaurora.org> commit 0fa193b08627927ccaa0804a34d80480894614b8 (r197708) [3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/CJAHAIBC.html Differential Revision: http://reviews.llvm.org/D4163 llvm-svn: 211533
* Convert a few methods to use ErrorOr.Rafael Espindola2014-06-231-10/+6
| | | | | | | It used to be inconvenient to mix ErrorOr and UniquePtr, but with c++11 they work OK together. llvm-svn: 211532
* [Mips] Add a target streamer when creating a null streamer.Rafael Espindola2014-06-233-33/+70
| | | | | | Should fix DebugInfo/global.ll on the mips bot. llvm-svn: 211527
* Recommit 211309 (StringMap::insert), reverted in 211328 due to issues with ↵David Blaikie2014-06-231-2/+8
| | | | | | | | | | | | private, but non-deleted, move members. Certain versions of GCC (~4.7) couldn't handle the SFINAE on access control, but with "= delete" (hidden behind a macro for portability) this issue is worked around/addressed. Patch by Agustín Bergé llvm-svn: 211525
* R600/SI: Verify restrictions on div_scale operands.Matt Arsenault2014-06-231-0/+35
| | | | llvm-svn: 211524
* R600/SI: Fix div_scale intrinsic.Matt Arsenault2014-06-234-4/+62
| | | | | | | The operand that must match one of the others does matter, and implement selecting for it. llvm-svn: 211523
* ARMEB: Vector extend operationsChristian Pirker2014-06-232-20/+150
| | | | | | Reviewed at http://reviews.llvm.org/D4043 llvm-svn: 211520
* R600: Remove AMDILISelLoweringMatt Arsenault2014-06-236-48/+13
| | | | llvm-svn: 211519
* R600: Select is not expensive.Matt Arsenault2014-06-231-0/+7
| | | | llvm-svn: 211518
* R600: Move add/sub with overflow out of AMDILISelLoweringMatt Arsenault2014-06-233-19/+12
| | | | | | Add more tests for these. llvm-svn: 211517
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