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* Clean up language and grammar.Eric Christopher2014-05-207-8/+8
| | | | | | | Based on a patch by jfcaron3@gmail.com! PR19806 llvm-svn: 209216
* Temporarily revert: r209129 - [mips][mips64r6] Sorted *_ENC, *_DESC classes ↵Daniel Sanders2014-05-201-124/+117
| | | | | | | | | | | | and tests After discussion with Zoran, we have decided to temporarily revert this commit. It's causing some difficult to resolve conflicts and we are under time pressure to deliver an initial MIPS64r6 compiler. We will re-apply an equivalent patch once the time pressure has passed. llvm-svn: 209211
* TableGen: permit non-leaf ComplexPattern usesTim Northover2014-05-201-6/+8
| | | | | | | | | | | | | | | | | | This allows the results of a ComplexPattern check to be distributed to separate named Operands, instead of the current system where all results must apply (and match perfectly) with a single Operand. For example, if "some_addrmode" is a ComplexPattern producing two results, you can write: def : Pat<(load (some_addrmode GPR64:$base, imm:$offset)), (INST GPR64:$base, imm:$offset)>; This should allow neater instruction definitions in TableGen that don't put all possible aspects of addressing into a single operand, but are still usable with relatively simple C++ CodeGen idioms. llvm-svn: 209206
* Add parentheses to suppress the gcc warning '-Wparentheses'.Simon Atanasyan2014-05-201-2/+2
| | | | | | No functional changes. llvm-svn: 209203
* Legalizer: Make bswap promotion safe for vectors.Benjamin Kramer2014-05-201-2/+2
| | | | llvm-svn: 209202
* [Mips] Add more relocation types and MIPS specific e_flags constants.Simon Atanasyan2014-05-202-0/+21
| | | | llvm-svn: 209201
* ARMEB: Additional test files for ARM fixupsChristian Pirker2014-05-201-1/+4
| | | | llvm-svn: 209200
* TableGen: convert InstAlias's Emit bit to an int.Tim Northover2014-05-202-68/+65
| | | | | | | | | | | | | When multiple aliases overlap, the correct string to print can often be determined purely by considering the InstAlias declarations in some particular order. This allows the user to specify that order manually when desired, without resorting to hacking around with the default lexicographical order on Record instantiation, which is error-prone and ugly. I was also mistaken about "add w2, w3, w4" being the same as "add w2, w3, w4, uxtw". That's only true if Rn is the stack pointer. llvm-svn: 209199
* [X86] Tune LEA usage for SilvermontAlexey Volkov2014-05-207-14/+102
| | | | | | | | | | | | | According to Intel Software Optimization Manual on Silvermont in some cases LEA is better to be replaced with ADD instructions: "The rule of thumb for ADDs and LEAs is that it is justified to use LEA with a valid index and/or displacement for non-destructive destination purposes (especially useful for stack offset cases), or to use a SCALE. Otherwise, ADD(s) are preferable." Differential Revision: http://reviews.llvm.org/D3826 llvm-svn: 209198
* [LV][REFACTOR] One more tiny fix for printing debug locations in loop ↵Zinovy Nis2014-05-201-10/+8
| | | | | | | | vectorizer. Now consistent with the remarks emitter. Differential Revision: http://reviews.llvm.org/D3821 llvm-svn: 209197
* Teach isKnownNonNull that a nonnull return is not null. Add a test for this ↵Nick Lewycky2014-05-201-0/+5
| | | | | | case as well as the case of a nonnull attribute (already handled but not tested). llvm-svn: 209193
* DebugInfo: Emit function definitions within their namespace scope.David Blaikie2014-05-201-22/+0
| | | | | | | | This workaround (presumably for ancient GDB) doesn't appear to be required (GDB 7.5 seems to tolerate function definition DIEs in namespace scope just fine). llvm-svn: 209189
* Add 'nonnull', a new parameter and return attribute which indicates that the ↵Nick Lewycky2014-05-208-2/+23
| | | | | | pointer is not null. Instcombine will elide comparisons between these and null. Patch by Luqman Aden! llvm-svn: 209185
* DebugInfo: Assume all subprogram DIEs have been created before any abstract ↵David Blaikie2014-05-191-5/+5
| | | | | | | | | | | | | | subprograms are constructed. Since we visit the whole list of subprograms for each CU at module start, this is clearly true - don't test for the case, just assert it. A few old test cases seemed to have incomplete subprogram lists, but any attempt to reproduce them shows full subprogram lists that even include entities that have been completely inlined and the out of line definition removed. llvm-svn: 209178
* [ARM64] Adds Cortex-A53 scheduling support for vector load/store post.Chad Rosier2014-05-194-60/+152
| | | | | | | Patch by Dave Estes<cestes@codeaurora.org>! PR19761 http://reviews.llvm.org/D3829 llvm-svn: 209176
* Remove unused method declarationMatt Arsenault2014-05-191-1/+0
| | | | llvm-svn: 209174
* DebugInfo: Don't include DW_AT_inline on each abstract definition multiple ↵David Blaikie2014-05-191-1/+0
| | | | | | | | | | | | | | | | | times. When I refactored this in r208636 I accidentally caused this to be added multiple times to each abstract subprogram (not accounting for the deduplicating effect of the InlinedSubprogramDIEs set). This got better in r208798 when the abstract definitions got the attribute added to them at construction time, but still had the redundant copies introduced in r208636. This commit removes those excess DW_AT_inlines and relies solely on the insertion in r208798. llvm-svn: 209166
* DebugInfo: Fix missing inlined_subroutines caused by r208748.David Blaikie2014-05-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The check in DwarfDebug::constructScopeDIE was meant to consider inlined subroutines as any non-top-level scope that was a subprogram. Instead of checking "not top level scope" it was checking if the /subprogram's/ scope was non-top-level. Fix this and beef up a test case to demonstrate some of the missing inlined_subroutines are no longer missing. In the course of fixing this I also found that r208748 (with this fix) found one /extra/ inlined_subroutine in concrete_out_of_line.ll due to two inlined_subroutines having the same inlinedAt location. The previous implementation was collapsing these into a single inlined subroutine. I'm not sure what the original code was that created this .ll file so I'm not sure if this actually happens in practice today. Since we deliberately include column information to disambiguate two calls on the same line, that may've addressed this bug in the frontend, but it's good to know that workaround isn't necessary for this particular case anymore. llvm-svn: 209165
* Fix typos.Eric Christopher2014-05-191-1/+2
| | | | llvm-svn: 209164
* [ConstantHoisting][X86] Change the cost model to never hoist constants for ↵Juergen Ributzka2014-05-191-2/+13
| | | | | | | | | | | | | | | types larger than i128. Currently the X86 backend doesn't support types larger than i128 very well. For example an i192 multiply will assert in codegen when the 2nd argument is a constant and the constant got hoisted. This fix changes the cost model to never hoist constants for types larger than i128. Once the codegen issues have been resolved, the cost model can be updated to allow also larger types. This is related to <rdar://problem/16954938> llvm-svn: 209162
* [X86] Add ISel patterns to improve the selection of TZCNT and LZCNT.Andrea Di Biagio2014-05-191-0/+81
| | | | | | | | | | Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
* Implement MachOObjectFile::isSectionData() and MachOObjectFile::isSectionBSSKevin Enderby2014-05-191-6/+12
| | | | | | | | so that llvm-size will total up all the sections in the Berkeley format. This allows for rough categorizations for Mach-O sections. And allows the total of llvm-size’s Berkeley and System V formats to be the same. llvm-svn: 209158
* Added more insertps optimizationsFilipe Cabecinhas2014-05-192-11/+72
| | | | | | | | | | | | | | | | | | | | Summary: When inserting an element that's coming from a vector load or a broadcast of a vector (or scalar) load, combine the load into the insertps instruction. Added PerformINSERTPSCombine for the case where we need to fix the load (load of a vector + insertps with a non-zero CountS). Added patterns for the broadcasts. Also added tests for SSE4.1, AVX, and AVX2. Reviewers: delena, nadav, craig.topper Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3581 llvm-svn: 209156
* [RuntimeDyld] Fix x86-64 MachO GOT relocation handling.Lang Hames2014-05-191-2/+7
| | | | | | | | | | | For GOT relocations the addend should modify the offset to the GOT entry, not the value of the entry itself. Teach RuntimeDyldMachO to do The Right Thing here. Fixes <rdar://problem/16961886>. llvm-svn: 209154
* Check the alwaysinline attribute on the call as well as on the caller.Peter Collingbourne2014-05-192-3/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D3815 llvm-svn: 209150
* Use range forMatt Arsenault2014-05-191-4/+1
| | | | llvm-svn: 209147
* reverting r209132Jyotsna Verma2014-05-192-121/+250
| | | | llvm-svn: 209139
* MemoryBuffer: Use GetNativeSystemInfo()Alp Toker2014-05-192-17/+6
| | | | | | | Removes old 4096 byte workaround. This functionality has been available since Windows XP. llvm-svn: 209137
* Revert "Patch for function cloning to inline all blocks whose address is taken"Eric Christopher2014-05-191-106/+34
| | | | | | | | as it was causing build failures in ruby. This reverts commit r207713. llvm-svn: 209135
* [ARM64] Split tbz/tbnz into W/X register variantBradley Smith2014-05-198-64/+144
| | | | llvm-svn: 209134
* Hexagon: Add encoding bits to the mpy instructions.Jyotsna Verma2014-05-192-250/+121
| | | | llvm-svn: 209132
* [mips][mips64r6] Sorted *_ENC, *_DESC classes and testsZoran Jovanovic2014-05-191-117/+124
| | | | | | Differential Revision: http://reviews.llvm.org/D3808 llvm-svn: 209129
* Resolving MSVC warnings about switch statements with a default label, but no ↵Aaron Ballman2014-05-192-11/+6
| | | | | | case labels. No functional changes intended. llvm-svn: 209126
* SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the ↵Benjamin Kramer2014-05-196-1/+51
| | | | | | | | | | bswap not. - On ARM/ARM64 we get a vrev because the shuffle matching code is really smart. We still unroll anything that's not v4i32 though. - On X86 we get a pshufb with SSSE3. Required more cleverness in isShuffleMaskLegal. - On PPC we get a vperm for v8i16 and v4i32. v2i64 is unrolled. llvm-svn: 209123
* Added inst-combine for 'MIN(MIN(A, 97), 23)' and 'MAX(MAX(A, 23), 97)'Dinesh Dwivedi2014-05-191-5/+13
| | | | | | | | | | | This removes TODO added in r208849 [http://reviews.llvm.org/D3629] MIN(MIN(A, 97), 23) -> MIN(A, 23) MAX(MAX(A, 23), 97) -> MAX(A, 97) Differential Revision: http://reviews.llvm.org/D3785 llvm-svn: 209110
* Remove last uses of OwningPtr from llvm. As far as I can tell these method ↵Craig Topper2014-05-183-80/+0
| | | | | | versions are not used by lldb, lld, or clang. llvm-svn: 209103
* ARM: make libcall setup more table drivenSaleem Abdulrasool2014-05-181-161/+100
| | | | | | | | | Rather than create a series of function calls to setup the library calls, create a table with the information and just use the table to drive the configuration of the library calls. This makes it easier to both inspect the list as well as to modify it. NFC. llvm-svn: 209089
* Options: Use erase_if to remove Args from the list.Benjamin Kramer2014-05-181-8/+3
| | | | | | | While there make getOption return a const reference so we don't have to put it on the stack when calling methods on it. No functionality change. llvm-svn: 209088
* ARM: improve WoA ABI conformance for frame registerSaleem Abdulrasool2014-05-181-3/+7
| | | | | | | | | Windows on ARM uses R11 for the frame pointer even though the environment is a pure Thumb-2, thumb-only environment. Replicate this behaviour to improve Windows ABI compatibility. This register is used for fast stack walking, and thus is part of the Windows ABI. llvm-svn: 209085
* ARM: consolidate frame pointer register knowledgeSaleem Abdulrasool2014-05-181-3/+5
| | | | | | | | | | | Use the ARMBaseRegisterInfo to query the frame register. The base register info is aware of the frame register that is used for the frame pointer. Use that to determine the frame register rather than duplicating the knowledge. Although, the code path is slightly different in that it may return SP, that can only occur if the frame pointer has been omitted in the machine function, which is supposed to contain the desired value in that case. llvm-svn: 209084
* Target: remove old constructors for CallLoweringInfoSaleem Abdulrasool2014-05-1718-228/+190
| | | | | | | | | | This is mostly a mechanical change changing all the call sites to the newer chained-function construction pattern. This removes the horrible 15-parameter constructor for the CallLoweringInfo in favour of setting properties of the call via chained functions. No functional change beyond the removal of the old constructors are intended. llvm-svn: 209082
* Target: change member from reference to pointerSaleem Abdulrasool2014-05-175-7/+7
| | | | | | | | | This is a preliminary step to help ease the construction of CallLoweringInfo. Changing the construction to a chained function pattern requires that the parameter be nullable. However, rather than copying the vector, save a pointer rather than the reference to permit a late binding of the arguments. llvm-svn: 209080
* ARM: whitespaceSaleem Abdulrasool2014-05-171-3/+3
| | | | | | Remove some whitespace. NFC. llvm-svn: 209079
* Use create methods since msvc doesn't handle delegating constructors.Rafael Espindola2014-05-177-29/+43
| | | | llvm-svn: 209076
* Handle ConstantAggregateZero when upgrading global_ctors.Rafael Espindola2014-05-171-6/+9
| | | | llvm-svn: 209075
* Reduce abuse of default values in the GlobalAlias constructor.Rafael Espindola2014-05-177-18/+33
| | | | | | This is in preparation for adding an optional offset. llvm-svn: 209073
* Revert r209049 and r209065, "Add support for combining GEPs across PHI nodes"NAKAMURA Takumi2014-05-171-66/+0
| | | | | | It broke clang selfhosting even after r209065. llvm-svn: 209067
* Fix for sanitizer crash introduced in r209049Louis Gerbarg2014-05-171-1/+8
| | | | | | | | | | This patch fixes 3 issues introduced by r209049 that only showed up in on the sanitizer buildbots. One was a typo in a compare. The other is a check to confirm that the single differing value in the two incoming GEPs is the same type. The final issue was the the IRBuilder under some circumstances would build PHIs in the middle of the block. llvm-svn: 209065
* Target: Replace getSection().empty() with hasSection()David Majnemer2014-05-171-1/+1
| | | | | | No functional change, just a small cleanup. llvm-svn: 209064
* ARM: use the proper target object format for WoASaleem Abdulrasool2014-05-171-1/+2
| | | | | | | | WoA uses COFF, not ELF. ARMISelLowering::createTLOF would previously return ELF for any non-MachO platform. This was a missed site when the original change for target format support for Windows on ARM was done. llvm-svn: 209057
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