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* [X86] Remove unnecessary peakThroughBitcasts call that's already take care ↵Craig Topper2017-01-241-2/+0
| | | | | | of by the ISD::isBuildVectorAllOnes check below. llvm-svn: 292894
* AMDGPU : Add trap handler support.Wei Ding2017-01-243-20/+33
| | | | llvm-svn: 292893
* [AVX-512] Simplify multiclasses for integer logic operations. There were ↵Craig Topper2017-01-241-35/+23
| | | | | | | | several inputs that didn't vary. While there give them the same scheduling itinerary as the SSE/AVX versions. llvm-svn: 292892
* Make VerifyDomInfo and VerifyLoopInfo global variablesSerge Pavlov2017-01-242-4/+4
| | | | | | | | | | | | | | | Verifications of dominator tree and loop info are expensive operations so they are disabled by default. They can be enabled by command line options -verify-dom-info and -verify-loop-info. These options however enable checks only in files Dominators.cpp and LoopInfo.cpp. If some transformation changes dominaror tree and/or loop info, it would be convenient to place similar checks to the files implementing the transformation. This change makes corresponding flags global, so they can be used in any file to optionally turn verification on. llvm-svn: 292889
* [SystemZ] Gracefully fail in GeneralShuffle::add() instead of assertion.Jonas Paulsson2017-01-241-12/+22
| | | | | | | | | | | | | | The GeneralShuffle::add() method used to have an assert that made sure that source elements were at least as big as the destination elements. This was wrong, since it is actually expected that an EXTRACT_VECTOR_ELT node with a smaller source element type than the return type gets extended. Therefore, instead of asserting this, it is just checked and if this is the case 'false' is returned from the GeneralShuffle::add() method. This case should be very rare and is not handled further by the backend. Review: Ulrich Weigand. llvm-svn: 292888
* [X86] Don't split v8i32 all ones values if only AVX1 is available. Keep it ↵Craig Topper2017-01-242-23/+13
| | | | | | | | intact and split it at isel. This allows us to remove the check in ANDN combining that had to look through the extraction. llvm-svn: 292881
* [X86] Remove Undef handling from extractSubVector. This is now handled ↵Craig Topper2017-01-241-4/+0
| | | | | | inside getNode. llvm-svn: 292877
* [SelectionDAG] Teach getNode to simplify a couple easy cases of ↵Craig Topper2017-01-241-0/+13
| | | | | | | | | | | | | | | | | | | | | EXTRACT_SUBVECTOR Summary: This teaches getNode to simplify extracting from Undef. This is similar to what is done for EXTRACT_VECTOR_ELT. It also adds support for extracting from CONCAT_VECTOR when we can reuse one of the inputs to the concat. These seem like simple non-target specific optimizations. For X86 we currently handle undef in extractSubvector, but not all EXTRACT_SUBVECTOR creations go through there. Ultimately, my motivation here is to simplify extractSubvector and remove custom lowering for EXTRACT_SUBVECTOR since we don't do anything but handle undef and BUILD_VECTOR optimizations, but those should be DAG combines. Reviewers: RKSimon, delena Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29000 llvm-svn: 292876
* [APInt] Remove calls to clearUnusedBits from XorSlowCase and operator^=Craig Topper2017-01-241-6/+2
| | | | | | | | | | | | | | | | | Summary: There's a comment in XorSlowCase that says "0^0==1" which isn't true. 0 xored with 0 is still 0. So I don't think we need to clear any unused bits here. Now there is no difference between XorSlowCase and AndSlowCase/OrSlowCase other than the operation being performed Reviewers: majnemer, MatzeB, chandlerc, bkramer Reviewed By: MatzeB Subscribers: chfast, llvm-commits Differential Revision: https://reviews.llvm.org/D28986 llvm-svn: 292873
* LiveIntervalAnalysis: Calculate liveness even if a superreg is reserved.Matthias Braun2017-01-241-6/+13
| | | | | | | | | | | | | | | | | A register unit may be allocatable and non-reserved but some of the register(tuples) built with it are reserved. We still need to calculate liveness in this case. Note to out of tree targets: If you start seeing machine verifier errors with this commit, it probably means that you do not properly mark super registers of reserved register as reserved. See for example r292836 or r292870 for example on how to fix that. rdar://29996737 Differential Revision: https://reviews.llvm.org/D28881 llvm-svn: 292871
* PowerPC: Mark super regs of reserved regs reserved.Matthias Braun2017-01-241-35/+25
| | | | | | | | | | | | | | When a register like R1 is reserved, X1 should be reserved as well. This was already done "manually" when 64bit code was enabled, however using the markSuperRegs() function on the base register is more convenient and allows to use the checksAllSuperRegsMarked() function even in 32bit mode to avoid accidental breakage in the future. This is also necessary to allow https://reviews.llvm.org/D28881 Differential Revision: https://reviews.llvm.org/D29056 llvm-svn: 292870
* [LTO] Teach lib/LTO about the new pass manager.Davide Italiano2017-01-241-4/+66
| | | | | | Differential Revision: https://reviews.llvm.org/D28997 llvm-svn: 292864
* [PM] Flesh out the new pass manager LTO pipeline.Davide Italiano2017-01-241-5/+158
| | | | | | Differential Revision: https://reviews.llvm.org/D28996 llvm-svn: 292863
* [sanitizer-coverage] emit __sanitizer_cov_trace_pc_guard w/o a preceding ↵Kostya Serebryany2017-01-241-1/+1
| | | | | | 'if' by default. Update the docs, also add deprecation notes around other parts of sanitizer coverage llvm-svn: 292862
* [APFloat] Add PPCDoubleDouble multiplicationTim Shen2017-01-241-6/+83
| | | | | | | | | | Reviewers: echristo, hfinkel, kbarton, iteratee Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D28382 llvm-svn: 292860
* [WebAssembly] Update LibFunc::Func -> LibFuncDerek Schuff2017-01-242-2/+2
| | | | | | Fixes compile failures after r292848 llvm-svn: 292857
* SimplifyLibCalls: Replace more unary libcalls with intrinsicsMatt Arsenault2017-01-233-30/+37
| | | | llvm-svn: 292855
* [LoopUnroll] First form LCSSA, then loop-simplifyMichael Kuperstein2017-01-231-18/+17
| | | | | | | | | | | | | Running non-LCSSA-preserving LoopSimplify followed by LCSSA on (roughly) the same loop is incorrect, since LoopSimplify may break LCSSA arbitrarily higher in the loop nest. Instead, run LCSSA first, and then run LCSSA-preserving LoopSimplify on the result. This fixes PR31718. Differential Revision: https://reviews.llvm.org/D29055 llvm-svn: 292854
* [AMDGPU] Fix obsolete comments, spotted by Malcolm Parsons. (NFC)Eugene Zelenko2017-01-231-3/+4
| | | | llvm-svn: 292853
* Makes promoteIndirectCall an external function.Dehao Chen2017-01-231-17/+7
| | | | | | | | | | | | | | Summary: promoteIndirectCall should be a utility function that could be invoked by other optimization passes. Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29051 llvm-svn: 292850
* [Analysis] Add LibFunc_ prefix to enums in TargetLibraryInfo. (NFC)David L. Jones2017-01-2319-1322/+1322
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The LibFunc::Func enum holds enumerators named for libc functions. Unfortunately, there are real situations, including libc implementations, where function names are actually macros (musl uses "#define fopen64 fopen", for example; any other transitively visible macro would have similar effects). Strictly speaking, a conforming C++ Standard Library should provide any such macros as functions instead (via <cstdio>). However, there are some "library" functions which are not part of the standard, and thus not subject to this rule (fopen64, for example). So, in order to be both portable and consistent, the enum should not use the bare function names. The old enum naming used a namespace LibFunc and an enum Func, with bare enumerators. This patch changes LibFunc to be an enum with enumerators prefixed with "LibFFunc_". (Unfortunately, a scoped enum is not sufficient to override macros.) There are additional changes required in clang. Reviewers: rsmith Subscribers: mehdi_amini, mzolotukhin, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D28476 llvm-svn: 292848
* AMDGPU: Custom lower more vector operationsMatt Arsenault2017-01-232-0/+105
| | | | | | This avoids stack usage. llvm-svn: 292846
* [RDF] Add registers to live set even if they are live alreadyKrzysztof Parzyszek2017-01-231-6/+5
| | | | | | | | When calculating kills, a register may be considered live because a part of it is live, but if there is a use of that (whole) register, the whole register (and its subregisters) need to be added to the live set. llvm-svn: 292845
* [libFuzzer] mutate empty input using the regular mutators (instead of a ↵Kostya Serebryany2017-01-231-14/+5
| | | | | | custom dummy one). This way when we mutate an empty input there is a chance we will get a dictionary word llvm-svn: 292843
* DAG: Don't fold vector extract into load if target doesn't want toMatt Arsenault2017-01-231-0/+5
| | | | | | | Fixes turning a 32-bit scalar load into an extending vector load for AMDGPU when dynamically indexing a vector. llvm-svn: 292842
* Revert "Refactor SampleProfile.cpp to move computation inside a branch. (NFC)"Evgeniy Stepanov2017-01-231-2/+2
| | | | | | Causes MSan failures on the buildbot. llvm-svn: 292840
* [APFloat] Switch from (PPCDoubleDoubleImpl, IEEEdouble) layout to ↵Tim Shen2017-01-231-79/+320
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (IEEEdouble, IEEEdouble) Summary: This patch changes the layout of DoubleAPFloat, and adjust all operations to do either: 1) (IEEEdouble, IEEEdouble) -> (uint64_t, uint64_t) -> PPCDoubleDoubleImpl, then run the old algorithm. 2) Do the right thing directly. 1) includes multiply, divide, remainder, mod, fusedMultiplyAdd, roundToIntegral, convertFromString, next, convertToInteger, convertFromAPInt, convertFromSignExtendedInteger, convertFromZeroExtendedInteger, convertToHexString, toString, getExactInverse. 2) includes makeZero, makeLargest, makeSmallest, makeSmallestNormalized, compare, bitwiseIsEqual, bitcastToAPInt, isDenormal, isSmallest, isLargest, isInteger, ilogb, scalbn, frexp, hash_value, Profile. I could split this into two patches, e.g. use 1) for all operatoins first, then incrementally change some of them to 2). I didn't do that, because 1) involves code that converts data between PPCDoubleDoubleImpl and (IEEEdouble, IEEEdouble) back and forth, and may pessimize the compiler. Instead, I find easy functions and use approach 2) for them directly. Next step is to implement move multiply and divide from 1) to 2). I don't have plans for other functions in 1). Differential Revision: https://reviews.llvm.org/D27872 llvm-svn: 292839
* AMDGPU: Combine fp16/fp64 subtarget featuresMatt Arsenault2017-01-233-18/+27
| | | | | | | The same control register controls both, and are set to the same defaults. Keep the old names around as aliases. llvm-svn: 292837
* [Hexagon] Explicitly reserve aliases of reserved registersKrzysztof Parzyszek2017-01-232-13/+22
| | | | llvm-svn: 292836
* [libFuzzer] make sure we use the feedback from std::string operator ==Kostya Serebryany2017-01-234-1/+31
| | | | llvm-svn: 292835
* Add support for the x86_thread_state32_t andKevin Enderby2017-01-231-1/+20
| | | | | | | | | | | | | in llvm-objdump for Mach-O files add the printing of the x86_thread_state32_t in the same format as otool-classic(1) on darwin. To do this the 32-bit x86 general tread state needed to be defined in include/llvm/Support/MachO.h . rdar://30110111 llvm-svn: 292829
* [AArch64][GlobalISel] Legalize narrow scalar fp->int conversions.Ahmed Bougacha2017-01-232-3/+16
| | | | | | | | | Since we're now avoiding operations using narrow scalar integer types, we have to legalize the integer side of the FP conversions. This requires teaching the legalizer how to do that. llvm-svn: 292828
* [AArch64][GlobalISel] Legalize narrow scalar ops again.Ahmed Bougacha2017-01-232-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since r279760, we've been marking as legal operations on narrow integer types that have wider legal equivalents (for instance, G_ADD s8). Compared to legalizing these operations, this reduced the amount of extends/truncates required, but was always a weird legalization decision made at selection time. So far, we haven't been able to formalize it in a way that permits the selector generated from SelectionDAG patterns to be sufficient. Using a wide instruction (say, s64), when a narrower instruction exists (s32) would introduce register class incompatibilities (when one narrow generic instruction is selected to the wider variant, but another is selected to the narrower variant). It's also impractical to limit which narrow operations are matched for which instruction, as restricting "narrow selection" to ranges of types clashes with potentially incompatible instruction predicates. Concerns were also raised regarding MIPS64's sign-extended register assumptions, as well as wrapping behavior. See discussions in https://reviews.llvm.org/D26878. Instead, legalize the operations. Should we ever revert to selecting these narrow operations, we should try to represent this more accurately: for instance, by separating a "concrete" type on operations, and an "underlying" type on vregs, we could move the "this narrow-looking op is really legal" decision to the legalizer, and let the selector use the "underlying" vreg type only, which would be guaranteed to map to a register class. In any case, we eventually should mitigate: - the performance impact by selecting no-op extract/truncates to COPYs (which we currently do), and the COPYs to register reuses (which we don't do yet). - the compile-time impact by optimizing away extract/truncate sequences in the legalizer. llvm-svn: 292827
* [ARM] Classification Improvements to ARM Sched-Models. NFCI.Javed Absar2017-01-235-115/+294
| | | | | | | | | | | | | | | | | This is a series of patches to enable adding of machine sched models for ARM processors easier and compact. They define new sched-readwrites for groups of ARM instructions. This has been missing so far, and as a consequence, machine scheduler models for individual sub-targets have tended to be larger than they needed to be. The current patch focuses on floating-point instructions. Reviewers: Diana Picus (rovka), Renato Golin (rengolin) Differential Revision: https://reviews.llvm.org/D28194 llvm-svn: 292825
* Add LC_BUILD_VERSION load commandSteven Wu2017-01-232-0/+55
| | | | | | | | | | | | | | | | | | | Summary: Add a new load command LC_BUILD_VERSION. It is a generic version of LC_*_VERSION_MIN load_command used on Apple platforms. Instead of having a seperate load command for each platform, LC_BUILD_VERSION is recording platform info as an enum. It also records SDK version, min_os, and tools that used to build the binary. rdar://problem/29781291 Reviewers: enderby Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29044 llvm-svn: 292824
* AMDGPU: Propagate fast math flags in fneg combinesMatt Arsenault2017-01-231-3/+3
| | | | | | Can't for fma/mad since it seems they can't have flags currently. llvm-svn: 292818
* AMDGPU: Remove unnecessary checkMatt Arsenault2017-01-231-3/+0
| | | | | | There are no scalar FP types that can be extended. llvm-svn: 292816
* [PGO] add debug option to view annotated cfg after prof use annotationXinliang David Li2017-01-232-2/+36
| | | | | | Differential Revision: http://reviews.llvm.org/D28967 llvm-svn: 292815
* DAG: Allow legalization of fcanonicalize vector typesMatt Arsenault2017-01-231-0/+3
| | | | llvm-svn: 292814
* [libFuzzer] deflake a test Kostya Serebryany2017-01-231-0/+1
| | | | llvm-svn: 292813
* [InstSimplify] refactor finding limits for icmp with binop; NFCISanjay Patel2017-01-231-105/+146
| | | | llvm-svn: 292812
* Refactor SampleProfile.cpp to move computation inside a branch. (NFC)Dehao Chen2017-01-231-2/+2
| | | | llvm-svn: 292803
* [InstCombine][X86] Add MULDQ/MULUDQ constant folding supportSimon Pilgrim2017-01-231-3/+40
| | | | llvm-svn: 292793
* Tweak ASCII art in Simplify CFG. NFCAmaury Sechet2017-01-231-1/+1
| | | | llvm-svn: 292792
* [SystemZ] Mark vector immediate load instructions with useful flags.Jonas Paulsson2017-01-232-19/+23
| | | | | | | | | Vector immediate load instructions should have the isAsCheapAsAMove, isMoveImm and isReMaterializable flags set. With them, these instruction will get hoisted out of loops. Review: Ulrich Weigand llvm-svn: 292790
* RuntimeDyldELF: add LDST128_ABS_LO12_NC relocEugene Leviant2017-01-231-0/+6
| | | | llvm-svn: 292788
* RuntimeDyldELF: add LDST8_ABS_LO12_NC and LDST16_ABS_LO12_NC relocsEugene Leviant2017-01-231-1/+13
| | | | | | Differential revision: https://reviews.llvm.org/D28863 llvm-svn: 292785
* [InstCombine][X86] MULDQ/MULUDQ undef -> zeroSimon Pilgrim2017-01-231-2/+2
| | | | | | Match generic mul behaviour so that <X x i64> multiply and muldq/muludq pattern act the same llvm-svn: 292784
* [PM] Replace the hard invalidate in JumpThreading for LVI with correctChandler Carruth2017-01-232-6/+25
| | | | | | | | | | | | | | | | | | | | | invalidation of deleted functions in GlobalDCE. This was always testing a bug really triggered in GlobalDCE. Right now we have analyses with asserting value handles into IR. As long as those remain, when *deleting* an IR unit, we cannot wait for the normal invalidation scheme to kick in even though it was designed to work correctly in the face of these kinds of deletions. Instead, the pass needs to directly handle invalidating the analysis results pointing at that IR unit. I've tought the Inliner about this and this patch teaches GlobalDCE. This will handle the asserting VH case in the existing test as well as other issues of the same fundamental variety. I've moved the test into the GlobalDCE directory and added a comment explaining what is going on. Note that we cannot simply require LVI here because LVI is too lazy. llvm-svn: 292773
* [PM] Clear any analyses for a dead function after inlining it and beforeChandler Carruth2017-01-231-2/+3
| | | | | | | | | | clearing its body. This is essential to avoid triggering asserting value handles in analyses on the function's body. I'm working on a test case for this behavior in LLVM, but Clang has a great one that managed to trigger this on all of the bots already. llvm-svn: 292770
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