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* [MSF] Default to FPM2, and always mark FPM pages allocated.Zachary Turner2018-03-291-32/+6
| | | | | | | | | | | | | | | | | | | | | | | | There are two FPMs in an MSF file, the idea being that for incremental updates you can write to the alternate one and then atomically swap them on commit. LLVM defaulted to using FPM1 on the first commit, but this differs from Microsoft's behavior which is to default to using FPM2 on the first commit. To eliminate some byte-level file differences, this patch changes LLVM's default to also be FPM2. Additionally, LLVM was trying to be "smart" about marking FPM pages allocated. In addition to marking every page belonging to the alternate FPM as unallocated, LLVM also marked pages at the end of the main FPM which were not needed as unallocated. In order to match the behavior of Microsoft-generated PDBs, we now always mark every FPM block as allocated, regardless of whether it is in the main FPM or the alt FPM, and regardless of whether or not it describes blocks which are actually in the file. This has the side benefit of simplifying our code. llvm-svn: 328812
* [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to ↵Craig Topper2018-03-2954-61/+72
| | | | | | | | | | | | CodeGen layer. Currently EVT is in the IR layer only because of Function.cpp needing a very small piece of the functionality of EVT::getEVTString(). The rest of EVT is used in codegen making CodeGen a better place for it. The previous code converted a Type* to EVT and then called getEVTString. This was only expected to handle the primitive types from Type*. Since there only a few primitive types, we can just print them as strings directly. Differential Revision: https://reviews.llvm.org/D45017 llvm-svn: 328806
* Reapply "[DWARFv5] Emit file 0 to the line table."Paul Robinson2018-03-297-71/+131
| | | | | | | | | | | | | | | | | DWARF v5 specifies that the root file (also given in the DW_AT_name attribute of the compilation unit DIE) should be emitted explicitly to the line table's list of files. This makes the line table more independent of the .debug_info section. We emit the new syntax only for DWARF v5 and later. Fixes the bug found by asan. Also XFAIL the new test for Darwin, which is stuck on DWARF v2, and fix up other tests so they stop failing on Windows. Last but not least, don't break "clang -g" of an assembler file that has .file directives in it. Differential Revision: https://reviews.llvm.org/D44054 llvm-svn: 328805
* [JumpThreading] Don't select an edge that we know we can't threadHaicheng Wu2018-03-291-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In r312664 (D36404), JumpThreading stopped threading edges into loop headers. Unfortunately, I observed a significant performance regression as a result of this change. Upon further investigation, the problematic pattern looked something like this (after many high level optimizations): while (true) { bool cond = ...; if (!cond) { <body> } if (cond) break; } Now, naturally we want jump threading to essentially eliminate the second if check and hook up the edges appropriately. However, the above mentioned change, prevented it from doing this because it would have to thread an edge into the loop header. Upon further investigation, what is happening is that since both branches are threadable, JumpThreading picks one of them at arbitrarily. In my case, because of the way that the IR ended up, it tended to pick the one to the loop header, bailing out immediately after. However, if it had picked the one to the exit block, everything would have worked out fine (because the only remaining branch would then be folded, not thraded which is acceptable). Thus, to fix this problem, we can simply eliminate loop headers from consideration as possible threading targets earlier, to make sure that if there are multiple eligible branches, we can still thread one of the ones that don't target a loop header. Patch by Keno Fischer! Differential Revision: https://reviews.llvm.org/D42260 llvm-svn: 328798
* .debug_names: Correctly align the AugmentationStringSize fieldPavel Labath2018-03-291-2/+1
| | | | | | | | | | | | | We should align the value of the field, not the overall section offset. This distinction matters if one of the debug_names contributions is not of size which is a multiple of four. The dwarf producers may choose to emit rounded contributions, but they are not required to do so. In the latter case, without this patch we would corrupt the parsing state, as we would adjust the offset even if subsequent contributions contained correctly rounded augmentation strings. llvm-svn: 328796
* [Hexagon] Add support to handle bit-reverse load intrinsicsKrzysztof Parzyszek2018-03-294-30/+153
| | | | | | Patch by Sumanth Gundapaneni. llvm-svn: 328774
* .debug_names: Parse DW_IDX_die_offset as a referencePavel Labath2018-03-291-1/+1
| | | | | | | | | | | Before this patch we were parsing the attributes as section offsets, as that is what apple_names is doing. However, this is not correct as DWARF v5 specifies that this attribute should use the Reference form class. This also updates all the testcases (except the ones that deliberately pass a different form) to use the correct form class. llvm-svn: 328773
* [X86][SSE] Don't bother re-adding combined target shuffles to the work listSimon Pilgrim2018-03-291-65/+16
| | | | | | | | | | We are re-adding all the bitcasts, constant masks and target shuffles to the work list for no apparent gain. Found while investigating adding SimplifyDemandedVectorElts to target shuffles. Differential Revision: https://reviews.llvm.org/D44942 llvm-svn: 328771
* [Mips] Remove dead codeSimon Dardis2018-03-291-1/+0
| | | | | | | | | | | | I believe the role of ehDataReg has been replaced by MipsABIInfo::GetEhDataReg, thus removing the dead code. Patch By: Wei-Ren Chen. Reviewers: ehostunreach, sdardis Differential Revision: https://reviews.llvm.org/D44867 llvm-svn: 328767
* [LoopRotate] Restructuring LoopRotation.cpp to create Loop Rotation Pass ↵David Green2018-03-293-581/+619
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | with Loop Rotation Utility Interface The existing LoopRotation.cpp is implemented as one of loop passes instead of being a utility. The user cannot easily perform the loop rotation selectively (or on demand) under different optimization level. For example, the loop rotation is needed as part of the logic to convert a loop into a loop with bottom test for a transformation. If the loop rotation is simply added as a loop pass before the transformation, the pass is skipped if it is compiled at –O0 or if it is explicitly disabled by the user, causing the compiler to generate incorrect code. Furthermore, as a loop pass it will rotate all loops instead of just the relevant loops. We provide a utility interface for the loop rotation so that the loop rotation can be called on demand. The changeset is as follows: - Create a new file lib/Transforms/Utils/LoopRotationUtils.cpp and move the main implementation of class LoopRotate into this file. - Create a new file llvm/include/Transform/Utils/LoopRotationUtils.h with the interface LoopRotation(...). - Original LoopRotation.cpp is changed to use the utility function LoopRotation in LoopRotationUtils.cpp. This is done in the same way community did for mem-to-reg implementation. Patch by Jin Lin! Differential Revision: https://reviews.llvm.org/D44595 llvm-svn: 328766
* [Transforms] Make sure to include the c binding header when defining c ↵Benjamin Kramer2018-03-291-0/+1
| | | | | | | | | | binding functions Otherwise the definitions can't see the extern C declarations and get name mangled, making it impossible for users to call them. This breaks the Go bindings. llvm-svn: 328765
* [NFC] Fix meaningless assert in SCEVMax Kazantsev2018-03-291-2/+2
| | | | llvm-svn: 328764
* [X86] Don't pass getRegisterName from the InstPrinters into ↵Craig Topper2018-03-294-13/+13
| | | | | | | | EmitAnyX86InstComments. Just always use the function from the ATTPrinter. NFC The IntelPrinter and the ATTPrinter produce the same strings for the same input. We already use the ATTPrinter explicitly in several other places. llvm-svn: 328762
* [LLVM-C] Finish exception instruction bindingsRobert Widmann2018-03-291-2/+92
| | | | | | | | | | | | | | | | | Summary: Add support for cleanupret, catchret, catchpad, cleanuppad and catchswitch and their associated accessors. Test is modified from SimplifyCFG because it contains many diverse usages of these instructions. Reviewers: whitequark, deadalnix, echristo Reviewed By: echristo Subscribers: llvm-commits, harlanhaskins Differential Revision: https://reviews.llvm.org/D44496 llvm-svn: 328759
* [X86] Rename RIi64_NOREX tblgen class to just Ii64. Make RIi64 inherit from ↵Craig Topper2018-03-292-23/+19
| | | | | | | | it. NFC This feels more consistent with the other classes. We don't need to say _NOREX if we didn't start it with an R in the first place. llvm-svn: 328757
* [X86] Cleanup inheritance of the X86InstrFormats.td classes. NFCCraig Topper2018-03-291-2/+2
| | | | | | EVEX shouldn't inherit from VEX and EVEX_4V shouldn't inherit from VEX_4V. llvm-svn: 328756
* [MemorySSA] Turn an assert into a conditionGeorge Burgess IV2018-03-291-2/+2
| | | | | | | | | | | | Eli pointed out that variadic functions are totally a thing, so this assert is incorrect. No test-case is provided, since the only way this assert fires is if a specific DenseMap falls back to doing `isEqual` checks, and that seems fairly brittle (and requires a pyramid of growing `call void (i8, ...) @varargs(i8 0)`). llvm-svn: 328755
* [MemorySSA] Consider callsite args for hashing and equality.George Burgess IV2018-03-291-9/+20
| | | | | | | | | | | | | | We use a `DenseMap<MemoryLocOrCall, MemlocStackInfo>` to keep track of prior work when optimizing uses in MemorySSA. Because we weren't accounting for callsite arguments in either the hash code or equality tests for `MemoryLocOrCall`s, we optimized uses too aggressively in some rare cases. Fix by Daniel Berlin. Should fix PR36883. llvm-svn: 328748
* Remove some unused includes to fix layering.David Blaikie2018-03-292-2/+0
| | | | llvm-svn: 328745
* Plumb useAA through TargetTransformInfo to remove Transforms->CodeGen header ↵David Blaikie2018-03-285-17/+14
| | | | | | | | dependency Thanks to echristo for the pointers on direction. llvm-svn: 328737
* [X86][SkylakeServer] Remove checks for 'k', 'z', '_Int' and 'b' from ↵Craig Topper2018-03-281-2116/+2116
| | | | | | | | | | scheduler regexs. Most of these were optional matches at the end of the strings, but since the strings themselves are prefix matches by default you don't need to check for something optional at the end. I've left the 'b' on memory instructions where it means 'broadcast' because I'm not sure those really have the same load latency and we may need to split them explicitly in the future. llvm-svn: 328730
* [PostRAMachineSink] preserve CFGJun Bum Lim2018-03-281-0/+5
| | | | | | | | | | | | | | Summary: Mark CFG is preserved since this pass do not make any change in CFG. Reviewers: sebpop, mzolotukhin, mcrosier Reviewed By: mzolotukhin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44845 llvm-svn: 328727
* [Hexagon] Add support for "new" circular buffer intrinsicsKrzysztof Parzyszek2018-03-285-91/+280
| | | | | | | | | | | | | | | | | | | These instructions have been around for a long time, but we haven't supported intrinsics for them. The "new" versions use the CSx register for the start of the buffer instead of the K field in the Mx register. We need to use pseudo instructions for these instructions until after register allocation. The problem is that these instructions allocate a M0/CS0 or M1/CS1 pair. But, we can't generate code for the CSx set-up until after register allocation when the Mx register has been fixed for the instruction. There is a related clang patch. Patch by Brendon Cahoon. llvm-svn: 328724
* Oops - moved slightly too many things from Scalar to Utils. Move ↵David Blaikie2018-03-282-4/+4
| | | | | | LoopSimplifyCFG things back llvm-svn: 328720
* [MachineOutliner] Simplify call outlining + require valid callee save info ↵Jessica Paquette2018-03-281-31/+18
| | | | | | | | | | for call outlining This commit simplifies the call outlining logic by removing references to the Function associated with the callee. To do this, it requires that valid callee save info is available to the outliner. llvm-svn: 328719
* Transforms: Introduce Transforms/Utils.h rather than spreading the ↵David Blaikie2018-03-2837-29/+50
| | | | | | | | | declarations amongst Scalar.h and IPO.h Fixes layering - Transforms/Utils shouldn't depend on including a Scalar or IPO header, because Scalar and IPO depend on Utils. llvm-svn: 328717
* [llvm-ar] Support multiple dashed optionsPeter Collingbourne2018-03-281-9/+13
| | | | | | | | | | | | | | | This allows syntax like: $ llvm-ar -c -r -u file.a file.o This is in addition to the other formats that are already supported: $ llvm-ar cru file.a file.o $ llvm-ar -cru file.a file.o Patch by Tom Anderson! Differential Revision: https://reviews.llvm.org/D44452 llvm-svn: 328716
* [AMDGPU][MC] Added ds_add_src2_f32Dmitry Preobrazhensky2018-03-281-0/+3
| | | | | | | | | See bug 36833: https://bugs.llvm.org/show_bug.cgi?id=36833 Differential Revision: https://reviews.llvm.org/D44779 Reviewers: arsenm, artem.tamazov, timcorringham llvm-svn: 328713
* [AMDGPU][MC] Added PCK variants of image load/store instructionsDmitry Preobrazhensky2018-03-281-26/+40
| | | | | | | | | See bug 36834: https://bugs.llvm.org/show_bug.cgi?id=36834 Differential Revision: https://reviews.llvm.org/D44795 Reviewers: artem.tamazov, arsenm, timcorringham, nhaehnle llvm-svn: 328710
* [AMDGPU][MC][GFX9] Added buffer_*_format_d16_hi_xDmitry Preobrazhensky2018-03-281-0/+10
| | | | | | | | | See bug 36835: https://bugs.llvm.org/show_bug.cgi?id=36835 Differential Revision: https://reviews.llvm.org/D44825 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 328707
* [AMDGPU][MC][GFX9] Added s_scratch* instructionsDmitry Preobrazhensky2018-03-281-0/+15
| | | | | | | | | See bug 36836: https://bugs.llvm.org/show_bug.cgi?id=36836 Differential Revision: https://reviews.llvm.org/D44832 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 328704
* [X86][Btver2] Moved JWriteFCmp/JWriteFCmpY classes next to each other. NFCISimon Pilgrim2018-03-281-14/+14
| | | | | | Renamed JWriteFPAY22 to JWriteFCmpY - we've tended to avoid latency based names llvm-svn: 328701
* Revert "Reapply "[DWARFv5] Emit file 0 to the line table.""Alexander Potapenko2018-03-287-124/+71
| | | | | | | | | | | | | | | This reverts commit r328676. Commit r328676 broke the -no-integrated-as flag necessary to build Linux kernel with Clang: $ cat t.c void foo() {} $ clang -no-integrated-as -c t.c -g /tmp/t-dcdec5.s: Assembler messages: /tmp/t-dcdec5.s:8: Error: file number less than one clang-7.0: error: assembler command failed with exit code 1 (use -v to see invocation) llvm-svn: 328699
* [X86][BtVer2] Fix the number of micro opcodes for AES[ENC|DEC] and other YMM ↵Andrea Di Biagio2018-03-281-1/+4
| | | | | | | | | | | instructions. Similar to r328694. The number of micro opcodes should be 2 for those instructions. This was found when testing AVX code for BtVer2 using llvm-mca. llvm-svn: 328698
* [MSan] Introduce ActualFnStart. NFCAlexander Potapenko2018-03-281-8/+10
| | | | | | | | | | | | | This is a step towards the upcoming KMSAN implementation patch. KMSAN is going to prepend a special basic block containing tool-specific calls to each function. Because we still want to instrument the original entry block, we'll need to store it in ActualFnStart. For MSan this will still be F.getEntryBlock(), whereas for KMSAN it'll contain the second BB. llvm-svn: 328697
* Revert "[AMDGPU] For OS type AMDPAL, fixed scratch on compute shader"Tim Renouf2018-03-281-4/+2
| | | | | | | | | | | This reverts commit 0daf86291d3aa04d3cc280cd0ef24abdb0174981. It was causing an assert in test/CodeGen/AMDGPU/amdpal.ll only on a release-with-asserts build. I will resubmit the change when I have fixed that. Change-Id: If270594eba27a7dc4076bdeab3fa8e6bfda3288a llvm-svn: 328695
* [X86][BtVer2] Fix the number of micro opcodes for a bunch of YMM instructions.Andrea Di Biagio2018-03-281-0/+12
| | | | | | | | | | | | | The Jaguar backend natively supports 128-bit data types. Operations on YMM registers are split into two COPs (complex operations). Each COP consumes a slot in the dispatch group, and in the reorder buffer. The scheduling model for Jaguar should mark those instructions as `let NumMicroOps = 2`. This was found when testing AVX code for BtVer2 using llvm-mca. llvm-svn: 328694
* [MSan] Add an isStore argument to getShadowOriginPtr(). NFCAlexander Potapenko2018-03-281-38/+47
| | | | | | | | | | | | | | | | This is a step towards the upcoming KMSAN implementation patch. The isStore argument is to be used by getShadowOriginPtrKernel(), it is ignored by getShadowOriginPtrUserspace(). Depending on whether a memory access is a load or a store, KMSAN instruments it with different functions, __msan_metadata_ptr_for_load_X() and __msan_metadata_ptr_for_store_X(). Those functions may return different values for a single address, which is necessary in the case the runtime library decides to ignore particular accesses. llvm-svn: 328692
* [ARM] Support float literals under XOChristof Douma2018-03-283-3/+6
| | | | | | | | | | Follow up patch of r328313 to support the UseVMOVSR constraint. Removed some unneeded instructions from the test and removed some stray comments. Differential Revision: https://reviews.llvm.org/D44941 llvm-svn: 328691
* [RegisterCoalescing] Don't move COPY if it would interfere with another valueMikael Holmen2018-03-281-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: RegisterCoalescer::removePartialRedundancy tries to hoist B = A from BB0/BB2 to BB1: BB1: ... BB0/BB2: ---- B = A; | ... | A = B; | |------- | It does so if a number of conditions are fulfilled. However, it failed to check if B was used by any of the terminators in BB1. Since we must insert B = A before the terminators (since it's not a terminator itself), this means that we could erroneously insert a new definition of B before a use of it. Reviewers: wmi, qcolombet Reviewed By: wmi Subscribers: MatzeB, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D44918 llvm-svn: 328689
* [ORC] Fix ORC on platforms without indirection support.Lang Hames2018-03-281-1/+5
| | | | | | | | | | Previously this crashed because a nullptr (returned by createLocalIndirectStubsManagerBuilder() on platforms without indirection support) functor was unconditionally invoked. Patch by Andres Freund. Thanks Andres! llvm-svn: 328687
* AMDGPU: Really implement getFrameRegisterMatt Arsenault2018-03-271-1/+2
| | | | | | | Currently this seems to only really be used for debug info. llvm-svn: 328677
* Reapply "[DWARFv5] Emit file 0 to the line table."Paul Robinson2018-03-277-71/+124
| | | | | | | | | | | | | | | | DWARF v5 specifies that the root file (also given in the DW_AT_name attribute of the compilation unit DIE) should be emitted explicitly to the line table's list of files. This makes the line table more independent of the .debug_info section. Fixes the bug found by asan. Also XFAIL the new test for Darwin, which is stuck on DWARF v2, and fix up other tests so they stop failing on Windows. Last but not least, don't break "clang -g" of an assembler file that has .file directives in it. Differential Revision: https://reviews.llvm.org/D44054 llvm-svn: 328676
* [MachineOutliner] AArch64: Don't outline ADRPs with un-outlinable operandsJessica Paquette2018-03-271-11/+7
| | | | | | | | | If an ADRP appears with, say, a CPI operand, we shouldn't outline it. This moves the check for unsafe operands so that it occurs before the special-case for ADRPs. Also add a test for outlining ADRPs. llvm-svn: 328674
* [AMDGPU] For OS type AMDPAL, fixed scratch on compute shaderTim Renouf2018-03-271-2/+4
| | | | | | | | | | | | | | | | | | Summary: For OS type AMDPAL, the scratch descriptor is loaded from offset 0 of the GIT, whose 32 bit pointer is in s0 (s8 for gfx9 merged shaders). This commit fixes that to use offset 0x10 instead of offset 0 for a compute shader, per the PAL ABI spec. Reviewers: kzhuravl, nhaehnle, timcorringham Subscribers: kzhuravl, wdng, yaxunl, t-tye, llvm-commits, dstuttard, nhaehnle, arsenm Differential Revision: https://reviews.llvm.org/D44468 Change-Id: I93dffa647758e37f613bb5e0dfca840d82e6d26f llvm-svn: 328673
* [DWARF] Suppress split line tables more carefully.Paul Robinson2018-03-275-20/+19
| | | | | | | | | | | | | | | | If a given split type unit does not have source locations, don't have it refer to the split line table. If no split type unit refers to the split line table, don't emit the line table at all. This will save a little space on rare occasions, but also refactors things a bit to improve which class is responsible for what. Responding to review comments on r326395. Differential Revision: https://reviews.llvm.org/D44220 llvm-svn: 328670
* [CodeGen] Fixed unreachable with -print-machineinstrs and custom pseudo ↵Tim Renouf2018-03-271-1/+6
| | | | | | | | | | | | | | | | | | source value Summary: Rev 327580 "[CodeGen] Use MIR syntax for MachineMemOperand printing" broke -print-machineinstrs for us on AMDGPU, because we have custom pseudo source values, and MIR serialization does not implement that. This commit at least restores the functionality of -print-machineinstrs, even if it does not properly implement the missing MIR serialization functionality. Differential Revision: https://reviews.llvm.org/D44871 Change-Id: I44961c0b90bf6d48c01484ed7a4e466fd300db66 llvm-svn: 328668
* Initialize variable added in r328617.Sterling Augustine2018-03-271-0/+1
| | | | llvm-svn: 328667
* [X86] Add WriteFMOVMSK/WriteVecMOVMSK/WriteMMXMOVMSK scheduler classesSimon Pilgrim2018-03-2711-60/+57
| | | | | | | | Currently MOVMSK instructions use the WriteVecLogic class, which is a very poor choice given that MOVMSK involves a SSE->GPR transfer. Differential Revision: https://reviews.llvm.org/D44924 llvm-svn: 328664
* [DWARF][DWARF v5]: Adding support for dumping DW_RLE_offset_pair and ↵Wolfgang Pieb2018-03-271-19/+48
| | | | | | | | | | DW_RLE_base_address Reviewers: dblakie, aprantl Differential Revision: https://reviews.llvm.org/D44811 llvm-svn: 328662
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