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* Speculative change to try to fix older GCC versions that can't handleChandler Carruth2012-09-141-2/+2
| | | | | | the injected class name of a dependent base class here. llvm-svn: 163884
* Introduce a new SROA implementation.Chandler Carruth2012-09-144-2/+2642
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is essentially a ground up re-think of the SROA pass in LLVM. It was initially inspired by a few problems with the existing pass: - It is subject to the bane of my existence in optimizations: arbitrary thresholds. - It is overly conservative about which constructs can be split and promoted. - The vector value replacement aspect is separated from the splitting logic, missing many opportunities where splitting and vector value formation can work together. - The splitting is entirely based around the underlying type of the alloca, despite this type often having little to do with the reality of how that memory is used. This is especially prevelant with unions and base classes where we tail-pack derived members. - When splitting fails (often due to the thresholds), the vector value replacement (again because it is separate) can kick in for preposterous cases where we simply should have split the value. This results in forming i1024 and i2048 integer "bit vectors" that tremendously slow down subsequnet IR optimizations (due to large APInts) and impede the backend's lowering. The new design takes an approach that fundamentally is not susceptible to many of these problems. It is the result of a discusison between myself and Duncan Sands over IRC about how to premptively avoid these types of problems and how to do SROA in a more principled way. Since then, it has evolved and grown, but this remains an important aspect: it fixes real world problems with the SROA process today. First, the transform of SROA actually has little to do with replacement. It has more to do with splitting. The goal is to take an aggregate alloca and form a composition of scalar allocas which can replace it and will be most suitable to the eventual replacement by scalar SSA values. The actual replacement is performed by mem2reg (and in the future SSAUpdater). The splitting is divided into four phases. The first phase is an analysis of the uses of the alloca. This phase recursively walks uses, building up a dense datastructure representing the ranges of the alloca's memory actually used and checking for uses which inhibit any aspects of the transform such as the escape of a pointer. Once we have a mapping of the ranges of the alloca used by individual operations, we compute a partitioning of the used ranges. Some uses are inherently splittable (such as memcpy and memset), while scalar uses are not splittable. The goal is to build a partitioning that has the minimum number of splits while placing each unsplittable use in its own partition. Overlapping unsplittable uses belong to the same partition. This is the target split of the aggregate alloca, and it maximizes the number of scalar accesses which become accesses to their own alloca and candidates for promotion. Third, we re-walk the uses of the alloca and assign each specific memory access to all the partitions touched so that we have dense use-lists for each partition. Finally, we build a new, smaller alloca for each partition and rewrite each use of that partition to use the new alloca. During this phase the pass will also work very hard to transform uses of an alloca into a form suitable for promotion, including forming vector operations, speculating loads throguh PHI nodes and selects, etc. After splitting is complete, each newly refined alloca that is a candidate for promotion to a scalar SSA value is run through mem2reg. There are lots of reasonably detailed comments in the source code about the design and algorithms, and I'm going to be trying to improve them in subsequent commits to ensure this is well documented, as the new pass is in many ways more complex than the old one. Some of this is still a WIP, but the current state is reasonbly stable. It has passed bootstrap, the nightly test suite, and Duncan has run it successfully through the ACATS and DragonEgg test suites. That said, it remains behind a default-off flag until the last few pieces are in place, and full testing can be done. Specific areas I'm looking at next: - Improved comments and some code cleanup from reviews. - SSAUpdater and enabling this pass inside the CGSCC pass manager. - Some datastructure tuning and compile-time measurements. - More aggressive FCA splitting and vector formation. Many thanks to Duncan Sands for the thorough final review, as well as Benjamin Kramer for lots of review during the process of writing this pass, and Daniel Berlin for reviewing the data structures and algorithms and general theory of the pass. Also, several other people on IRC, over lunch tables, etc for lots of feedback and advice. llvm-svn: 163883
* Remove silly dead store. Patch by Ettl Martin.Duncan Sands2012-09-141-2/+1
| | | | llvm-svn: 163882
* mips16 fixes.Akira Hatanaka2012-09-142-2/+16
| | | | | | | | | 1. Add MoveR3216 2. Correct spelling for Move32R16 Patch by Reed Kotler. llvm-svn: 163869
* Fix both the test for zero and what we do if we have a zero forEric Christopher2012-09-131-1/+4
| | | | | | | | umulo legalization. Fixes PR13839 llvm-svn: 163856
* Reformat, remove a couple unused variables and move some variablesEric Christopher2012-09-131-8/+8
| | | | | | closer to where they're needed. llvm-svn: 163855
* Assembler: Darwin variables defined via .set are no-dead-strip.Jim Grosbach2012-09-132-4/+9
| | | | | | | | For gas compatibility. rdar://12219394 llvm-svn: 163854
* MachO: Correctly mark symbol-difference variables as N_ABS.Jim Grosbach2012-09-131-5/+30
| | | | | | | | | | | .set a, b - c + CONSTANT d = b - c + CONSTANT Both 'a' and 'd' should be marked as absolute symbols (N_ABS). rdar://12219394 llvm-svn: 163853
* Handle the new !tbaa.struct metadata tags when converting a memcpy into scalarDan Gohman2012-09-131-0/+17
| | | | | | loads and stores. llvm-svn: 163844
* Better const handling for RuntimeDyld and MCJIT.Jim Grosbach2012-09-133-4/+5
| | | | | | mapSectionAddress() wasn't consistent. llvm-svn: 163843
* Fix commentMichael Liao2012-09-131-1/+1
| | | | llvm-svn: 163835
* Add wider vector/integer support for PR12312Michael Liao2012-09-132-100/+103
| | | | | | | | - Enhance the fix to PR12312 to support wider integer, such as 256-bit integer. If more than 1 fully evaluated vectors are found, POR them first followed by the final PTEST. llvm-svn: 163832
* Enhance type legalization on bitcast from vector to integerMichael Liao2012-09-131-5/+34
| | | | | | | | - Find a legal vector type before casting and extracting element from it. - As the new vector type may have more than 2 elements, build the final hi/lo pair by BFS pairing them from bottom to top. llvm-svn: 163830
* Fix the TCRETURNmi64 bug differently.Jakob Stoklund Olesen2012-09-131-2/+21
| | | | | | | | | | Add a PatFrag to match X86tcret using 6 fixed registers or less. This avoids folding loads into TCRETURNmi64 using 7 or more volatile registers. <rdar://problem/12282281> llvm-svn: 163819
* Extract code for reducing a type to a single value type into a helper function.Dan Gohman2012-09-131-15/+21
| | | | llvm-svn: 163817
* Define an official slot for the new !tbaa.struct metadata tag.Dan Gohman2012-09-131-0/+5
| | | | llvm-svn: 163815
* mips16: When copying operands in a conditional branch instruction, allow forAkira Hatanaka2012-09-131-3/+9
| | | | | | | | immediate operands to be copied. Patch by Reed Kotler. llvm-svn: 163811
* Revert r163761 "Don't fold indexed loads into TCRETURNmi64."Jakob Stoklund Olesen2012-09-133-39/+1
| | | | | | The patch caused "Wrong topological sorting" assertions. llvm-svn: 163810
* MemCpyOpt: When forming a memset from stores also take GEP constexprs into ↵Benjamin Kramer2012-09-131-3/+3
| | | | | | | | account. This is common when storing to global variables. llvm-svn: 163809
* Fix an 80 char line limit.Nadav Rotem2012-09-131-1/+2
| | | | llvm-svn: 163808
* Rename the flag which protects from escaped allocas, which may come from ↵Nadav Rotem2012-09-131-5/+12
| | | | | | bugs in user code or in the compiler. Also, dont assert if the protection is not enabled. llvm-svn: 163807
* Unify the emission of the calling conventions into a single function to ↵Micah Villmow2012-09-131-42/+27
| | | | | | reduce code duplication. llvm-svn: 163805
* This patch introduces A15 as a target in LLVM.Silviu Baranga2012-09-139-30/+41
| | | | llvm-svn: 163803
* Fix a dagcombine optimization. The optimization attempts to optimize a ↵Nadav Rotem2012-09-131-1/+2
| | | | | | | | | | | bitcast of fneg to integers by xoring the high-bit. This fails if the source operand is a vector because we need to negate each of the elements in the vector. Fix rdar://12281066 PR13813. llvm-svn: 163802
* Fix a typo.Nadav Rotem2012-09-131-1/+1
| | | | llvm-svn: 163801
* Use Nick's suggestion of storing a large NULL into the GV instead of memset, ↵Bill Wendling2012-09-131-18/+10
| | | | | | which requires TargetData. llvm-svn: 163799
* Stack Coloring: We have code that checks that all of the uses of allocasNadav Rotem2012-09-131-5/+17
| | | | | | | | | | | | | are within the lifetime zone. Sometime legitimate usages of allocas are hoisted outside of the lifetime zone. For example, GEPS may calculate the address of a member of an allocated struct. This commit makes sure that we only check (abort regions or assert) for instructions that read and write memory using stack frames directly. Notice that by allowing legitimate usages outside the lifetime zone we also stop checking for instructions which use derivatives of allocas. We will catch less bugs in user code and in the compiler itself. llvm-svn: 163791
* Fix Doxygen issues:Dmitri Gribenko2012-09-131-1/+4
| | | | | | | | * wrap code blocks in \code ... \endcode; * refer to parameter names in paragraphs correctly (\arg is not what most people want -- it starts a new paragraph). llvm-svn: 163790
* Add a new compression type to ModRM table that detects when the memory modRM ↵Craig Topper2012-09-132-0/+9
| | | | | | byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. llvm-svn: 163774
* MCJIT: relocation addends encoded in the target aren't quite so easy.Jim Grosbach2012-09-131-1/+6
| | | | | | | | | | The assumption that the target address for the relocation will always be sizeof(intptr_t) and will always contain an addend for the relocation value is very wrong. Default to no addend for now. rdar://12157052 llvm-svn: 163765
* MCJIT: Make sure to mask off non-type-field bits.Jim Grosbach2012-09-131-1/+1
| | | | | | | When comparing to the macho relocation type enum value, make sure we're only comparing against the bits in the RelType that correspond. llvm-svn: 163764
* MCJIT: Pass the i386 MachO relocation type properly.Jim Grosbach2012-09-131-1/+1
| | | | llvm-svn: 163763
* Don't fold indexed loads into TCRETURNmi64.Jakob Stoklund Olesen2012-09-133-1/+39
| | | | | | | | | | | | | We don't have enough GR64_TC registers when calling a varargs function with 6 arguments. Since %al holds the number of vector registers used, only %r11 is available as a scratch register. This means that addressing modes using both base and index registers can't be folded into TCRETURNmi64. <rdar://problem/12282281> llvm-svn: 163761
* Introduce the __llvm_gcov_flush function.Bill Wendling2012-09-131-6/+56
| | | | | | | | | | This function writes out the current values of the counters and then resets them. This can be used similarly to the __gcov_flush function to sync the counters when need be. For instance, in a situation where the application doesn't exit. <rdar://problem/12185886> llvm-svn: 163757
* Recommit, with fixes:Eric Christopher2012-09-124-1/+48
| | | | | | | | | | | Add some support for dealing with an object pointer on arguments. Part of rdar://9797999 which now supports adding the object pointer attribute to the subprogram as it should. llvm-svn: 163754
* Misc.Akira Hatanaka2012-09-121-3/+6
| | | | | | | | | 1. Remove RA from list of allocatable registers 2. Enable d,y,r constraint inline assembly instructions Patch by Reed Kotler. llvm-svn: 163753
* Fix PR11985Michael Liao2012-09-1211-30/+54
| | | | | | | | | | | - BlockAddress has no support of BA + offset form and there is no way to propagate that offset into machine operand; - Add BA + offset support and a new interface 'getTargetBlockAddress' to simplify target block address forming; - All targets are modified to use new interface and X86 backend is enhanced to support BA + offset addressing. llvm-svn: 163743
* Detect overflow in the path count computation. rdar://12277446.Dan Gohman2012-09-121-0/+13
| | | | llvm-svn: 163739
* Remove an overly-aggressive assertion. The code following this assertion ↵Owen Anderson2012-09-121-2/+0
| | | | | | already knows how to handle the case where DstRC was NULL, so it's not actually protecting us from anything, and this pattern can come up when using unknown_class operands in the SelectionDAG. llvm-svn: 163736
* Delete dead code.Jakob Stoklund Olesen2012-09-121-36/+0
| | | | llvm-svn: 163735
* Revert "Add some support for dealing with an object pointer on arguments."Eric Christopher2012-09-124-40/+0
| | | | | | This should be done on the subprogram, not the variable itself. llvm-svn: 163734
* [ms-inline asm] Make the operand size directives case insensitive.Chad Rosier2012-09-121-8/+9
| | | | llvm-svn: 163729
* PGO: preserve branch-weight metadata when removing a case which jumpsManman Ren2012-09-121-0/+22
| | | | | | to the default target. llvm-svn: 163724
* Fix a couple of Doxygen comment issues pointed out by -Wdocumentation.Dmitri Gribenko2012-09-122-2/+2
| | | | llvm-svn: 163721
* Enable exceptions handling on PPC64 now that cr misaligned spillingRoman Divacky2012-09-121-2/+1
| | | | | | was fixed in r163713. llvm-svn: 163715
* This patch corrects logic in PPCFrameLowering for save and restore of ↵Roman Divacky2012-09-124-74/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | nonvolatile condition register fields across calls under the SVR4 ABIs. * With the 64-bit ABI, the save location is at a fixed offset of 8 from the stack pointer. The frame pointer cannot be used to access this portion of the stack frame since the distance from the frame pointer may change with alloca calls. * With the 32-bit ABI, the save location is just below the general register save area, and is accessed via the frame pointer like the rest of the save areas. This is an optional slot, so it must only be created if any of CR2, CR3, and CR4 were modified. * For both ABIs, save/restore logic is generated only if one of the nonvolatile CR fields were modified. I also took this opportunity to clean up an extra FIXME in PPCFrameLowering.h. Save area offsets for 32-bit GPRs are meaningless for the 64-bit ABI, so I removed them for correctness and efficiency. Fixes PR13708 and partially also PR13623. It lets us enable exception handling on PPC64. Patch by William J. Schmidt! llvm-svn: 163713
* Add support for AMD Geode.Roman Divacky2012-09-122-0/+2
| | | | llvm-svn: 163710
* Fix constant folding through bitcasts by no longer relying on undefined ↵Kristof Beyls2012-09-121-2/+2
| | | | | | | | | | | | behaviour (converting NaN values between float and double). SelectionDAG::getConstantFP(double Val, EVT VT, bool isTarget); should not be used when Val is not a simple constant (as the comment in SelectionDAG.h indicates). This patch avoids using this function when folding an unknown constant through a bitcast, where it cannot be guaranteed that Val will be a simple constant. llvm-svn: 163703
* Add a flag to disable the code that looks for allocas which escaped the ↵Nadav Rotem2012-09-121-6/+18
| | | | | | lifetime regions. This is useful for debugging. No testcase because without this check we fail on assertions when finding escaped allocas. llvm-svn: 163702
* Add a function computeRegisterLiveness() to MachineBasicBlock. This uses ↵James Molloy2012-09-121-0/+74
| | | | | | | | analyzePhysReg() from r163694 to heuristically try and determine the liveness state of a physical register upon arrival at a particular instruction in a block. The search for liveness is clipped to a specific number of instructions around the target MachineInstr, in order to avoid degenerating into an O(N^2) algorithm. It tries to use various clues about how instructions around (both before and after) a given MachineInstr use that register, to determine its state at the MachineInstr. llvm-svn: 163695
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