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* Remove "gpr0 allocation" from the PPC README TODO listHal Finkel2013-03-271-1/+0
| | | | | | As Chris pointed out, post r178123, this is now done! llvm-svn: 178165
* Don't try to generate crash diagnostics if we had an I/O failure. It's veryChad Rosier2013-03-271-1/+1
| | | | | | | likely the crash diagnostics generation will fail as well. Part of rdar://13296693 llvm-svn: 178163
* Add a boolean parameter to the llvm::report_fatal_error() function to indicatedChad Rosier2013-03-271-8/+8
| | | | | | | if crash diagnostics should be generated. By default this is enabled. Part of rdar://13296693 llvm-svn: 178161
* Specutively revert r178130.Bill Wendling2013-03-271-44/+29
| | | | | | | | | | | | | | | | | | | This may be causing a failure on some buildbots: Referencing function in another module! tail call fastcc void @_ZL11EvaluateOpstPtRj(i16 zeroext %17, i16* %Vals, i32* %NumVals), !dbg !219 Referencing function in another module! tail call fastcc void @_ZL11EvaluateOpstPtRj(i16 zeroext %19, i16* %Vals, i32* %NumVals), !dbg !221 Broken module found, compilation aborted! Stack dump: 0. Running pass 'Function Pass Manager' on module 'ld-temp.o'. 1. Running pass 'Module Verifier' on function '@_ZL11EvaluateOpstPtRj' clang: error: unable to execute command: Illegal instruction: 4 clang: error: linker command failed due to signal (use -v to see invocation) <rdar://problem/13516485> llvm-svn: 178156
* Fix commentDavid Blaikie2013-03-271-1/+1
| | | | llvm-svn: 178155
* R600/SI: add SETO/SETUO patternsChristian Konig2013-03-271-0/+14
| | | | | | | | 6 more piglit tests. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178145
* Silence warning about mixing || in &&, fix up 80-cols.Benjamin Kramer2013-03-271-1/+3
| | | | llvm-svn: 178144
* Print PPC ZERO as 0 (not r0) even on DarwinHal Finkel2013-03-271-2/+2
| | | | | | | It seems that the Darwin PPC assembler requires r0 to be written as 0 when it means 0 (at least in lwarx/stwcx.). Fixes PR15605. llvm-svn: 178142
* Switch to LLVM support function abs64 to keep VS2008 happy.Tim Northover2013-03-272-4/+4
| | | | llvm-svn: 178141
* Fix target-customized spilling in the register scavengerHal Finkel2013-03-271-1/+1
| | | | | | | | | | | | This is a follow-up to r178073 (which should actually make target-customized spilling work again). I still don't have a regression test for this (but it would be good to have one; Thumb 1 and Mips16 use this callback as well). Patch by Richard Sandiford. llvm-svn: 178137
* Enabling the generation of dependency breakers for partial updates on ↵Silviu Baranga2013-03-272-9/+6
| | | | | | Cortex-A15. Also fixing a small bug in getting the update clearence for VLD1LNd32. llvm-svn: 178134
* Hexagon: Disable optimizations at O0.Jyotsna Verma2013-03-271-18/+31
| | | | llvm-svn: 178132
* Improve performance of LinkModules when linking with modules with large ↵James Molloy2013-03-271-29/+44
| | | | | | numbers of functions which link lazily. Instead of creating and destroying function prototypes irrespective of if they are used, only create them if they are used. llvm-svn: 178130
* R600/SI: add cummuting of rev instructionsChristian Konig2013-03-275-34/+87
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178127
* R600/SI: add mulhu/mulhs patternsChristian Konig2013-03-273-2/+20
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178126
* R600/SI: add srl/sha patterns for SIChristian Konig2013-03-271-2/+6
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178125
* Allocate r0 on PPCHal Finkel2013-03-271-2/+0
| | | | | | | The R0 register can now be allocated because instructions that cannot use R0 as a GPR have been appropriately marked. llvm-svn: 178123
* Use the PPC no-r0 class on the TOC LD pseudosHal Finkel2013-03-271-2/+2
| | | | | | | | | | The register parameter in these instructions becomes the base register in an r+i ld instruction (and, thus, cannot be r0). This is not yet testable because we don't yet allocate r0 (and even then any test would be very fragile). llvm-svn: 178121
* Apply the no-r0 register class to the PPC SELECT_CC_I[4|8] pseudosHal Finkel2013-03-271-2/+7
| | | | | | | | | | Either operand of these pseudo instructions can be transformed into the first operand of an isel instruction (and this operand cannot be r0). This is not yet testable because we don't yet allocate r0 (and even when we do, any test would be very fragile). llvm-svn: 178119
* Apply the no-r0 class to PPC TOC ADDI[S] pseudo instructionsHal Finkel2013-03-271-9/+9
| | | | | | | | | | | | Like the addi/addis instructions themselves, these pseudo instructions also cannot have r0 as their register parameter (because it will be interpreted as the value 0). This is not yet testable because we don't yet allocate r0 (and even when we do, any regression test would be very fragile because it would depend on the register allocator heuristics). llvm-svn: 178118
* Remove the link register from the GPR classes on PowerPC.Bill Schmidt2013-03-271-2/+2
| | | | | | | | | | | | | | | Some implementation detail in the forgotten past required the link register to be placed in the GPRC and G8RC register classes. This is just wrong on the face of it, and causes several extra intersection register classes to be generated. I found this was having evil effects on instruction scheduling, by causing the wrong register class to be consulted for register pressure decisions. No code generation changes are expected, other than some minor changes in instruction order. Seven tests in the test bucket required minor tweaks to adjust to the new normal. llvm-svn: 178114
* Adding DIImportedModules to DIScopes.David Blaikie2013-03-272-62/+163
| | | | | | | | | | | | This is just the basic groundwork for supporting DW_TAG_imported_module but I wanted to commit this before pushing support further into Clang or LLVM so that this rather churny change is isolated from the rest of the work. The major churn here is obviously adding another field (within the common DIScope prefix) to all DIScopes (files, classes, namespaces, lexical scopes, etc). This should be the last big churny change needed for DW_TAG_imported_module/using directive support/PR14606. llvm-svn: 178099
* Don't spill PPC VRSAVE on non-Darwin (even in SjLj)Hal Finkel2013-03-273-1/+8
| | | | | | | | | | | | | As Bill Schmidt pointed out to me, only on Darwin do we need to spill/restore VRSAVE in the SjLj code. For non-Darwin, don't spill/restore VRSAVE (and I've added some asserts to make sure that we're not). As it turns out, we're not currently handling the Darwin case correctly (I've added a FIXME in the test case). I've tried adding various implied register definitions/uses to force the spill without success, so I'll need to address this later. llvm-svn: 178096
* Make DIBuilder::createClassType more type safe by returning DICompositeType ↵David Blaikie2013-03-261-8/+10
| | | | | | rather than DIType llvm-svn: 178091
* DebugInfo: more support for mutating DICompositeType to reduce magic number ↵David Blaikie2013-03-261-1/+8
| | | | | | usage in Clang llvm-svn: 178090
* Add a boolean parameter to the ExecuteAndWait static function to indicatedChad Rosier2013-03-261-4/+7
| | | | | | | | | | if execution failed. ExecuteAndWait returns -1 upon an execution failure, but checking the return value isn't sufficient because the wait command may return -1 as well. This new parameter is to be used by the clang driver in a subsequent commit. Part of rdar://13362359 llvm-svn: 178087
* Use the full path when outputting the `.gcda' file.Bill Wendling2013-03-261-5/+14
| | | | | | | | | | | | | | If we compile a single source program, the `.gcda' file will be generated where the program was executed. This isn't desirable, because that place may be at an unpredictable place (the program could call `chdir' for instance). Instead, we will output the `.gcda' file in the same place we output the `.gcno' file. I.e., the directory where the executable was generated. This matches GCC's behavior. <rdar://problem/13061072> & PR11809 llvm-svn: 178084
* Add XTEST codegen supportMichael Liao2013-03-264-1/+22
| | | | llvm-svn: 178083
* Add HLE target featureMichael Liao2013-03-264-1/+14
| | | | llvm-svn: 178082
* Enable SandyBridgeModel for all modern Intel P6 descendants.Jakob Stoklund Olesen2013-03-262-34/+44
| | | | | | | | | | | | All Intel CPUs since Yonah look a lot alike, at least at the granularity of the scheduling models. We can add more accurate models for processors that aren't Sandy Bridge if required. Haswell will probably need its own. The Atom processor and anything based on NetBurst is completely different. So are the non-Intel chips. llvm-svn: 178080
* Debug Info: Provide a means to update the members of a composite typeDavid Blaikie2013-03-261-0/+11
| | | | | | | | This will be used to factor out some uses of magic number operand offsets inside Clang where these fields were updated in an effort to resolve forward declarations/circular references. llvm-svn: 178078
* Restore real bit lengths on PPC register numbersHal Finkel2013-03-261-12/+12
| | | | | | | | | | As suggested by Bill Schmidt (in reviewing r178067), use the real register number bit lengths (which is self-documenting, and prevents using illegal numbers), and set only the relevant bits in HWEncoding (which defaults to 0). No functionality change intended. llvm-svn: 178077
* Fix the register scavenger for targets that provide custom spillingHal Finkel2013-03-261-2/+5
| | | | | | | | | | | As pointed out by Richard Sandiford, my recent updates to the register scavenger broke targets that use custom spilling (because the new code assumed that if there were no valid spill slots, than spilling would be impossible). I don't have a test case, but it should be possible to create one for Thumb 1, Mips 16, etc. llvm-svn: 178073
* PPC: Use HWEncoding and TRI->getEncodingValueHal Finkel2013-03-268-100/+31
| | | | | | | | | | | As pointed out by Jakob, we don't need to maintain a separate register-numbering table. Instead we should let TableGen generate the table for us from the information (already present) in PPCRegisterInfo.td. TRI->getEncodingValue is now used to access register-encoding values. No functionality change intended. llvm-svn: 178067
* R600/SIMCCodeEmitter.cpp: Prune a couple of unused members, STI and Ctx. ↵NAKAMURA Takumi2013-03-261-3/+1
| | | | | | [-Wunused-private-field] llvm-svn: 178065
* Use multiple virtual registers in PPC CR spillingHal Finkel2013-03-262-25/+35
| | | | | | | | | | | | Now that the register scavenger can support multiple spill slots, and PEI can use virtual-register-based scavenging for multiple simultaneous registers, we can use a virtual register for the transfer register in the CR spilling code. This should eliminate the last place (outside of the prologue/epilogue) where we depend on the unconditional availability of the r0 register. We will soon be able to allocate it (in a somewhat restricted sense) as a GPR. llvm-svn: 178060
* Update PPCRegisterInfo's use of virtual registers to be SSAHal Finkel2013-03-261-3/+5
| | | | | | | | | | | PPC's use of PEI's virtual-register-based scavenging functionality had redefined the virtual registers (it was non-SSA). Now that PEI supports dealing with instructions with multiple virtual registers, this can be cleanup up to use multiple virtual registers and keep SSA form. No functionality change intended. llvm-svn: 178059
* Update PEI's virtual-register-based scavenging to support multiple ↵Hal Finkel2013-03-262-22/+35
| | | | | | | | | | | | | | | | | | | simultaneous mappings The previous algorithm could not deal properly with scavenging multiple virtual registers because it kept only one live virtual -> physical mapping (and iterated through operands in order). Now we don't maintain a current mapping, but rather use replaceRegWith to completely remove the virtual register as soon as the mapping is established. In order to allow the register scavenger to return a physical register killed by an instruction for definition by that same instruction, we now call RS->forward(I) prior to eliminating virtual registers defined in I. This requires a minor update to forward to ignore virtual registers. These new features will be tested in forthcoming commits. llvm-svn: 178058
* Annotate the remaining x86 instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-263-10/+10
| | | | | | | | | | Now all x86 instructions that have itinerary classes also have SchedRW lists. This is required before the new scheduling models can be used. There are still unannotated instructions remaining, but they don't have itinerary classes either. llvm-svn: 178051
* Annotate x87 and mmx instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-262-31/+71
| | | | | | | This only covers the instructions that were given itinerary classes for the Atom model. llvm-svn: 178050
* Annotate control instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-261-28/+41
| | | | | | | This could definitely be more granular. I am not sure if it makes a difference. llvm-svn: 178049
* Annotate the rest of X86InstrInfo.td with SchedRW lists.Jakob Stoklund Olesen2013-03-261-27/+43
| | | | llvm-svn: 178048
* BasicAA: Only query twice if the result of the more general query was MayAliasArnold Schwaighofer2013-03-261-5/+5
| | | | | | | | | | | | | | This is a compile time optimization. Before the patch we would do two traversals on each call to aliasGEP - one with a set size parameter one with UnknownSize. We can do better by first checking the result of the alias query with UnknownSize. Only if this one returns MayAlias do we query a second time using size and type. This recovers an about 7% compile time regression on spec/ammp. radar://12349960 llvm-svn: 178045
* Add PREFETCHW codegen supportMichael Liao2013-03-265-5/+21
| | | | | | - Add 'PRFCHW' feature defined in AVX2 ISA extension llvm-svn: 178040
* Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.Jyotsna Verma2013-03-262-186/+48
| | | | llvm-svn: 178032
* Make InstCombineCasts.cpp:OptimizeIntToFloatBitCast endian safe.Ulrich Weigand2013-03-261-1/+9
| | | | | | | | | | | | | The OptimizeIntToFloatBitCast converts shift-truncate sequences into extractelement operations. The computation of the element index to be used in the resulting operation is currently only correct for little-endian targets. This commit fixes the element index computation to be correct for big-endian targets as well. If the target byte order is unknown, the optimization cannot be performed at all. llvm-svn: 178031
* Hexagon: Remove HexagonMCInst.h file. It has been replaced with ↵Jyotsna Verma2013-03-261-41/+0
| | | | | | MCTargetDesc/HexagonMCInst.h. llvm-svn: 178030
* Revert ARM Scheduler Model: Add resources instructions, map resourcesArnold Schwaighofer2013-03-264-70/+24
| | | | | | | | | | | | | This reverts commit r177968. It is causing failures in a local build bot. "fatal error: error in backend: Expected a variant SchedClass" Original commit message: Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. llvm-svn: 178028
* Remove default case from fully covered switch.Benjamin Kramer2013-03-261-1/+1
| | | | llvm-svn: 178025
* R600/SI: improve post ISel foldingChristian Konig2013-03-261-31/+43
| | | | | | | Not only fold immediates, but avoid unnecessary copies as well. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178024
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