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* Basic blocks typically have few predecessors. Use a SmallDenseMap toChris Lattner2013-10-141-3/+3
| | | | | | avoid a heap allocation when this is the case. llvm-svn: 192602
* [msan] Instrument x86.*_cvt* intrinsics.Evgeniy Stepanov2013-10-141-28/+149
| | | | | | | | Currently MSan checks that arguments of *cvt* intrinsics are fully initialized. That's too much to ask: some of them only operate on lower half, or even quarter, of the input register. llvm-svn: 192599
* [AArch64] Add support for NEON scalar integer compare instructions.Chad Rosier2013-10-141-0/+78
| | | | llvm-svn: 192596
* Add Cortex-A57 supportBernard Ogden2013-10-142-1/+10
| | | | llvm-svn: 192591
* Add subtarget feature support for Cortex-A53Bernard Ogden2013-10-143-4/+18
| | | | | | | Some previous implicit defaults have changed, for example FP and NEON are now on by default. llvm-svn: 192590
* [mips][msa] Direct Object Emission support for BIT instructions.Matheus Almeida2013-10-142-74/+130
| | | | | | | | | | | | | | | | | | List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
* [mips][msa] Direct Object Emission support for VEC instructions.Matheus Almeida2013-10-142-67/+88
| | | | | | | List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
* [mips][msa] Direct Object Emission of INSVE.{b,h,w,d}.Matheus Almeida2013-10-141-14/+18
| | | | llvm-svn: 192587
* [mips][msa] Direct Object Emission for the majority of the ELM instructions.Matheus Almeida2013-10-142-31/+109
| | | | | | | | | | List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
* [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.Matheus Almeida2013-10-143-14/+175
| | | | | | | | | INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192582
* [msan] Fix handling of scalar select of vectors.Evgeniy Stepanov2013-10-141-4/+4
| | | | llvm-svn: 192575
* Fixed a bug in dynamic allocation memory on stack.Elena Demikhovsky2013-10-142-8/+15
| | | | | | | | The alignment of allocated space was wrong, see Bugzila 17345. Done by Zvi Rackover <zvi.rackover@intel.com>. llvm-svn: 192573
* Create classes to reduce the size of the tablegen entries for the CRC32 ↵Craig Topper2013-10-141-66/+33
| | | | | | instructions. llvm-svn: 192568
* Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps ↵Craig Topper2013-10-144-83/+102
| | | | | | instructions to parse either GR32 or GR64 without resorting to duplicating instructions. llvm-svn: 192567
* Add disassembler support for SSE4.1 register/register form of PEXTRW. There ↵Craig Topper2013-10-141-0/+7
| | | | | | is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding. llvm-svn: 192566
* Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the ↵Craig Topper2013-10-141-2/+10
| | | | | | disassembler tables. Add PINSRWrr64i to complement the AVX version. llvm-svn: 192565
* Windows: Fix a typo in an assertDavid Majnemer2013-10-141-6/+3
| | | | llvm-svn: 192564
* Don't use 64-bit versions of MOVMSKPD in CodeGen. The instructions only ↵Craig Topper2013-10-141-4/+8
| | | | | | produce a 1-bit result so we can just use SUBREG_TO_REG to extend the 32-bit versions. llvm-svn: 192562
* Windows: Don't bother with pinning Kernel32.dllDavid Majnemer2013-10-141-3/+1
| | | | | | We don't delay load it so it shouldn't be going anywhere. llvm-svn: 192561
* MC: Don't assume incoming StringRef's are null terminated.Will Dietz2013-10-132-7/+2
| | | | | | | | | | This can happen when processing command line arguments, which are often stored as std::string's and later turned into StringRef's via std::string::data(). Unfortunately this is not guaranteed to return a null-terminated string until C++11, causing breakage on platforms that don't do this. llvm-svn: 192558
* R600: improve dump of S_WAITCNTVincent Lejeune2013-10-133-1/+21
| | | | llvm-svn: 192557
* R600/SI: Add SinkingPass before ISelVincent Lejeune2013-10-131-0/+1
| | | | llvm-svn: 192556
* R600/SI: Support byval argumentsVincent Lejeune2013-10-132-2/+8
| | | | llvm-svn: 192555
* R600: Use masked read sel for texture instructionsVincent Lejeune2013-10-131-0/+5
| | | | llvm-svn: 192554
* R600: fix swizzle exportVincent Lejeune2013-10-131-5/+9
| | | | llvm-svn: 192553
* R600: Clear the VPM bit of export instructions.Vincent Lejeune2013-10-131-4/+4
| | | | | | | It makes apparently no change it to set this bit or not but the docs recommand to left it cleared. llvm-svn: 192552
* Windows: Use GetModuleHandleEx instead of LoadLibraryDavid Majnemer2013-10-131-2/+2
| | | | | | | | | | | | | | | | | | | We were using an anti-pattern of: - LoadLibrary - GetProcAddress - FreeLibrary This is problematic because of several reasons: - We are holding on to pointers into a library we just unloaded. - Calling LoadLibrary results in an increase in the reference count of the library in question and any libraries that it depends on and so-on and so-forth. This is none too quick. Instead, use GetModuleHandleEx with GET_MODULE_HANDLE_EX_FLAG_PIN. This is done because because we didn't bring the reference for the library into existence and therefor shouldn't count on it being around later. llvm-svn: 192550
* TargetLowering: Don't index into empty string.Will Dietz2013-10-131-1/+1
| | | | | | (This is triggered by current lit tests) llvm-svn: 192549
* SLPVectorizer: Sort PHINodes based on their opcodeArnold Schwaighofer2013-10-121-23/+44
| | | | | | | | | | | | | | Before this patch we relied on the order of phi nodes when we looked for phi nodes of the same type. This could prevent vectorization of cases where there was a phi node of a second type in between phi nodes of some type. This is important for vectorization of an internal graphics kernel. On the test suite + external on x86_64 (and on a run on armv7s) it showed no impact on either performance or compile time. radar://15024459 llvm-svn: 192537
* LoopVectorize: Add missing INITIALIZE_PASS_DEPENDENCY macrosTobias Grosser2013-10-121-0/+3
| | | | | Contributed-by: Peter Zotov <whitequark@whitequark.org> llvm-svn: 192536
* Remove more filters from the disassembler. Mark some AVX512 instructions as ↵Craig Topper2013-10-121-0/+6
| | | | | | CodeGenOnly. llvm-svn: 192525
* R600: Store disassembly in a special ELF section when feature +DumpCode is ↵Tom Stellard2013-10-123-14/+83
| | | | | | | | | enabled. Patch by: Jay Cornwall Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 192523
* Mark some more instructions as CodeGenOnly. Remove filters from the ↵Craig Topper2013-10-121-17/+19
| | | | | | disassembler. llvm-svn: 192522
* For Mips16, start to consolidate all forms of 32 bit literal loading so thatReed Kotler2013-10-121-3/+1
| | | | | | they can be better handled and optimized in the Mips16 constant island code. llvm-svn: 192520
* Add missing #include's to cctype when using isdigit/alpha/etc.Will Dietz2013-10-126-0/+7
| | | | llvm-svn: 192519
* Debug Info: remove form from function addDIEEntry.Manman Ren2013-10-113-26/+17
| | | | | | | | | The form must be a reference form in addDIEEntry. Which reference form to use will be decided by the callee. No functionality change. llvm-svn: 192517
* Adding multiple object support to MCJIT EH frame handlingAndrew Kaylor2013-10-119-59/+123
| | | | llvm-svn: 192504
* Fix typoMatt Arsenault2013-10-111-1/+1
| | | | llvm-svn: 192499
* fConversion: Attempt #2 at fixing the MSVC build.Benjamin Kramer2013-10-111-2/+2
| | | | llvm-svn: 192492
* IfConversion: Try to unbreak the MSVC build.Benjamin Kramer2013-10-111-1/+1
| | | | llvm-svn: 192487
* Mips: Disassemble sign-extended 64 bit immediates properly.Benjamin Kramer2013-10-111-1/+3
| | | | | | This doesn't change the meaning of the output, but makes look right. PR17539. llvm-svn: 192483
* Remove kill flags after if conversion if necessaryMatthias Braun2013-10-111-66/+89
| | | | | | | | | | | | | | | | | | | When if converting something like: true: ... = R0<kill> false: ... = R0<kill> then the instructions of the true block must not have a <kill> flag anymore, as the instruction of the false block follow and do still read the R0 value. Specifically this patch determines the set of register live-in in the false block (possibly after simulating the liveness changes of the duplicated instructions). Each of these live-in registers mustn't be killed. llvm-svn: 192482
* [DAGCombiner] Reapply load slicing (192471) with a test that explicitly set ↵Quentin Colombet2013-10-111-2/+574
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sse4.2 support. This should fix the buildbots. Original commit message: [DAGCombiner] Slice a big load in two loads when the element are next to each other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> llvm-svn: 192476
* [DAGCombiner] Revert load slicing (r192471), until I figure out why it fails ↵Quentin Colombet2013-10-111-574/+2
| | | | | | on ubuntu. llvm-svn: 192474
* [DAGCombiner] Slice a big load in two loads when the element are next to eachQuentin Colombet2013-10-111-2/+574
| | | | | | | | | | | | | | | | | | | | | | | | other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> llvm-svn: 192471
* Better info when debugging vectorizerRenato Golin2013-10-111-6/+5
| | | | llvm-svn: 192460
* [ARM] Fix FP ABI attributes with no VFP enabled.Amara Emerson2013-10-111-14/+12
| | | | llvm-svn: 192458
* fix typo in commentMatthias Braun2013-10-111-1/+1
| | | | llvm-svn: 192455
* This reverts 192447 because of compiler warning generated on darwin build.Matheus Almeida2013-10-113-174/+14
| | | | llvm-svn: 192451
* This reverts r192449 because of compiler warning generated on darwin build.Matheus Almeida2013-10-112-109/+31
| | | | llvm-svn: 192450
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