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* AArch64/ARM64: port across stub handling for ELF C++ exceptions.Tim Northover2014-04-162-4/+36
| | | | | | | | The most important part here is that we should actuall emit the stubs we refer to in the exception table, but as a side issue this uses more sensible & GCC compatible representations for some of the bits of information. llvm-svn: 206380
* ARM64: use 32-bit moves for constants where possible.Tim Northover2014-04-162-8/+24
| | | | | | | | | | | | If we know that a particular 64-bit constant has all high bits zero, then we can rely on the fact that 32-bit ARM64 instructions automatically zero out the high bits of an x-register. This gives the expansion logic less constraints to satisfy and so sometimes allows it to pick better sequences. Came up while porting test/CodeGen/AArch64/movw-consts.ll: this will allow a 32-bit MOVN to be used in @test8 soon. llvm-svn: 206379
* ARM64: use the integrated assembler on ELF.Tim Northover2014-04-161-0/+2
| | | | llvm-svn: 206378
* [mips] Emit '.set nomicromips' before a function's entry labelMatheus Almeida2014-04-161-3/+2
| | | | | | | | | | | if not in micromips mode. The test (elf_st_other.ll) was renamed as the name and description didn't make sense as the test wasn't checking any symbol table entry. Differential Revision: http://reviews.llvm.org/D3346 llvm-svn: 206377
* Fixing a compile error in debug versions of MSVC. It seems that the ↵Aaron Ballman2014-04-161-1/+2
| | | | | | range-based for loop is confused by the DEBUG macro expansion unless a compound statement is used. llvm-svn: 206376
* [mips] Correct callee saved list for the N32 ABI and enable testDaniel Sanders2014-04-161-2/+2
| | | | | | | | | | | | Summary: Depends on D3339 Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3340 llvm-svn: 206371
* ARM64: mark x7 as used when an i128 gets shunted onto the stack.Tim Northover2014-04-161-1/+1
| | | | | | | | The second half of a split i128 was ending up in x7, which is not a good thing. This is another part of PR19432. llvm-svn: 206366
* DAGCombiner: don't optimise non-existant litpool loadTim Northover2014-04-161-1/+3
| | | | | | | | | | | This particular DAG combine is designed to kick in when both ConstantFPs will end up being loaded via a litpool, however those nodes have a semi-legal status, dictated by isFPImmLegal so in some cases there wouldn't have been a litpool in the first place. Don't try to be clever in those circumstances. Picked up while merging some AArch64 tests. llvm-svn: 206365
* Simplify a static_assert so VS2013 can build itTimur Iskhodzhanov2014-04-161-2/+4
| | | | llvm-svn: 206363
* COFF: fix an off by one errorSaleem Abdulrasool2014-04-161-1/+1
| | | | | | | | | | Adjust the tests to validate the number of auxiliary entries used to store the filename. Thanks to majnemer's sharp eye for catching the missing - 1 in the round up calculation. llvm-svn: 206359
* Convert SelectionDAG::getVTList to use ArrayRefCraig Topper2014-04-1610-30/+31
| | | | llvm-svn: 206357
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-1610-34/+40
| | | | | | instead of comparing to nullptr. llvm-svn: 206356
* COFF: add support for .file symbolsSaleem Abdulrasool2014-04-162-2/+30
| | | | | | | | | | | | | Add support for emitting .file records. This is mostly a quality of implementation change (more complete support for COFF file emission) that was noticed while working on COFF file emission for Windows on ARM. A .file record is emitted as a symbol with storage class FILE (103) and the name ".file". A series of auxiliary format 4 records follow which contain the file name. The filename is stored as an ANSI string and is padded with NULL if the length is not a multiple of COFF::SymbolSize (18). llvm-svn: 206355
* Target: whitespaceSaleem Abdulrasool2014-04-161-1/+1
| | | | llvm-svn: 206353
* R600: Expand sign extension of vectors.Matt Arsenault2014-04-164-16/+47
| | | | | | | | | | | | | | Setting vector types to expand will result in scalarization on pre SI hw, as those gpus don't have vector shifts either. Expand also i32 vectors, this helps llvm make the correct decision about scalarizing the vector ops. v2: move setOperation() calls to R600ISelLowering.cpp. cleanup the SI code to make it obvious that this patch does is nop for SI Patch by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 206348
* [ARM64,C++11] Tidy up branch relaxation a bit w/ c++11.Jim Grosbach2014-04-161-32/+25
| | | | | | No functional change. llvm-svn: 206344
* ARM64: Nuke some dead code.Jim Grosbach2014-04-161-1/+0
| | | | | | Missed in previous commit. llvm-svn: 206343
* [ARM64,C++11] Clean up the ARM64 LOH collection pass.Jim Grosbach2014-04-151-155/+114
| | | | | | | | Range'ify a bunch of loops, mainly. As a result, we have a variety of objects via reference rather than by pointer, so propogate that through the various helper functions where it makes sense. llvm-svn: 206337
* R600/SI: Print code size along with used registersMatt Arsenault2014-04-152-13/+19
| | | | llvm-svn: 206336
* R600/SI: Print more immediates in hex formatMatt Arsenault2014-04-154-13/+68
| | | | | | | | | Print in decimal for inline immediates, and hex otherwise. Use hex always for offsets in addressing offsets. This approximately matches what the shader compiler does. llvm-svn: 206335
* R600/SI: Cleanup parsing of register names.Matt Arsenault2014-04-152-34/+47
| | | | | | Try to figure out the class and number of subregisters. llvm-svn: 206334
* R600/SI: Fix loads of i1Matt Arsenault2014-04-152-4/+25
| | | | llvm-svn: 206330
* RegionInfo: Do not access a value that was just moved awayTobias Grosser2014-04-151-1/+1
| | | | | | This fixes a regression introduced in r206310. llvm-svn: 206328
* Make FastISel::SelectInstruction return before target specific fast-isel codeAkira Hatanaka2014-04-151-2/+8
| | | | | | | | | | | handles Intrinsic::trap if TargetOptions::TrapFuncName is set. This fixes a bug in which the trap function was not taken into consideration when a program was compiled without optimization (at -O0). <rdar://problem/16291933> llvm-svn: 206323
* [X86] Improve the lowering of packed shifts by constant build_vector.Andrea Di Biagio2014-04-151-0/+73
| | | | | | | | | | | | | | | | | | | | | | | This patch teaches the backend how to efficiently lower logical and arithmetic packed shifts on both SSE and AVX/AVX2 machines. When possible, instead of scalarizing a vector shift, the backend should try to expand the shift into a sequence of two packed shifts by immedate count followed by a MOVSS/MOVSD. Example (v4i32 (srl A, (build_vector < X, Y, Y, Y>))) Can be rewritten as: (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>))) [with X and Y ConstantInt] The advantage is that the two new shifts from the example would be lowered into X86ISD::VSRLI nodes. This is always cheaper than scalarizing the vector into four scalar shifts plus four pairs of vector insert/extract. llvm-svn: 206316
* [ARM64] Set default CPU to generic instead of cyclone.Quentin Colombet2014-04-151-3/+1
| | | | llvm-svn: 206313
* Revert r191049/r191059 as it can produce wrong code (see PR17975).Robert Lougher2014-04-151-21/+0
| | | | | | It has already been reverted on the 3.4 branch in r196521. llvm-svn: 206311
* Use unique_ptr to manage ownership of child Regions within llvm::RegionDavid Blaikie2014-04-153-31/+35
| | | | llvm-svn: 206310
* Add lifetime markers for allocas created to hold byval arguments, make themJulien Lerouge2014-04-151-0/+1
| | | | | | appear in the InlineFunctionInfo. llvm-svn: 206308
* Split byval argument initialization so the memcpy(s) are injected at theJulien Lerouge2014-04-151-29/+42
| | | | | | beginning of the first new block after inlining. llvm-svn: 206307
* LTO: Add more loop simplification passes to LTODuncan P. N. Exon Smith2014-04-151-1/+3
| | | | | | | | | Similar to r202051, add missing loop simplification passes to the LTO optimization pipeline. Patch by Rafael Espindola. llvm-svn: 206306
* verify-di: Add back braces for MSVC compatabilityDuncan P. N. Exon Smith2014-04-151-5/+12
| | | | | | | | Fixup after r206300. <rdar://problem/15500563> llvm-svn: 206305
* verify-di: Implement DebugInfoVerifierDuncan P. N. Exon Smith2014-04-154-50/+105
| | | | | | | | | | | | | | | | | | | | | Implement DebugInfoVerifier, which steals verification relying on DebugInfoFinder from Verifier. - Adds LegacyDebugInfoVerifierPassPass, a ModulePass which wraps DebugInfoVerifier. Uses -verify-di command-line flag. - Change verifyModule() to invoke DebugInfoVerifier as well as Verifier. - Add a call to createDebugInfoVerifierPass() wherever there was a call to createVerifierPass(). This implementation as a module pass should sidestep efficiency issues, allowing us to turn debug info verification back on. <rdar://problem/15500563> llvm-svn: 206300
* verify-di: split out VerifierSupportDuncan P. N. Exon Smith2014-04-151-57/+62
| | | | | | | | | Split out assertion and output helpers from Verifier in preparation for writing the DebugInfoVerifier. <rdar://problem/15500563> llvm-svn: 206299
* Use unique_ptr to manage PassInfo instances in the PassRegistryDavid Blaikie2014-04-151-8/+4
| | | | llvm-svn: 206297
* MipsAsmParser.cpp: Fix vg_leak in MipsOperand::CreateMem(). Mem.Base is ↵NAKAMURA Takumi2014-04-151-0/+16
| | | | | | managed by k_Memory itself. llvm-svn: 206293
* MipsAsmParser::ParseRegister(): Be responsible to delete an Operand on a ↵NAKAMURA Takumi2014-04-151-0/+2
| | | | | | temporary Operands. llvm-svn: 206292
* AArch64/ARM64: add missing pattern for extending load.Tim Northover2014-04-151-0/+2
| | | | llvm-svn: 206290
* AArch64/ARM64: only mangle MOVZ/MOVN during encoding when neededTim Northover2014-04-151-0/+16
| | | | | | | | Sometimes we need emit the bits that would actually be a MOVN when producing a relocated MOVZ instruction (don't ask). But not always, a check which ARM64 got wrong until now. llvm-svn: 206289
* AArch64/ARM64: add support for large code-model jump tables.Tim Northover2014-04-152-0/+18
| | | | | | | I've left the MachO CodeGen as it is, there's a reasonable chance it should use the GOT like ConstPools, but I'm not certain. llvm-svn: 206288
* AArch64/ARM64: add patterns for various commutations of FNMADD.Tim Northover2014-04-151-0/+14
| | | | llvm-svn: 206287
* AArch64/ARM64: add half as a storage type on ARM64.Tim Northover2014-04-154-15/+19
| | | | | | | This brings it into line with the AArch64 behaviour and should open the way for certain OpenCL features. llvm-svn: 206286
* AArch64/ARM64: copy patterns for fixed-point conversionsTim Northover2014-04-152-15/+98
| | | | | | | | Code is mostly copied directly across, with a slight extension of the ISelDAGToDAG function so that it can cope with the floating-point constants being behind a litpool. llvm-svn: 206285
* ARM64: add constraints to various FastISel operationsTim Northover2014-04-151-6/+13
| | | | llvm-svn: 206284
* FastISel: constrain the RegClass of operands when emitting instructions.Tim Northover2014-04-152-27/+47
| | | | | | | | | | | ARM64 suffered multiple -verify-machineinstr failures (principally over the xsp/xzr issue) because FastISel was completely ignoring which subset of the general-purpose registers each instruction required. More fixes are coming in ARM64 specific FastISel, but this should cover the generic problems. llvm-svn: 206283
* AArch64/ARM64: add dp tests from AArch64Tim Northover2014-04-151-0/+5
| | | | llvm-svn: 206281
* ARM64AsmParser.cpp: Fix vg_leak in MC/ARM64/fp-encoding.s.NAKAMURA Takumi2014-04-151-0/+2
| | | | llvm-svn: 206279
* Optional hash symbol feature support for ARM64Stepan Dyatkovskiy2014-04-151-16/+37
| | | | | | http://reviews.llvm.org/D3328 llvm-svn: 206276
* Current definition of subtract with immediate instruction aliases uses ↵Vladimir Medic2014-04-153-49/+14
| | | | | | CodeGenOnly defined instructions and post matcher expansion methods to emit real instructions add with immediate. However, they can directly alias add with immediate instruction and remove unnecessary definitions and code in MipsAsmParser.cpp. This patch makes no change in functionality, just removes unnecessary definitions and code. llvm-svn: 206272
* [Allocator] Finally, finish nuking the redundant code that led me hereChandler Carruth2014-04-151-7/+7
| | | | | | | | | | | | | | | | by removing the MallocSlabAllocator entirely and just using MallocAllocator directly. This makes all off these allocators expose and utilize the same core interface. The only ugly part of this is that it exposes the fact that the JIT allocator has no real handling of alignment, any more than the malloc allocator does. =/ It would be nice to fix both of these to support alignments, and then to leverage that in the BumpPtrAllocator to do less over allocation in order to manually align pointers. But, that's another patch for another day. This patch has no functional impact, it just removes the somewhat meaningless wrapper around MallocAllocator. llvm-svn: 206267
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